WO2006109221A2 - Lateral bipolar transistor - Google Patents

Lateral bipolar transistor Download PDF

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Publication number
WO2006109221A2
WO2006109221A2 PCT/IB2006/051045 IB2006051045W WO2006109221A2 WO 2006109221 A2 WO2006109221 A2 WO 2006109221A2 IB 2006051045 W IB2006051045 W IB 2006051045W WO 2006109221 A2 WO2006109221 A2 WO 2006109221A2
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WO
WIPO (PCT)
Prior art keywords
region
cmos
base
bipolar transistor
emitter
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Application number
PCT/IB2006/051045
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French (fr)
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WO2006109221A3 (en
Inventor
Philippe Meunier-Beillard
Raymond J. E. Hueting
Johannes J. T. M. Donkers
Erwin Hijzen
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Nxp B.V.
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Application filed by Nxp B.V. filed Critical Nxp B.V.
Publication of WO2006109221A2 publication Critical patent/WO2006109221A2/en
Publication of WO2006109221A3 publication Critical patent/WO2006109221A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66242—Heterojunction transistors [HBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H01L29/7378—Vertical transistors comprising lattice mismatched active layers, e.g. SiGe strained layer transistors

Definitions

  • This invention relates to a lateral bipolar transistor.
  • US-6,489,665 discloses a lateral bipolar transistor comprising an emitter region, a collector region, which surrounds, but is laterally displaced from, the emitter region and a base region. Further a gate region of a CMOS device is provided comprising a polysilicon layer covering a gate oxide layer and overlying at least a portion of the base region. The gate region is in electrical communication with the base region via the gate oxide layer. By etching an opening in the gate region, a base-gate contact is formed thereby reducing the base resistance. However, the base-gate contact only connects the base region on a limited number of locations, which increases the base resistance.
  • the invention provides a CMOS-based lateral bipolar transistor with an emitter region, a collector region and a base region.
  • a first CMOS spacer is provided which is displaced from a second CMOS spacer by a space region, which formerly comprised a gate electrode.
  • the first CMOS spacer covers a portion of the emitter region
  • the second CMOS spacer covers a portion of the collector region and the space region overlies the base region.
  • the base region comprises a relatively large exposed area, on which an electrical contact is provided, which reduces the base resistance.
  • Covering the base region with a metal layer may reduce the base resistance further.
  • the CMOS-based lateral bipolar transistor is fabricated from a CMOS device on a substrate.
  • the CMOS device comprises a gate electrode in between a first and a second CMOS spacer, a gate oxide region, a bulk region and a first and a second source-drain region.
  • An emitter region is formed in the first source-drain region and in a first portion of the bulk region, which is adjacent to the first source-drain region.
  • a collector region is formed in the second source-drain region and in a second portion of the bulk region, which is adjacent to the second source-drain region.
  • a base region is formed adjacent to the emitter region and adjacent to the collector region in a third portion of the bulk region.
  • the base region is underlying the space region, and not by the gate electrode or by a portion of the gate oxide region, because these regions are removed. Therefore the base region comprises a relatively large exposed area, and by forming an electrical contact on the exposed area of the base region, the base resistance is reduced further.
  • Fig. 1 is a cross-sectional view of an embodiment of the CMOS-based lateral bipolar transistor according to the invention.
  • Figs. 2 - 7 are cross-sectional views of various stages of the fabrication of the CMOS-based lateral bipolar transistor according to an embodiment of the invention.
  • Fig. 1 illustrates a schematic cross-section of an embodiment of a CMOS- based lateral bipolar transistor.
  • the lateral bipolar transistor comprises an n-type emitter region 41, a p-type base region 43 and an n-type collector region 45, which regions are provided on a substrate region 1.
  • the base region 43 is positioned adjacent to the emitter region 41 and adjacent to the collector region 45, in a region, which is laterally defined by a first CMOS spacer 9 and a second CMOS spacer 10.
  • the gate electrode material of the former CMOS device has been removed, which advantageously exposes a relatively large portion of the base region 43, thereby enabling a reduction of the base resistance.
  • a metal layer 29 is applied and an emitter contact 31, a base contact 33 and a collector contact 35 are formed, thereby further reducing the resistance of the base, collector and emitter regions.
  • the base region 43 may also comprise SiGe, thereby creating a heterojunction bipolar transistor.
  • a bulk silicon substrate may be applied, hence in this embodiment the substrate region 1 comprises a semiconductor material, such as silicon.
  • a silicon-on- insulator (SOI) or a strained-silicon-on-insulator (SSOI) substrate may be applied, wherein the substrate region 1 comprises an insulating material, such as silicon dioxide.
  • the emitter region 41, the base region 43 and the collector region 45 are formed in the silicon, respectively strained- silicon layer that is provided on the insulating substrate region 1 of the SOI, respectively SSOI substrate.
  • the SOI and SSOI substrates provide an advantageous electrical isolation of the lateral bipolar transistor from other devices on the substrate.
  • a strained-silicon layer is applied in combination with SiGe in the base region 43 and the metal layer 29, a CMOS-based strained-silicon HEMT (High Electron Mobility Transistor) device may be formed.
  • the HEMT device may be advantageously applied in applications, which require a high gain at high frequencies.
  • Figs. 2 - 7 illustrate cross-sectional views of various stages of the fabrication of an embodiment of the invention.
  • Fig. 2 shows an NMOS device fabricated in a standard CMOS process providing a gate electrode 11, a first CMOS spacer 9, a second CMOS spacer 10, a gate insulation region 13, a first source region 6, a second source region 8, a first drain region 5 and a second drain region 7.
  • the NMOS device is formed on an SOI substrate, which comprises a p-type silicon region 3 and a silicon dioxide substrate region 1.
  • the gate insulation region 13 may comprise silicon dioxide.
  • the CMOS spacers 9 and 10 comprise an insulating material, with the property that it is not significantly affected when the gate insulation region 13 is etched.
  • the CMOS spacers 9 and 10 may for example comprise silicon nitride and the gate insulation region 13 silicon dioxide.
  • the gate electrode 11 comprises a conducting material, such as polysilicon.
  • the first source region 6 and the first drain region 7 comprise an n-type dopant, such as arsenic.
  • the second source region 8 and the second drain region 7 are lightly doped regions and comprise relatively low-doped n-type regions.
  • the next step is a first n-type angled implant, indicated by the arrow A in Fig. 3, to form a first emitter sub region 17 below the first source region 6.
  • a second n- type angled implant indicated by the arrow B in Fig. 3, forms a second emitter sub region 19, which has a higher doping level than the first emitter sub region 17 and overdopes the first source region 6.
  • the angle of the first and second angled implant is such that the second CMOS spacer 10 provides a shield for a relatively large portion of the first drain region 5.
  • a relatively low-doped n-type collector sub region 15 is formed by a third angled implant, indicated by the arrow C in Fig. 3.
  • the angle of the third angled implant is such that the second CMOS spacer 10 does not provide a shield for a portion of the p-type silicon region 3, which is covered by the second CMOS spacer 10 and by a portion of the gate electrode 11.
  • a silicon dioxide layer 21 is deposited and planarized using for example chemical mechanical polishing (CMP), thereby exposing the gate electrode 11, as is illustrated in Fig. 4.
  • CMP chemical mechanical polishing
  • a standard photolithographic patterning technique is applied which forms openings above the to be fabricated bipolar transistors, exposes the gate electrode 11, and protects the CMOS devices.
  • the gate electrode 11 is removed using standard etching techniques, followed by etching of a portion of the gate insulation region 13, which is in between the first CMOS spacer 9 and the second CMOS spacer 10.
  • etching a portion of the gate insulation region 13 has a minor effect on the CMOS spacers 9 and 10, because of the different properties of the insulating material of the CMOS spacers 9 and 10 and the insulating material of the gate insulation region 13.
  • a space region 22 is formed between the first CMOS spacer 9 and the second CMOS spacer 10, which exposes the p-type silicon region 3, and portions of the first emitter sub region 17, the second source region 8, the first collector sub region 15 and the second drain region 7.
  • a relatively thin layer of the silicon material, which is exposed by the space region 22, is etched using for example a HCl-based etchant.
  • the etching of the silicon material may be prolonged to consume a larger portion of the relatively lightly doped second source region 8 and second drain region 7, which reduces the negative influence of these lightly doped regions on the performance of the lateral bipolar transistor.
  • SiGe is epitaxially grown on the now exposed silicon material in the space region 22, thereby forming a SiGe region 23. There is a remaining portion of the p-type silicon region 3, which is not affected by the epitaxial growth.
  • inside spacers 25, comprising an insulating material such as silicon nitride, are formed in the space region 22.
  • the inside spacers 25 have an L-shape, but any other shape may be applied.
  • a p-type base implant is performed thereby forming a base region 27, which overdopes the remaining portion of the p-type silicon region 3.
  • the inside spacers 25 mask the p-type base implant and define the exposed area of the base region 27.
  • the silicon etching and SiGe forming steps may be omitted, in which case the base region comprises p-doped silicon material only.
  • the patterned resist layer and the silicon dioxide layer 21 are removed.
  • the exposed silicon material is suicided, thereby forming a metal layer 29, as is shown in Fig. 7, which reduces the base, collector and emitter resistances further.
  • the invention may also be applied to PMOS devices.
  • the fabrication method may also be applied on bulk silicon substrates, or SSOI substrates.
  • the invention provides a CMOS-based lateral bipolar transistor and a method of fabricating the same.
  • a CMOS device forms the basis of the CMOS-based lateral bipolar transistor.
  • the CMOS device is provided on a silicon, SOI or SSOI substrate and comprises a source and drain region, CMOS spacers and a removed gate electrode.
  • An emitter region and a collector region are disposed in the source and drain regions, and a base region, comprising SiGe or p-type silicon, is provided adjacent to the emitter region and the collector region.
  • the base region has a relatively large exposed area, because it is not covered by the, formerly removed, gate electrode.
  • the base resistance may be reduced by providing a metal layer and an electrical contact on the exposed area of the base region.

Abstract

The invention provides a CMOS-based lateral bipolar transistor and a method of fabricating the same. A CMOS device forms the basis of the CMOS-based lateral bipolar transistor. The CMOS device is provided on a silicon, SOI or SSOI substrate and comprises a source and drain region, CMOS spacers (9, 10) and a removed gate electrode. An emitter region (41) and a collector region (45) are disposed in the source and drain regions, and a base region (43), comprising SiGe or p-type silicon, is provided adjacent to the emitter region (41) and the collector region (45). The base region (43) has a relatively large exposed area, because it is not covered by the, formerly removed, gate electrode. The base resistance may be reduced by providing a metal layer (29) and an electrical contact (33) on the exposed area of the base region (43).

Description

Lateral bipolar transistor
This invention relates to a lateral bipolar transistor.
US-6,489,665 discloses a lateral bipolar transistor comprising an emitter region, a collector region, which surrounds, but is laterally displaced from, the emitter region and a base region. Further a gate region of a CMOS device is provided comprising a polysilicon layer covering a gate oxide layer and overlying at least a portion of the base region. The gate region is in electrical communication with the base region via the gate oxide layer. By etching an opening in the gate region, a base-gate contact is formed thereby reducing the base resistance. However, the base-gate contact only connects the base region on a limited number of locations, which increases the base resistance.
It is an object of the invention to provide a CMOS-based lateral bipolar transistor with a reduced base resistance. According to the invention, this object is achieved by providing a lateral bipolar transistor as claimed in claim 1.
The invention provides a CMOS-based lateral bipolar transistor with an emitter region, a collector region and a base region. A first CMOS spacer is provided which is displaced from a second CMOS spacer by a space region, which formerly comprised a gate electrode. The first CMOS spacer covers a portion of the emitter region, the second CMOS spacer covers a portion of the collector region and the space region overlies the base region. The base region comprises a relatively large exposed area, on which an electrical contact is provided, which reduces the base resistance.
Covering the base region with a metal layer may reduce the base resistance further.
The CMOS-based lateral bipolar transistor is fabricated from a CMOS device on a substrate. The CMOS device comprises a gate electrode in between a first and a second CMOS spacer, a gate oxide region, a bulk region and a first and a second source-drain region. An emitter region is formed in the first source-drain region and in a first portion of the bulk region, which is adjacent to the first source-drain region. A collector region is formed in the second source-drain region and in a second portion of the bulk region, which is adjacent to the second source-drain region. The gate electrode and a portion of the gate oxide region, which is between the first and the second CMOS spacer, are removed, thereby forming a space region between the first and the second CMOS spacer. A base region is formed adjacent to the emitter region and adjacent to the collector region in a third portion of the bulk region. The base region is underlying the space region, and not by the gate electrode or by a portion of the gate oxide region, because these regions are removed. Therefore the base region comprises a relatively large exposed area, and by forming an electrical contact on the exposed area of the base region, the base resistance is reduced further.
These and other aspects of the invention will be further elucidated and described with reference to the drawings, in which: Fig. 1 is a cross-sectional view of an embodiment of the CMOS-based lateral bipolar transistor according to the invention, and
Figs. 2 - 7 are cross-sectional views of various stages of the fabrication of the CMOS-based lateral bipolar transistor according to an embodiment of the invention.
The Figures are not drawn to scale. In general, identical components are denoted by the same reference numerals in the Figures.
Fig. 1 illustrates a schematic cross-section of an embodiment of a CMOS- based lateral bipolar transistor. The lateral bipolar transistor comprises an n-type emitter region 41, a p-type base region 43 and an n-type collector region 45, which regions are provided on a substrate region 1. The base region 43 is positioned adjacent to the emitter region 41 and adjacent to the collector region 45, in a region, which is laterally defined by a first CMOS spacer 9 and a second CMOS spacer 10. Between the first CMOS spacer 9 and the second CMOS spacer 10, the gate electrode material of the former CMOS device has been removed, which advantageously exposes a relatively large portion of the base region 43, thereby enabling a reduction of the base resistance. A metal layer 29 is applied and an emitter contact 31, a base contact 33 and a collector contact 35 are formed, thereby further reducing the resistance of the base, collector and emitter regions. The base region 43 may also comprise SiGe, thereby creating a heterojunction bipolar transistor. In an embodiment a bulk silicon substrate may be applied, hence in this embodiment the substrate region 1 comprises a semiconductor material, such as silicon. In another embodiment a silicon-on- insulator (SOI) or a strained-silicon-on-insulator (SSOI) substrate may be applied, wherein the substrate region 1 comprises an insulating material, such as silicon dioxide. In the case that an SOI or SSOI substrate is provided, the emitter region 41, the base region 43 and the collector region 45 are formed in the silicon, respectively strained- silicon layer that is provided on the insulating substrate region 1 of the SOI, respectively SSOI substrate. In this way the SOI and SSOI substrates provide an advantageous electrical isolation of the lateral bipolar transistor from other devices on the substrate. If a strained-silicon layer is applied in combination with SiGe in the base region 43 and the metal layer 29, a CMOS-based strained-silicon HEMT (High Electron Mobility Transistor) device may be formed. The HEMT device may be advantageously applied in applications, which require a high gain at high frequencies.
Figs. 2 - 7 illustrate cross-sectional views of various stages of the fabrication of an embodiment of the invention. Fig. 2 shows an NMOS device fabricated in a standard CMOS process providing a gate electrode 11, a first CMOS spacer 9, a second CMOS spacer 10, a gate insulation region 13, a first source region 6, a second source region 8, a first drain region 5 and a second drain region 7. The NMOS device is formed on an SOI substrate, which comprises a p-type silicon region 3 and a silicon dioxide substrate region 1. The gate insulation region 13 may comprise silicon dioxide. The CMOS spacers 9 and 10 comprise an insulating material, with the property that it is not significantly affected when the gate insulation region 13 is etched. The CMOS spacers 9 and 10 may for example comprise silicon nitride and the gate insulation region 13 silicon dioxide. The gate electrode 11 comprises a conducting material, such as polysilicon. The first source region 6 and the first drain region 7 comprise an n-type dopant, such as arsenic. The second source region 8 and the second drain region 7 are lightly doped regions and comprise relatively low-doped n-type regions.
The next step is a first n-type angled implant, indicated by the arrow A in Fig. 3, to form a first emitter sub region 17 below the first source region 6. Then a second n- type angled implant, indicated by the arrow B in Fig. 3, forms a second emitter sub region 19, which has a higher doping level than the first emitter sub region 17 and overdopes the first source region 6. The angle of the first and second angled implant is such that the second CMOS spacer 10 provides a shield for a relatively large portion of the first drain region 5. A relatively low-doped n-type collector sub region 15 is formed by a third angled implant, indicated by the arrow C in Fig. 3. The angle of the third angled implant is such that the second CMOS spacer 10 does not provide a shield for a portion of the p-type silicon region 3, which is covered by the second CMOS spacer 10 and by a portion of the gate electrode 11.
Thereafter, a silicon dioxide layer 21 is deposited and planarized using for example chemical mechanical polishing (CMP), thereby exposing the gate electrode 11, as is illustrated in Fig. 4. A standard photolithographic patterning technique is applied which forms openings above the to be fabricated bipolar transistors, exposes the gate electrode 11, and protects the CMOS devices. The gate electrode 11 is removed using standard etching techniques, followed by etching of a portion of the gate insulation region 13, which is in between the first CMOS spacer 9 and the second CMOS spacer 10. The etching a portion of the gate insulation region 13 has a minor effect on the CMOS spacers 9 and 10, because of the different properties of the insulating material of the CMOS spacers 9 and 10 and the insulating material of the gate insulation region 13. In this way a space region 22 is formed between the first CMOS spacer 9 and the second CMOS spacer 10, which exposes the p-type silicon region 3, and portions of the first emitter sub region 17, the second source region 8, the first collector sub region 15 and the second drain region 7.
Subsequently, as is shown in Fig. 5, a relatively thin layer of the silicon material, which is exposed by the space region 22, is etched using for example a HCl-based etchant. The etching of the silicon material may be prolonged to consume a larger portion of the relatively lightly doped second source region 8 and second drain region 7, which reduces the negative influence of these lightly doped regions on the performance of the lateral bipolar transistor. SiGe is epitaxially grown on the now exposed silicon material in the space region 22, thereby forming a SiGe region 23. There is a remaining portion of the p-type silicon region 3, which is not affected by the epitaxial growth. Next, inside spacers 25, comprising an insulating material such as silicon nitride, are formed in the space region 22. The inside spacers 25 have an L-shape, but any other shape may be applied.
Thereafter, as is illustrated in Fig. 6, a p-type base implant is performed thereby forming a base region 27, which overdopes the remaining portion of the p-type silicon region 3. The inside spacers 25 mask the p-type base implant and define the exposed area of the base region 27. Optionally the silicon etching and SiGe forming steps may be omitted, in which case the base region comprises p-doped silicon material only.
Next, the patterned resist layer and the silicon dioxide layer 21 are removed. The exposed silicon material is suicided, thereby forming a metal layer 29, as is shown in Fig. 7, which reduces the base, collector and emitter resistances further. It is obvious for a person skilled in the art to interchange source and drain regions, and collector and emitter regions. Further, it is also obvious that the invention may also be applied to PMOS devices. In addition, the fabrication method may also be applied on bulk silicon substrates, or SSOI substrates. In summary, the invention provides a CMOS-based lateral bipolar transistor and a method of fabricating the same. A CMOS device forms the basis of the CMOS-based lateral bipolar transistor. The CMOS device is provided on a silicon, SOI or SSOI substrate and comprises a source and drain region, CMOS spacers and a removed gate electrode. An emitter region and a collector region are disposed in the source and drain regions, and a base region, comprising SiGe or p-type silicon, is provided adjacent to the emitter region and the collector region. The base region has a relatively large exposed area, because it is not covered by the, formerly removed, gate electrode. The base resistance may be reduced by providing a metal layer and an electrical contact on the exposed area of the base region.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of other elements or steps than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

Claims

CLAIMS:
1. A lateral bipolar transistor, comprising: an emitter region (17), a collector region (15), a first CMOS spacer (9) covering a portion of the emitter region (17), - a second CMOS spacer (10) displaced from the first CMOS spacer (9) by a space region (22) and covering a portion of the collector region (15), and a base region (27) underlying the space region (22) and adjacent to the emitter region (17) and the collector region (15).
2. The lateral bipolar transistor of claim 1, wherein the base region (27) is covered with a metal layer (29).
3. The lateral bipolar transistor of claim 1, wherein the base region (27) comprises a SiGe region (23).
4. A method for fabricating a lateral bipolar transistor, the method comprising: providing a CMOS device on a substrate region (1), the CMOS device comprising a gate electrode (11) in between a first CMOS spacer (9) and a second CMOS spacer (10), a gate oxide region (13), a bulk region (3) in between a first source-drain region (6) and a second source-drain region (5), a first step of forming an emitter region (17) in the first source-drain region (6) and in a first portion of the bulk region (3), a second step of forming a collector region (15) in the second source-drain region (5) and in a second portion of the bulk region (3), and - a third step of removing the gate electrode (11) and a portion of the gate oxide region (13) between the first CMOS spacer (9) and the second CMOS spacer (10), thereby forming a space region (22), a fourth step of forming a base region (27) underlying the space region (22) in a third portion of the bulk region (3) and adjacent to the emitter region (17) and adjacent to the collector region (15).
5. The method as claimed in claim 4, further comprising: after the third step, a step of forming a SiGe region (23) in a portion of the bulk region (3) between the first CMOS spacer (9) and the second CMOS spacer (10).
6. The method as claimed in claim 4, further comprising: before the fourth step, a step of forming inside spacers (25) covering the surfaces of the first CMOS spacer (9) and the second CMOS spacer (10) that face the space region (22).
7. The method as claimed in claim 4, in which the collector region (15) is formed with an angled implant and the emitter region (17) is formed with an angled implant.
8. The method as claimed in claim 4, in which the substrate region (1) comprises an insulating material.
PCT/IB2006/051045 2005-04-13 2006-04-05 Lateral bipolar transistor WO2006109221A2 (en)

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EP05102908 2005-04-13

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9059230B1 (en) 2014-01-10 2015-06-16 International Business Machines Corporation Lateral silicon-on-insulator bipolar junction transistor process and structure
US9105650B2 (en) 2012-09-12 2015-08-11 International Business Machines Corporation Lateral bipolar transistor and CMOS hybrid technology

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0252206A2 (en) * 1986-07-09 1988-01-13 Hitachi, Ltd. Method of fabricating semiconductor structure
US5952706A (en) * 1997-10-29 1999-09-14 National Semiconductor Corporation Semiconductor integrated circuit having a lateral bipolar transistor compatible with deep sub-micron CMOS processing
US20020192917A1 (en) * 2001-06-15 2002-12-19 Ian Wylie Method of converting a metal oxide semiconductor transistor into a bipolar transistor
US20040129982A1 (en) * 2000-05-25 2004-07-08 Renesas Technology Corporation Semiconductor device and manufacturing method
US6861325B1 (en) * 2002-09-24 2005-03-01 Advanced Micro Devices, Inc. Methods for fabricating CMOS-compatible lateral bipolar junction transistors

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0252206A2 (en) * 1986-07-09 1988-01-13 Hitachi, Ltd. Method of fabricating semiconductor structure
US5952706A (en) * 1997-10-29 1999-09-14 National Semiconductor Corporation Semiconductor integrated circuit having a lateral bipolar transistor compatible with deep sub-micron CMOS processing
US20040129982A1 (en) * 2000-05-25 2004-07-08 Renesas Technology Corporation Semiconductor device and manufacturing method
US20020192917A1 (en) * 2001-06-15 2002-12-19 Ian Wylie Method of converting a metal oxide semiconductor transistor into a bipolar transistor
US6861325B1 (en) * 2002-09-24 2005-03-01 Advanced Micro Devices, Inc. Methods for fabricating CMOS-compatible lateral bipolar junction transistors

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
GOMEZ R ET AL: "Lateral bipolar transistor fabricated on a deep-submicron technology" UNIVERSITY/GOVERNMENT/INDUSTRY MICROELECTRONICS SYMPOSIUM, 1999. PROCEEDINGS OF THE THIRTEENTH BIENNIAL MINNEAPOLIS, MN, USA 20-23 JUNE 1999, PISCATATWAY, NJ, USA,IEEE, US, 20 June 1999 (1999-06-20), pages 37-42, XP010345883 ISBN: 0-7803-5240-8 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9105650B2 (en) 2012-09-12 2015-08-11 International Business Machines Corporation Lateral bipolar transistor and CMOS hybrid technology
US9059230B1 (en) 2014-01-10 2015-06-16 International Business Machines Corporation Lateral silicon-on-insulator bipolar junction transistor process and structure
US9397203B2 (en) 2014-01-10 2016-07-19 Globalfoundries Inc. Lateral silicon-on-insulator bipolar junction transistor process and structure

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