JP3996267B2 - 半導体記憶装置 - Google Patents

半導体記憶装置 Download PDF

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Publication number
JP3996267B2
JP3996267B2 JP12879798A JP12879798A JP3996267B2 JP 3996267 B2 JP3996267 B2 JP 3996267B2 JP 12879798 A JP12879798 A JP 12879798A JP 12879798 A JP12879798 A JP 12879798A JP 3996267 B2 JP3996267 B2 JP 3996267B2
Authority
JP
Japan
Prior art keywords
bonding pads
disposed
transistor
bonding
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP12879798A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11330410A5 (cg-RX-API-DMAC10.html
JPH11330410A (ja
Inventor
宏一郎 野田
茂信 加藤
五郎 橘川
通宏 三島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
Elpida Memory Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elpida Memory Inc filed Critical Elpida Memory Inc
Priority to JP12879798A priority Critical patent/JP3996267B2/ja
Priority to TW088106238A priority patent/TW429603B/zh
Priority to KR1019990015869A priority patent/KR100830009B1/ko
Priority to US09/310,580 priority patent/US20020096694A1/en
Publication of JPH11330410A publication Critical patent/JPH11330410A/ja
Priority to US09/966,085 priority patent/US20020008255A1/en
Priority to US09/966,084 priority patent/US20020008254A1/en
Priority to US10/330,054 priority patent/US20030089926A1/en
Priority to US11/196,267 priority patent/US7400034B2/en
Publication of JPH11330410A5 publication Critical patent/JPH11330410A5/ja
Application granted granted Critical
Publication of JP3996267B2 publication Critical patent/JP3996267B2/ja
Priority to US12/146,654 priority patent/US7638871B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H10W72/5473—Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
JP12879798A 1998-05-12 1998-05-12 半導体記憶装置 Expired - Lifetime JP3996267B2 (ja)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP12879798A JP3996267B2 (ja) 1998-05-12 1998-05-12 半導体記憶装置
TW088106238A TW429603B (en) 1998-05-12 1999-04-19 Semiconductor apparatus
KR1019990015869A KR100830009B1 (ko) 1998-05-12 1999-05-03 반도체 장치
US09/310,580 US20020096694A1 (en) 1998-05-12 1999-05-12 Semiconductor device
US09/966,085 US20020008255A1 (en) 1998-05-12 2001-10-01 Semiconductor device
US09/966,084 US20020008254A1 (en) 1998-05-12 2001-10-01 Semiconductor device
US10/330,054 US20030089926A1 (en) 1998-05-12 2002-12-30 Semiconductor device
US11/196,267 US7400034B2 (en) 1998-05-12 2005-08-04 Semiconductor device
US12/146,654 US7638871B2 (en) 1998-05-12 2008-06-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12879798A JP3996267B2 (ja) 1998-05-12 1998-05-12 半導体記憶装置

Publications (3)

Publication Number Publication Date
JPH11330410A JPH11330410A (ja) 1999-11-30
JPH11330410A5 JPH11330410A5 (cg-RX-API-DMAC10.html) 2005-12-22
JP3996267B2 true JP3996267B2 (ja) 2007-10-24

Family

ID=14993685

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12879798A Expired - Lifetime JP3996267B2 (ja) 1998-05-12 1998-05-12 半導体記憶装置

Country Status (4)

Country Link
US (6) US20020096694A1 (cg-RX-API-DMAC10.html)
JP (1) JP3996267B2 (cg-RX-API-DMAC10.html)
KR (1) KR100830009B1 (cg-RX-API-DMAC10.html)
TW (1) TW429603B (cg-RX-API-DMAC10.html)

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JP2013021528A (ja) * 2011-07-12 2013-01-31 Elpida Memory Inc 半導体装置、及び出力バッファのインピーダンスを調整する方法
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KR102571550B1 (ko) * 2018-02-14 2023-08-28 삼성전자주식회사 메모리 장치, 메모리 시스템 및 전자 장치
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JP2021047960A (ja) * 2019-09-19 2021-03-25 キオクシア株式会社 半導体記憶装置
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Also Published As

Publication number Publication date
US20080265284A1 (en) 2008-10-30
US7638871B2 (en) 2009-12-29
US20030089926A1 (en) 2003-05-15
US20020008254A1 (en) 2002-01-24
US20020008255A1 (en) 2002-01-24
KR100830009B1 (ko) 2008-05-15
US20050263811A1 (en) 2005-12-01
US7400034B2 (en) 2008-07-15
US20020096694A1 (en) 2002-07-25
JPH11330410A (ja) 1999-11-30
KR19990088026A (ko) 1999-12-27
TW429603B (en) 2001-04-11

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