KR100830009B1 - 반도체 장치 - Google Patents
반도체 장치 Download PDFInfo
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- KR100830009B1 KR100830009B1 KR1019990015869A KR19990015869A KR100830009B1 KR 100830009 B1 KR100830009 B1 KR 100830009B1 KR 1019990015869 A KR1019990015869 A KR 1019990015869A KR 19990015869 A KR19990015869 A KR 19990015869A KR 100830009 B1 KR100830009 B1 KR 100830009B1
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- 239000004065 semiconductor Substances 0.000 title claims description 48
- 230000002093 peripheral effect Effects 0.000 claims description 38
- 238000000034 method Methods 0.000 claims description 16
- 239000002184 metal Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 4
- 208000035795 Hypocalcemic vitamin D-dependent rickets Diseases 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 208000033584 type 1 vitamin D-dependent rickets Diseases 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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Abstract
Description
Claims (38)
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- 어드레스신호 및 클록 신호용의 복수의 본딩 패드S와, 데이터 신호용의 복수의 본딩 패드D와, 제1, 제2, 제3 및 제4의 메모리 뱅크를 각각 구성하는 제1, 제2, 제3 및 제4의 메모리 어레이 영역을 동일 반도체칩 상에 구비하는 반도체 기억장치로서,상기 반도체칩의 장변 방향이 좌우방향, 단변 방향이 상하방향으로 되도록 평면시(平面視) 했을 경우에, 상기 반도체칩의 중심점에 대하여 왼쪽위(左上)로 상기 제1의 메모리 어레이 영역이 배치되고,왼쪽아래(左下)로 상기 제2의 메모리 어레이 영역이 배치되며,오른쪽아래(右下)로 상기 제3의 메모리 어레이 영역이 배치되고,오른쪽위(右上)로 상기 제4의 메모리 어레이 영역이 배치되며,상기 복수의 본딩 패드S는, 상기 제1의 메모리 어레이 영역과 상기 제2의 메모리 어레이 영역의 사이에 배치되고,상기 복수의 본딩 패드D는, 상기 제3의 메모리 어레이 영역과 상기 제4의 메모리 어레이 영역의 사이에 배치되고,상기 반도체칩의 단변 방향에 대한 중심축으로부터 상기 본딩 패드S까지의 거리가, 상기 중심축으로부터 본딩 패드D까지의 거리보다도 큰 반도체 기억장치.
- 제 30 항에 있어서,내부회로와,상기 본딩 패드D를 사이에 두고 상기 제3의 메모리 어레이 영역과 상기 제4의 메모리 어레이 영역과의 사이에 나열되도록 배치된 PMOS 트랜지스터와 NMOS 트랜지스터를 구비하고,상기 PMOS 트랜지스터의 소스는 제1 전원선에 접속되며, 드레인은 상기 본딩 패드D와 접속되고, 게이트는 상기 내부회로의 출력을 받으며,상기 NMOS 트랜지스터의 소스는 제2 전원선에 접속되고, 드레인은 상기 본딩 패드D와 접속되며, 게이트는 상기 내부회로의 출력을 받는 반도체 기억장치.
- 제 31 항에 있어서,상기 내부회로는, 상기 제1과 제2의 메모리 어레이 영역의 사이 및, 상기 제3과 제4의 메모리 어레이 영역의 사이에 배치되며,상기 제1 전원선과 제2 전원선은 상기 제1 내지 제4의 메모리 어레이 영역에 이용되는 전원선과는 다른 전원선인 반도체 기억장치.
- 제 30 항 또는 제 31 항에 있어서,LOC 패키지에 본딩되는 반도체 기억장치.
- 제 30 항에 있어서,상기 복수의 본딩 패드S 중 적어도 하나의 본딩 패드S와 접속된 정전보호소자를 구비하고,상기 제1의 메모리 어레이 영역과 상기 제2의 메모리 어레이 영역과의 사이에 있어서, 상기 본딩 패드S와 상기 정전보호소자가 상기 반도체칩의 단변 방향과 평행하게 나열되어 배치되는 반도체 기억장치.
- 제 34 항에 있어서,간접주변회로와, 컬럼 디코더와, 메인 로 디코더와, 메인 워드 드라이버와, 메인 앰프를 구비하고,상기 복수의 본딩 패드S와 상기 제1의 메모리 어레이 영역의 간격과, 상기 복수의 본딩 패드S와 상기 제2의 메모리 어레이 영역의 간격을 비교하여, 간격이 큰 쪽으로 상기 간접주변회로가 배치되고,상기 컬럼 디코더와 메인 앰프는, 각각 대응하는 메모리 어레이 영역과, 상기 복수의 본딩 패드S 또는 상기 복수의 본딩 패드D와의 사이에 배치되며,상기 메인 워드 드라이버와 메인 로 디코더는, 상기 제1과 제4의 메모리 어레이 영역의 사이와, 상기 제2와 제3의 메모리 어레이 영역의 사이에 배치되는 반도체 기억장치.
- 제 35 항에 있어서,PMOS 트랜지스터와 NMOS 트랜지스터를 구비하는 데이터 출력회로를 구비하고,상기 PMOS 트랜지스터와 NMOS 트랜지스터는 상기 본딩 패드D를 사이에 두고 상기 제3의 메모리 어레이 영역과 상기 제4의 메모리 어레이 영역과의 사이에 나열되도록 배치되는 반도체 기억장치.
- 제 36 항에 있어서,상기 PMOS 트랜지스터의 소스는 제1 전원선에 접속되고, 드레인은 상기 본딩 패드D와 접속되며,상기 NMOS 트랜지스터의 소스는 제2 전원선에 접속되고, 드레인은 상기 본딩 패드D와 접속되며,상기 제1 전원선과 제2 전원선은 상기 데이터 출력회로의 전용 전원선인 반도체 기억장치.
- 제 37 항에 있어서,LOC 패키지에 본딩되는 반도체 기억장치.
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JP12879798A JP3996267B2 (ja) | 1998-05-12 | 1998-05-12 | 半導体記憶装置 |
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US (6) | US20020096694A1 (ko) |
JP (1) | JP3996267B2 (ko) |
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Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19960558B4 (de) * | 1999-12-15 | 2008-07-24 | Qimonda Ag | Halbleiterspeicher vom wahlfreien Zugriffstyp (DRAM) |
KR100382739B1 (ko) * | 2001-04-13 | 2003-05-09 | 삼성전자주식회사 | 비대칭 데이터 경로를 갖는 반도체 메모리 장치 |
KR100572322B1 (ko) * | 2003-11-27 | 2006-04-19 | 삼성전자주식회사 | 반도체메모리장치의 비트라인 감지증폭블록의 레이아웃구조 |
DE102004012553A1 (de) * | 2004-03-15 | 2005-10-13 | Infineon Technologies Ag | Speicherbauelement mit asymmetrischer Kontaktreihe |
US8298179B2 (en) | 2004-12-22 | 2012-10-30 | Boston Scientific Scimed, Inc. | Catheter assembly with tapered joints and method of manufacture |
DE102005049248B4 (de) * | 2005-10-14 | 2008-06-26 | Qimonda Ag | Gehäuster DRAM-Chip für Hochgeschwindigkeitsanwendungen |
JP2010074018A (ja) * | 2008-09-22 | 2010-04-02 | Nec Electronics Corp | 半導体装置 |
JP5710955B2 (ja) * | 2010-12-10 | 2015-04-30 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置 |
KR101198141B1 (ko) * | 2010-12-21 | 2012-11-12 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 |
JP2013021528A (ja) * | 2011-07-12 | 2013-01-31 | Elpida Memory Inc | 半導体装置、及び出力バッファのインピーダンスを調整する方法 |
JP6165356B2 (ja) | 2015-06-26 | 2017-07-19 | オリンパス株式会社 | 内視鏡システム |
KR102571550B1 (ko) * | 2018-02-14 | 2023-08-28 | 삼성전자주식회사 | 메모리 장치, 메모리 시스템 및 전자 장치 |
US11631465B2 (en) | 2018-07-03 | 2023-04-18 | Samsung Electronics Co., Ltd. | Non-volatile memory device |
US11164638B2 (en) | 2018-07-03 | 2021-11-02 | Samsung Electronics Co., Ltd. | Non-volatile memory device |
KR102601213B1 (ko) * | 2018-07-03 | 2023-11-10 | 삼성전자주식회사 | 비휘발성 메모리 장치 및 비휘발성 메모리 장치의 제조 방법 |
JP2021047960A (ja) * | 2019-09-19 | 2021-03-25 | キオクシア株式会社 | 半導体記憶装置 |
TWI792683B (zh) * | 2021-11-17 | 2023-02-11 | 旺宏電子股份有限公司 | 積體電路 |
US11903194B2 (en) | 2021-11-17 | 2024-02-13 | Macronix International Co., Ltd. | Integrated circuit |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03116865A (ja) * | 1989-09-29 | 1991-05-17 | Hitachi Ltd | 半導体記憶装置 |
KR960019737A (ko) * | 1994-11-10 | 1996-06-17 | 사토 후미오 | 반도체 기억장치 |
JPH09148540A (ja) * | 1995-11-28 | 1997-06-06 | Mitsubishi Electric Corp | 半導体装置 |
KR970051163A (ko) * | 1995-12-21 | 1997-07-29 | 김광호 | 반도체 메모리장치 |
JPH1117131A (ja) * | 1997-06-23 | 1999-01-22 | Nec Ic Microcomput Syst Ltd | 半導体メモリ装置 |
Family Cites Families (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5262999A (en) * | 1988-06-17 | 1993-11-16 | Hitachi, Ltd. | Large scale integrated circuit for low voltage operation |
KR0141495B1 (ko) * | 1988-11-01 | 1998-07-15 | 미다 가쓰시게 | 반도체 기억장치 및 그 결함구제방법 |
US5579256A (en) * | 1988-11-01 | 1996-11-26 | Hitachi, Ltd. | Semiconductor memory device and defect remedying method thereof |
US5579258A (en) * | 1991-11-28 | 1996-11-26 | Olympus Optical Co., Ltd. | Ferroelectric memory |
US5567655A (en) * | 1993-05-05 | 1996-10-22 | Lsi Logic Corporation | Method for forming interior bond pads having zig-zag linear arrangement |
JP3299342B2 (ja) * | 1993-06-11 | 2002-07-08 | 株式会社日立製作所 | 半導体メモリモジュール |
JPH0785655A (ja) * | 1993-09-16 | 1995-03-31 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP2647023B2 (ja) * | 1994-10-27 | 1997-08-27 | 日本電気株式会社 | 半導体記憶装置 |
US5661686A (en) * | 1994-11-11 | 1997-08-26 | Nkk Corporation | Nonvolatile semiconductor memory |
KR100197570B1 (ko) * | 1995-08-31 | 1999-06-15 | 윤종용 | 고성능 동기 반도체 메모리 장치의 클럭 패드 배치 구조 |
JP3406127B2 (ja) * | 1995-09-04 | 2003-05-12 | 三菱電機株式会社 | 半導体装置 |
JPH09139184A (ja) * | 1995-11-15 | 1997-05-27 | Nikon Corp | 静電偏向器の製造方法 |
JP3927620B2 (ja) * | 1996-06-12 | 2007-06-13 | キヤノン株式会社 | 電子ビーム露光方法及びそれを用いたデバイス製造方法 |
JP3796317B2 (ja) * | 1996-06-12 | 2006-07-12 | キヤノン株式会社 | 電子ビーム露光方法及びそれを用いたデバイス製造方法 |
US5929454A (en) * | 1996-06-12 | 1999-07-27 | Canon Kabushiki Kaisha | Position detection apparatus, electron beam exposure apparatus, and methods associated with them |
JP3728015B2 (ja) * | 1996-06-12 | 2005-12-21 | キヤノン株式会社 | 電子ビーム露光システム及びそれを用いたデバイス製造方法 |
US5981954A (en) * | 1997-01-16 | 1999-11-09 | Canon Kabushiki Kaisha | Electron beam exposure apparatus |
JP3689516B2 (ja) * | 1997-01-29 | 2005-08-31 | キヤノン株式会社 | 電子ビーム露光装置 |
JPH10214779A (ja) * | 1997-01-31 | 1998-08-11 | Canon Inc | 電子ビーム露光方法及び該方法を用いたデバイス製造方法 |
US6107636A (en) * | 1997-02-07 | 2000-08-22 | Canon Kabushiki Kaisha | Electron beam exposure apparatus and its control method |
US6104035A (en) * | 1997-06-02 | 2000-08-15 | Canon Kabushiki Kaisha | Electron-beam exposure apparatus and method |
JP3787417B2 (ja) * | 1997-06-11 | 2006-06-21 | キヤノン株式会社 | 電子ビーム露光方法及び電子ビーム露光装置 |
US6552353B1 (en) * | 1998-01-05 | 2003-04-22 | Canon Kabushiki Kaisha | Multi-electron beam exposure method and apparatus and device manufacturing method |
US6255155B1 (en) * | 1998-04-23 | 2001-07-03 | Hyundai Electronics Industries Co., Ltd. | Nonvolatile memory and method for fabricating the same |
JP2000049071A (ja) * | 1998-07-28 | 2000-02-18 | Canon Inc | 電子ビーム露光装置及び方法、ならびにデバイス製造方法 |
JP4454706B2 (ja) * | 1998-07-28 | 2010-04-21 | キヤノン株式会社 | 電子ビーム露光方法及び装置、ならびにデバイス製造方法 |
US6559456B1 (en) * | 1998-10-23 | 2003-05-06 | Canon Kabushiki Kaisha | Charged particle beam exposure method and apparatus |
JP4100799B2 (ja) * | 1999-01-25 | 2008-06-11 | キヤノン株式会社 | マスクパターン転写方法、マスクパターン転写装置、デバイス製造方法及び転写マスク |
JP2000232053A (ja) * | 1999-02-09 | 2000-08-22 | Canon Inc | マスクパターン転写方法、該マスクパターン転写方法を用いたマスクパターン転写装置及びデバイス製造方法 |
US6465783B1 (en) * | 1999-06-24 | 2002-10-15 | Nikon Corporation | High-throughput specimen-inspection apparatus and methods utilizing multiple parallel charged particle beams and an array of multiple secondary-electron-detectors |
JP4427847B2 (ja) * | 1999-11-04 | 2010-03-10 | エルピーダメモリ株式会社 | ダイナミック型ramと半導体装置 |
US6566664B2 (en) * | 2000-03-17 | 2003-05-20 | Canon Kabushiki Kaisha | Charged-particle beam exposure apparatus and device manufacturing method |
JP4947841B2 (ja) * | 2000-03-31 | 2012-06-06 | キヤノン株式会社 | 荷電粒子線露光装置 |
JP4647820B2 (ja) * | 2001-04-23 | 2011-03-09 | キヤノン株式会社 | 荷電粒子線描画装置、および、デバイスの製造方法 |
JP2003031172A (ja) * | 2001-07-16 | 2003-01-31 | Nikon Corp | 偏向器とその製造方法、及び荷電粒子露光装置 |
US6873535B1 (en) * | 2004-02-04 | 2005-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple width and/or thickness write line in MRAM |
JP4997872B2 (ja) * | 2006-08-22 | 2012-08-08 | ソニー株式会社 | 不揮発性半導体メモリデバイスおよびその製造方法 |
-
1998
- 1998-05-12 JP JP12879798A patent/JP3996267B2/ja not_active Expired - Lifetime
-
1999
- 1999-04-19 TW TW088106238A patent/TW429603B/zh active
- 1999-05-03 KR KR1019990015869A patent/KR100830009B1/ko not_active IP Right Cessation
- 1999-05-12 US US09/310,580 patent/US20020096694A1/en not_active Abandoned
-
2001
- 2001-10-01 US US09/966,085 patent/US20020008255A1/en not_active Abandoned
- 2001-10-01 US US09/966,084 patent/US20020008254A1/en not_active Abandoned
-
2002
- 2002-12-30 US US10/330,054 patent/US20030089926A1/en not_active Abandoned
-
2005
- 2005-08-04 US US11/196,267 patent/US7400034B2/en not_active Expired - Fee Related
-
2008
- 2008-06-26 US US12/146,654 patent/US7638871B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03116865A (ja) * | 1989-09-29 | 1991-05-17 | Hitachi Ltd | 半導体記憶装置 |
KR960019737A (ko) * | 1994-11-10 | 1996-06-17 | 사토 후미오 | 반도체 기억장치 |
JPH09148540A (ja) * | 1995-11-28 | 1997-06-06 | Mitsubishi Electric Corp | 半導体装置 |
KR970051163A (ko) * | 1995-12-21 | 1997-07-29 | 김광호 | 반도체 메모리장치 |
JPH1117131A (ja) * | 1997-06-23 | 1999-01-22 | Nec Ic Microcomput Syst Ltd | 半導体メモリ装置 |
Also Published As
Publication number | Publication date |
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JP3996267B2 (ja) | 2007-10-24 |
US7400034B2 (en) | 2008-07-15 |
US20020008255A1 (en) | 2002-01-24 |
US20020096694A1 (en) | 2002-07-25 |
US20050263811A1 (en) | 2005-12-01 |
JPH11330410A (ja) | 1999-11-30 |
US20080265284A1 (en) | 2008-10-30 |
KR19990088026A (ko) | 1999-12-27 |
US20020008254A1 (en) | 2002-01-24 |
TW429603B (en) | 2001-04-11 |
US7638871B2 (en) | 2009-12-29 |
US20030089926A1 (en) | 2003-05-15 |
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