JP3519579B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法

Info

Publication number
JP3519579B2
JP3519579B2 JP24399397A JP24399397A JP3519579B2 JP 3519579 B2 JP3519579 B2 JP 3519579B2 JP 24399397 A JP24399397 A JP 24399397A JP 24399397 A JP24399397 A JP 24399397A JP 3519579 B2 JP3519579 B2 JP 3519579B2
Authority
JP
Japan
Prior art keywords
groove
region
alignment mark
insulating film
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP24399397A
Other languages
English (en)
Japanese (ja)
Other versions
JPH1187488A (ja
JPH1187488A5 (enExample
Inventor
隆 黒井
舞子 酒井
勝之 堀田
弘和 佐山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP24399397A priority Critical patent/JP3519579B2/ja
Priority to TW087100469A priority patent/TW425661B/zh
Priority to US09/028,112 priority patent/US5889335A/en
Priority to KR1019980012551A priority patent/KR100276546B1/ko
Priority to US09/200,469 priority patent/US6218262B1/en
Publication of JPH1187488A publication Critical patent/JPH1187488A/ja
Application granted granted Critical
Publication of JP3519579B2 publication Critical patent/JP3519579B2/ja
Publication of JPH1187488A5 publication Critical patent/JPH1187488A5/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/975—Substrate or mask aligning feature

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Element Separation (AREA)
JP24399397A 1997-09-09 1997-09-09 半導体装置及びその製造方法 Expired - Fee Related JP3519579B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP24399397A JP3519579B2 (ja) 1997-09-09 1997-09-09 半導体装置及びその製造方法
TW087100469A TW425661B (en) 1997-09-09 1998-01-15 Semiconductor device and method of manufacturing the same
US09/028,112 US5889335A (en) 1997-09-09 1998-02-23 Semiconductor device and method of manufacturing the same
KR1019980012551A KR100276546B1 (ko) 1997-09-09 1998-04-09 반도체장치및그제조방법
US09/200,469 US6218262B1 (en) 1997-09-09 1998-11-27 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24399397A JP3519579B2 (ja) 1997-09-09 1997-09-09 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JPH1187488A JPH1187488A (ja) 1999-03-30
JP3519579B2 true JP3519579B2 (ja) 2004-04-19
JPH1187488A5 JPH1187488A5 (enExample) 2004-08-12

Family

ID=17112127

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24399397A Expired - Fee Related JP3519579B2 (ja) 1997-09-09 1997-09-09 半導体装置及びその製造方法

Country Status (4)

Country Link
US (2) US5889335A (enExample)
JP (1) JP3519579B2 (enExample)
KR (1) KR100276546B1 (enExample)
TW (1) TW425661B (enExample)

Families Citing this family (83)

* Cited by examiner, † Cited by third party
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JP3594779B2 (ja) * 1997-06-24 2004-12-02 株式会社ルネサステクノロジ 半導体装置の製造方法
JP3553327B2 (ja) * 1997-07-25 2004-08-11 沖電気工業株式会社 半導体基板のアライメントマーク及びその製造方法
JPH1174229A (ja) * 1997-08-29 1999-03-16 Toshiba Microelectron Corp 半導体装置
US6395619B2 (en) * 1997-12-05 2002-05-28 Sharp Kabushiki Kaisha Process for fabricating a semiconductor device
JP3211767B2 (ja) * 1998-03-27 2001-09-25 日本電気株式会社 半導体装置の製造方法
US6087733A (en) * 1998-06-12 2000-07-11 Intel Corporation Sacrificial erosion control features for chemical-mechanical polishing process
US6043133A (en) * 1998-07-24 2000-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of photo alignment for shallow trench isolation chemical-mechanical polishing
TW381320B (en) * 1998-09-24 2000-02-01 United Microelectronics Corp Method for improving the alignment of semiconductor processes
US6303458B1 (en) * 1998-10-05 2001-10-16 Chartered Semiconductor Manufacturing Ltd. Alignment mark scheme for Sti process to save one mask step
TW436961B (en) * 1998-12-14 2001-05-28 United Microelectronics Corp Method for forming the dielectric layer of an alignment marker area
JP3758876B2 (ja) * 1999-02-02 2006-03-22 Ｎｅｃマイクロシステム株式会社 半導体装置のレイアウト方法
JP2001036036A (ja) * 1999-07-21 2001-02-09 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6191000B1 (en) * 1999-08-23 2001-02-20 Macronix International Co., Ltd. Shallow trench isolation method used in a semiconductor wafer
JP4666700B2 (ja) * 1999-08-30 2011-04-06 富士通セミコンダクター株式会社 半導体装置の製造方法
JP2001110889A (ja) * 1999-10-07 2001-04-20 Nec Corp 半導体装置およびその製造方法
JP3943320B2 (ja) * 1999-10-27 2007-07-11 富士通株式会社 半導体装置及びその製造方法
US6323111B1 (en) 1999-10-28 2001-11-27 Agere Systems Guardian Corp Preweakened on chip metal fuse using dielectric trenches for barrier layer isolation
DE19958906A1 (de) * 1999-12-07 2001-07-05 Infineon Technologies Ag Herstellung von integrierten Schaltungen
US6337122B1 (en) * 2000-01-11 2002-01-08 Micron Technology, Inc. Stereolithographically marked semiconductors devices and methods
JP2001203263A (ja) * 2000-01-20 2001-07-27 Hitachi Ltd 半導体集積回路装置の製造方法および半導体集積回路装置
US20070114631A1 (en) * 2000-01-20 2007-05-24 Hidenori Sato Method of manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device
US6603211B2 (en) * 2000-02-16 2003-08-05 Advanced Micro Devices, Inc. Method and system for providing a robust alignment mark at thin oxide layers
JP3415551B2 (ja) * 2000-03-27 2003-06-09 日本電気株式会社 半導体装置の製造方法
JP2001351837A (ja) * 2000-06-02 2001-12-21 Nec Corp 半導体装置の製造方法
JP2002043412A (ja) * 2000-07-24 2002-02-08 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP4832629B2 (ja) 2000-10-04 2011-12-07 ルネサスエレクトロニクス株式会社 半導体装置
KR20020056347A (ko) * 2000-12-29 2002-07-10 박종섭 반도체 소자의 제조 방법
JP3665275B2 (ja) * 2001-05-28 2005-06-29 沖電気工業株式会社 位置合わせマークの形成方法
JP2002368080A (ja) * 2001-06-05 2002-12-20 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP3875047B2 (ja) * 2001-06-22 2007-01-31 シャープ株式会社 半導体基板の面方位依存性評価方法及びそれを用いた半導体装置
JP4907014B2 (ja) * 2001-06-22 2012-03-28 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
JP4761662B2 (ja) * 2001-07-17 2011-08-31 三洋電機株式会社 回路装置の製造方法
KR100398576B1 (ko) * 2001-08-07 2003-09-19 주식회사 하이닉스반도체 정렬 정확도 향상방법
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US6803291B1 (en) * 2003-03-20 2004-10-12 Taiwan Semiconductor Manufacturing Co., Ltd Method to preserve alignment mark optical integrity
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JP4703364B2 (ja) * 2005-10-24 2011-06-15 株式会社東芝 半導体装置及びその製造方法
KR100745898B1 (ko) * 2006-02-21 2007-08-02 주식회사 하이닉스반도체 반도체 소자의 형성 방법
KR100876806B1 (ko) * 2006-07-20 2009-01-07 주식회사 하이닉스반도체 이중 패터닝 기술을 이용한 반도체 소자의 트랜지스터 형성방법
JP5509543B2 (ja) * 2008-06-02 2014-06-04 富士電機株式会社 半導体装置の製造方法
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US8598630B2 (en) 2008-10-06 2013-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Photo alignment mark for a gate last process
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JP5737922B2 (ja) * 2010-12-14 2015-06-17 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体デバイスの製造方法
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JP6055598B2 (ja) 2012-02-17 2016-12-27 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR101998666B1 (ko) 2013-06-25 2019-10-02 삼성전자주식회사 반도체 장치 및 그 제조 방법
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JP2015070251A (ja) * 2013-10-01 2015-04-13 富士通セミコンダクター株式会社 半導体装置、及び半導体装置の製造方法
KR102066000B1 (ko) 2013-12-11 2020-01-14 삼성전자주식회사 반도체 소자의 제조하는 방법
KR20160015094A (ko) 2014-07-30 2016-02-12 삼성전자주식회사 오버레이 마크, 오버레이 마크를 형성하는 방법 및 오버레이 마크를 이용하여 반도체 소자를 제조하는 방법
CN105914141B (zh) * 2016-06-24 2019-04-30 武汉新芯集成电路制造有限公司 一种形成栅极沟道的方法及对应的半导体结构
JP7163577B2 (ja) * 2017-12-28 2022-11-01 富士電機株式会社 半導体装置の製造方法
US10636744B2 (en) * 2018-08-09 2020-04-28 United Microelectronics Corp. Memory device including alignment mark trench
CN111916425B (zh) * 2019-05-10 2022-12-16 中芯国际集成电路制造(上海)有限公司 半导体形成方法及其结构
US11393769B2 (en) 2020-02-19 2022-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment structure for semiconductor device and method of forming same
DE102020112753A1 (de) 2020-02-19 2021-08-19 Taiwan Semiconductor Manufacturing Co., Ltd. Ausrichtungsstruktur für halbleitervorrichtung und verfahren zu ihrer herstellung
CN113467188B (zh) * 2020-03-30 2022-05-13 长鑫存储技术有限公司 半导体结构及其制备方法
CN113013076B (zh) * 2021-02-25 2022-06-10 长鑫存储技术有限公司 套刻标记的形成方法及半导体结构
US12191258B2 (en) * 2021-12-03 2025-01-07 Nanya Technology Corporation Semiconductor device having integral alignment marks with decoupling features and method for fabricating the same

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Also Published As

Publication number Publication date
TW425661B (en) 2001-03-11
US6218262B1 (en) 2001-04-17
US5889335A (en) 1999-03-30
KR100276546B1 (ko) 2000-12-15
KR19990029155A (ko) 1999-04-26
JPH1187488A (ja) 1999-03-30

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