JP2020518133A - ダイ処理 - Google Patents
ダイ処理 Download PDFInfo
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- JP2020518133A JP2020518133A JP2019557378A JP2019557378A JP2020518133A JP 2020518133 A JP2020518133 A JP 2020518133A JP 2019557378 A JP2019557378 A JP 2019557378A JP 2019557378 A JP2019557378 A JP 2019557378A JP 2020518133 A JP2020518133 A JP 2020518133A
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- die
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- singulated
- cleaned
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
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- H—ELECTRICITY
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
Abstract
Description
本出願は、米国特許法第119条(e)(1)の下で、2018年3月26日に出願された米国特許出願第15/936,075号、並びに2017年4月21日に出願された米国仮出願第62/488,340号及び2017年9月27日に出願された同第62/563,847号の利益を主張するものであり、それらは全体において参照により本明細書に組み込まれる。
以下の説明は、集積回路(integrated circuit、「IC」)の処理に関する。より具体的には、以下の説明は、ICダイを処理するためのデバイス及び技術に関する。
集積回路(IC)ダイを処理するための技術及びシステムの様々な実施形態が開示される。(他のダイ、基板、別の表面などとの)緊密な表面接合のために準備されるダイを、最小限の取り扱いで処理して、ダイの表面又は縁部の汚染を防止することができる。
例示的な実装形態
結論
Claims (51)
- 超小型電子アセンブリを形成する方法であって、
基板の一方又は両方の表面上に保護層を設ける工程と、
前記基板をキャリア上に固定する工程と、
前記基板を前記キャリアに固定された多少のダイに個片化する工程と、
前記ダイが前記キャリアに固定されている間に、前記ダイの少なくとも第1の表面を処理する工程と、
前記キャリアを第1のダイの外周の周りで切断する工程であって、前記切断が、前記第1のダイの第2の表面に固定された前記キャリアの一部分を形成する、工程と、
前記キャリアの前記部分が前記第1のダイの前記第2の表面に固定されている間に、前記第1のダイを前記多少のダイから除去する工程と、
前記第1のダイを基板の準備された表面に取り付ける工程であって、前記第1のダイの前記第1の表面が前記基板の前記準備された表面に取り付けられる、工程と、を含む、方法。 - 前記ダイが前記キャリアに固定されている間に、前記ダイの少なくとも前記第1の表面を洗浄する工程と、
前記ダイが前記キャリアに固定されている間に、前記ダイの前記第1の表面をプラズマ活性化する工程と、
前記ダイが前記キャリアに固定されている間に、前記ダイの少なくとも前記第1の表面を再洗浄する工程と、を更に含む、請求項1に記載の方法。 - 前記第1のダイ及び前記基板を熱処理して、前記第1のダイの前記第1の表面を前記基板の前記準備された表面に接合する工程を更に含む、請求項1に記載の方法。
- 前記第1のダイの前記第2の表面を洗浄する工程と、
前記第1のダイの前記第2の表面をプラズマ活性化する工程と、
前記キャリアを第2のダイの外周の周りで切断する工程であって、前記切断が、前記第2のダイの第2の表面に固定された前記キャリアの別の部分を形成する、工程と、
前記キャリアの前記他の部分が前記第2のダイの前記第2の表面に固定されている間に、前記第2のダイを前記多少のダイから除去する工程と、
前記第2のダイの第1の表面を前記第1のダイの前記第2の表面に取り付けて、積層ダイ配置を形成する工程と、
前記積層ダイ配置を熱処理する工程と、を更に含む、請求項1に記載の方法。 - 前記キャリアから1つ以上の追加のダイを打ち抜き、前記1つ以上の追加のダイを前記第2のダイ及び各後続のダイに取り付けて、前記積層ダイ配置を形成する工程を更に含む、請求項1に記載の方法。
- 前記キャリアを延伸させて、前記キャリアに固定された前記ダイ間に間隙を形成し、前記間隙に沿って前記キャリアを穿孔する工程を更に含む、請求項1に記載の方法。
- 前記キャリアが光学レーザーツールで穿孔されている、請求項6に記載の方法。
- 前記ダイが前記キャリアに固定されている間に、前記ダイの1つ以上の縁部を洗浄する工程を更に含む、請求項6に記載の方法。
- 前記ダイが前記キャリアに固定されている間に、前記ダイの前記第1の表面をプラズマアッシングする工程を更に含む、請求項1に記載の方法。
- 真空ツールを使用して前記第1のダイを除去する工程を更に含み、前記真空ツールが、前記第1のダイの前記第2の表面に固定された前記キャリアの前記部分に取り付けるように、かつ前記第1のダイを、前記第1のダイの表面又は縁部と直接接触させることなく、前記基板の前記準備された表面上に配置するように、設けられている、請求項1に記載の方法。
- 前記キャリアを前記第1のダイの前記外周の周りで切断することによって、前記キャリア内に開口部を形成する工程と、
ピッキングツールを前記キャリアの前記部分に取り付ける工程であって、前記キャリアの前記部分が、前記第1のダイの前記第2の表面に固定される、工程と、
前記第1のダイを前記開口部を通して引っ張ること、又は前記開口部を介して前記第1のダイを前記ピッキングツールで押すことによって、前記第1のダイを前記多少のダイから除去する工程と、を更に含む、請求項1に記載の方法。 - 前記キャリアが、ダイシングシートを含む、請求項1に記載の方法。
- 超小型電子アセンブリを形成する方法であって、
基板の一方又は両方の表面上に保護コーティングを堆積させる工程と、
前記基板をダイシングシート上に固定する工程と、
前記基板を前記ダイシングシートに固定された多少の個片化された要素に個片化する工程と、
前記個片化された要素が前記ダイシングシートに固定されている間に、前記個片化された要素の第1の表面を洗浄する工程と、
前記個片化された要素を紫外線に露光する工程と、
前記ダイシングシートを延伸して、前記ダイシングシートに固定された前記個片化された要素間で間隙を形成するか又は延在させる工程と、
前記個片化された要素が前記ダイシングシートに固定されている間に、前記個片化された要素の前記第1の表面から前記保護コーティングを洗浄する工程と、
前記個片化された要素が前記ダイシングシートに固定されている間に、前記個片化された要素の前記第1の表面をプラズマアッシングする工程と、
前記個片化された要素が前記ダイシングシートに固定されている間に、前記個片化された要素の前記第1の表面を再洗浄する工程と、
前記個片化された要素が前記ダイシングシートに固定されている間に、前記個片化された要素の前記第1の表面をプラズマ活性化する工程と、
前記個片化された要素が前記ダイシングシートに固定されている間に、前記個片化された要素の前記第1の表面を再度洗浄する工程と、
前記間隙に沿って前記ダイシングシートに穿孔を形成する工程と、
真空ツールで前記ダイシングシートの前記穿孔に沿って前記ダイシングシートから第1の個片化された要素を打ち抜き、前記ダイシングシートの一部を前記第1の個片化された要素の第2の表面に固定し、前記真空ツールから前記第1の個片化された要素の前記第2の表面を保護する工程と、
前記第1の個片化された要素を、準備された基板表面上に配置する工程と、
前記第1の個片化された要素を前記準備された基板表面に取り付ける工程であって、前記第1の個片化された要素の前記第1の表面が、前記準備された基板表面に取り付けられている、工程と、
前記第1の個片化された要素及び前記準備された基板表面を熱処理する工程と、
前記第1の個片化された要素の前記第2の表面を洗浄する工程と、
前記第1の個片化された要素の前記第2の表面をプラズマ活性化する工程と、
前記真空ツールで前記ダイシングシートから第2の個片化された要素を打ち抜き、前記ダイシングシートの別の部分を前記第2の個片化された要素の第2の表面に固定し、前記真空ツールから前記第2の個片化された要素の前記第2の表面を保護する工程と、
前記第2の個片化された要素の第1の表面を前記第1の個片化された要素の前記第2の表面に取り付けて、積層超小型電子装置を形成する工程と、
前記積層超小型電子装置を熱処理する工程と、を含む方法。 - 前記基板が、ウエハを含む、請求項13に記載の方法。
- 前記準備された基板表面が、ウエハ表面又はダイ表面又は誘電体表面又はポリマー層又は導電層を含む、請求項13に記載の方法。
- 前記準備された基板表面が、インターポーザの表面、パッケージの表面、フラットパネルの表面、回路の表面、又はシリコン若しくは非シリコンウエハの表面を含む、請求項13に記載の方法。
- 前記第1の個片化された要素及び前記準備された基板表面が、同じ材料で構成される、請求項13に記載の方法。
- 前記第1の個片化された要素及び前記準備された基板表面が、異なる材料で構成される、請求項13に記載の方法。
- 前記第1の個片化された要素の前記第1の表面が流動性の相互接続材料を含む、請求項13に記載の方法。
- システムであって、
洗浄される表面に所定に近接して配置されるように設けられたメガソニック変換器であって、前記洗浄される表面に音波エネルギーを印加するように設けられたメガソニック変換器と、
前記変換器に連結されるか又は前記変換器に一体化された1つ以上のブラシであって、前記1つ以上のブラシは、所定の接触圧で前記洗浄される表面と接触するように設けられ、かつ、前記メガソニック変換器が前記音波エネルギーを前記洗浄される表面に印加する間、前記洗浄される表面にブラシ掛けするように設けられる、1つ以上のブラシと、を備える、システム。 - 前記ブラシのうちの1つ以上に連結された回転ユニットを更に備え、前記回転ユニットは、前記メガソニック変換器が前記音波エネルギーを前記洗浄される表面に印加している間に、前記1つ以上のブラシを前記洗浄される表面に対して回転させるように設けられている、請求項20に記載のシステム。
- 前記回転ユニットが、前記1つ以上のブラシを回転させるために作動液を使用するように設けられた油圧回転ユニットを含む、請求項21に記載のシステム。
- 前記洗浄される表面を受容するように設けられた回転ターンテーブルを更に備え、前記ターンテーブルは、前記メガソニック変換器が前記洗浄される表面に前記音波エネルギーを印加し、前記1つ以上のブラシが前記洗浄される表面にブラシ掛けする間、前記洗浄される表面をスピンさせるように設けられている、請求項20に記載のシステム。
- 前記メガソニック変換器が前記音波エネルギーを前記洗浄される表面に印加し、前記1つ以上のブラシが前記洗浄される表面にブラシ掛けする間、前記変換器及び前記1つ以上のブラシを前記洗浄される表面にわたって前後横方向に移動させるように設けられた横方向の搬送装置を更に備える、請求項20に記載のシステム。
- 前記洗浄される表面の上に配設された洗浄溶液を更に備え、前記変換器は、前記洗浄溶液を介して前記洗浄される表面に前記音波エネルギーを印加するように設けられている、請求項20に記載のシステム。
- 前記洗浄される表面の上方に配置され、前記洗浄される表面上の流体の高さを検出するように設けられた流体高さセンサを更に備え、前記流体高さセンサは、前記流体の前記高さが第1の所定量未満であるときに少なくとも第1の信号を流体源に送信し、前記流体の前記高さが第2の所定量よりも大きいときに、第2の信号を前記流体源に送信するように設けられている、請求項20に記載のシステム。
- 前記システムが、1つ以上の基板、ウエハ、及び/又は半導体ダイの1つ以上の表面を洗浄するように設けられている、請求項20に記載のシステム。
- 前記1つ以上のブラシが、前記洗浄される表面に対応する1つ以上の構成要素の1つ以上の縁部をブラシ掛けするように設けられている、請求項20に記載のシステム。
- 1つ以上の超小型電子構成要素を処理表面上に装着する工程と、
統合メガソニックブラシシステムを前記超小型電子構成要素に近接して位置付ける工程であって、前記統合メガソニックブラシシステムは、メガソニック変換器と、前記メガソニック変換器に結合された又は前記メガソニック変換器と一体化された1つ以上のブラシと、を含む、工程と、
前記メガソニック変換器を介して、前記1つ以上の超小型電子構成要素に音波エネルギーを印加する工程と、
前記メガソニック変換器が前記音波エネルギーを前記1つ以上の超小型電子構成要素に印加している間に、前記1つ以上のブラシによって前記1つ以上の超小型電子構成要素の1つ以上の表面を同時にブラシ掛けする工程と、を含む、方法。 - 同時に前記変換器を介して前記音波エネルギーを印加しつつ、前記1つ以上のブラシによって前記1つ以上の超小型電子構成要素の前記1つ以上の表面をブラシ掛けしながら、前記処理表面を回転させる工程を更に含む、請求項29に記載の方法。
- 同時に前記変換器を介して前記音波エネルギーを印加しつつ、前記1つ以上のブラシによって前記1つ以上の超小型電子構成要素の前記1つ以上の表面をブラシ掛けしながら前記統合メガソニックブラシシステムを横方向にスキャンする工程を更に含む、請求項29に記載の方法。
- 所定量の洗浄液を前記1つ以上の超小型電子構成要素の前記1つ以上の表面に塗布する工程と、流体源と連通する流体高さセンサを用いて前記所定量の洗浄液を制御する工程と、を更に含む、請求項29に記載の方法。
- 前記洗浄溶液を通じて、前記メガソニック変換器を介して前記1つ以上の超小型電子構成要素に前記音波エネルギーを印加する工程を更に含む、請求項32に記載の方法。
- 超小型電子アセンブリを形成する方法であって、
基板の一方又は両方の表面上に保護層を設ける工程と、
前記基板をキャリア上に固定する工程と、
前記基板を前記キャリアに固定された多少のダイに個片化する工程と、
前記ダイが前記キャリアに固定されている間に、前記ダイの少なくとも第1の表面を処理する工程と、
前記キャリアを第1の既知の良好なダイの外周の周りで切断する工程と、
前記第1の既知の良好なダイを前記キャリアから除去し、前記キャリアの少なくとも一部は前記第1の既知の良好なダイの第2の表面に固定されている工程と、
前記第1の既知の良好なダイを、準備された基板表面に取り付ける工程であって、前記第1の既知の良好なダイの第1の表面が前記準備された基板表面に取り付けられている、工程と、
前記キャリアの前記部分を、前記第1の既知の良好なダイの前記第2の表面から除去する工程と、を含む、方法。 - 前記第1の既知の良好なダイが前記キャリアに固定されている間に、前記第1の既知の良好なダイの前記第1の表面をプラズマ活性化する工程を更に含む、請求項34に記載の方法。
- 前記第1の既知の良好なダイが前記準備された基板表面に接合されている間に、前記第1の既知の良好なダイを熱処理する工程を更に含む、請求項34に記載の方法。
- 接合するために前記第1の既知の良好なダイの前記第2の表面を準備する工程と、
前記キャリアから第2の既知の良好なダイを除去する工程と、
前記第2の既知の良好なダイの第1の表面を前記第1の既知の良好なダイの前記第2の表面に取り付けて、積層ダイ配置を形成する工程と、を更に含む、請求項34に記載の方法。 - 超小型電子アセンブリを形成する方法であって、
個片化された第1の既知の良好なダイをキャリア上で洗浄する工程と、
前記キャリアを前記第1の既知の良好なダイの外周の周りで切断する工程と、
前記第1の既知の良好なダイを前記キャリアから除去し、前記キャリアの少なくとも一部は前記第1の既知の良好なダイの第2の表面に固定されている工程と、
前記第1の既知の良好なダイの第1の表面を、準備された基板の表面に取り付ける工程と、
前記キャリアの前記部分を、前記第1の既知の良好なダイの前記第2の表面から除去する工程と、を含む、方法。 - 前記第1の既知の良好なダイ及び前記準備された基板を熱処理する工程を更に含む、請求項38に記載の方法。
- 前記第1の既知の良好なダイの前記第2の表面を洗浄する工程と、
前記第1の既知の良好なダイの前記第2の表面をプラズマ活性化する工程と、
第2の既知の良好なダイの第1の表面を洗浄する工程と、
前記第2の既知の良好なダイの第1の表面を前記第1の既知の良好なダイの前記第2の表面に取り付けて、積層ダイ配置を形成する工程と、
前記積層ダイ配置を熱処理する工程と、を更に含む、請求項38に記載の方法。 - 1つ以上の更なる既知の良好なダイを前記第2の既知の良好なダイに、及び後続の既知の良好なダイに取り付けて、前記積層ダイ配置を形成する工程を更に含む、請求項40に記載の方法。
- 超小型電子アセンブリを形成する方法であって、
洗浄され個片化された第1の既知の良品ダイをキャリアから切断する工程と、
前記第1の既知の良好なダイを前記キャリアから除去し、前記キャリアの少なくとも一部は前記第1の既知の良好なダイの第2の表面に固定されている工程と、
前記第1の既知の良好なダイの第1の表面を、準備された基板の表面に取り付ける工程と、
前記キャリアの前記部分を、前記第1の既知の良好なダイの前記第2の表面から除去する工程と、を含む、方法。 - 前記第1の既知の良好なダイが前記準備された基板に接合されている間に、前記第1の既知の良好なダイの前記第2の表面を準備する工程と、
前記キャリアから第2の既知の良好なダイを除去する工程と、
前記第2の既知の良好なダイの第1の表面を前記第1の既知の良好なダイの前記第2の表面に取り付けて、積層ダイ配置を形成する工程と、を更に含む、請求項42に記載の方法。 - 前記積層ダイ配置が前記準備された基板に接合されている間に、前記積層ダイ配置を熱処理する工程を更に含む、請求項43に記載の方法。
- 超小型電子アセンブリを形成する方法であって、
個片化され、洗浄された既知の良好なダイをキャリアから切断する工程であって、前記キャリアの少なくとも一部が、前記既知の良好なダイの第2の表面に固定されている、工程と、
前記既知の良好なダイの第1の表面を、準備された基板の表面に取り付ける工程と、
前記キャリアの前記部分を、前記既知の良好なダイの前記第2の表面から除去する工程と、を含む、方法。 - 超小型電子アセンブリを形成する方法であって、
個片化され、洗浄された第1の既知の良好なダイをキャリアから切断する工程と、
前記第1の既知の良好なダイの洗浄された表面を、準備された基板の表面に取り付ける工程と、を含む、方法。 - 前記第1の既知の良好なダイの第1の表面が前記準備された基板の前記表面に接合されている間に、前記第1の既知の良好なダイの第2の表面を準備する工程と、
第2の既知の良好なダイの第1の表面を前記第1の既知の良好な第1のダイの前記第2の表面に取り付けて、積層ダイ配置を形成する工程と、を更に含む、請求項46に記載の方法。 - 前記積層ダイ配置が前記準備された基板に接合されている間に、前記積層ダイ配置を熱処理する工程を更に含む、請求項47に記載の方法。
- 前記第1の既知の良好なダイの前記洗浄された表面が、流動性相互接続材料を含む、請求項46に記載の方法。
- 前記第1の既知の良好なダイの前記洗浄された表面が、金属パッド又は誘電体表面を含む、請求項46に記載の方法。
- 前記準備された基材の前記表面が、金属パッド又は誘電体表面を含む、請求項46に記載の方法。
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US20180308819A1 (en) | 2018-10-25 |
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