TWI790817B - 用於處理半導體晶粒構件的方法 - Google Patents

用於處理半導體晶粒構件的方法 Download PDF

Info

Publication number
TWI790817B
TWI790817B TW110142410A TW110142410A TWI790817B TW I790817 B TWI790817 B TW I790817B TW 110142410 A TW110142410 A TW 110142410A TW 110142410 A TW110142410 A TW 110142410A TW I790817 B TWI790817 B TW I790817B
Authority
TW
Taiwan
Prior art keywords
die
semiconductor die
die members
cleaning
carrier
Prior art date
Application number
TW110142410A
Other languages
English (en)
Other versions
TW202209590A (zh
Inventor
賽普里恩 艾米卡 烏佐
Original Assignee
美商英帆薩斯邦德科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商英帆薩斯邦德科技有限公司 filed Critical 美商英帆薩斯邦德科技有限公司
Publication of TW202209590A publication Critical patent/TW202209590A/zh
Application granted granted Critical
Publication of TWI790817B publication Critical patent/TWI790817B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
    • H01L21/6704—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing
    • H01L21/67046—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing using mainly scrubbing means, e.g. brushes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
    • H01L21/6704—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing
    • H01L21/67051—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing using mainly spraying means, e.g. nozzles
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6838—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping with gripping and holding devices using a vacuum; Bernoulli devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H01L2221/68322—Auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68336—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80003—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/80006—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
    • H01L2224/80011—Chemical cleaning, e.g. etching, flux
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
    • H01L2224/80012—Mechanical cleaning, e.g. abrasion using hydro blasting, brushes, ultrasonic cleaning, dry ice blasting, gas-flow
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
    • H01L2224/80013—Plasma cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
    • H01L2224/80019—Combinations of two or more cleaning methods provided for in at least two different groups from H01L2224/8001 - H01L2224/80014
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H01L2224/8003—Reshaping the bonding area in the bonding apparatus, e.g. flattening the bonding area
    • H01L2224/80031—Reshaping the bonding area in the bonding apparatus, e.g. flattening the bonding area by chemical means, e.g. etching, anodisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

代表性實施方式提供用於處理積體電路(IC)晶粒之技術及系統。經製備用於緊密的表面結合(至其他晶粒、至基板、至另一表面等)之晶粒可運用最小處置來處理，以防止該些晶粒之表面或邊緣之污染。該些技術包括當該些晶粒在切割片或其他裝置處理膜或表面上時處理晶粒。系統包括經配置以同時執行多個清潔程序之整合式清潔組件。

Description

用於處理半導體晶粒構件的方法
以下描述係關於積體電路(「IC」)之處理。更具體而言，以下描述係關於用於處理IC晶粒之裝置及技術。
優先權主張及相關申請案之交叉參考
本申請案主張2018年3月26日申請之美國專利申請案第15/936,075號及2017年4月21日申請之美國臨時申請案第62/488,340號以及2017年9月27日申請之美國臨時申請案第62/563,847號在35 U.S.C.§ 119(e)(1)下之權益，該些申請案特此以引用之方式併入。
對於諸如整合式晶片及晶粒之微電子元件的更緊湊實體配置的需要隨著攜帶型電子裝置之快速發展、物聯網之擴展、奈米級整合、亞波長光學整合等等已變得愈發強烈。僅作為實例，裝置通常被稱作整合具有大功率資料處理器之蜂巢式電話、記憶體及諸如全球定位系統接收器之輔助裝置、電子攝影機及區域網路連接件以及高解析度顯示器及相關聯影像處理晶片之功能的「智慧型電話」。此等裝置可提供諸如以下各者之功能：完整網際網路連接性，包括全解析度視訊之娛樂、導航、電子銀行、感測器、記憶體、微處理器、保健電子件、自動電子件等等，全部均在袖珍裝置中實現。複雜的攜帶型裝置需要將眾多晶片及晶粒封裝至較小空間中。
微電子元件常常包含諸如砷化矽或砷化鎵或其他之半導體材料的薄平板。晶片及晶粒通常經設置為個別預封裝單元。在一些單元設計中，將晶粒安裝至基板或晶片載體，隨後將該基板或晶片載體安裝於電路面板(諸如印刷電路板(printed circuit board；PCB))上。晶粒可經設置於便於在製造期間及在將晶粒安裝於外部基板上期間對晶粒之處置的封裝中。舉例而言，許多晶粒經設置於適合於表面黏著的封裝中。此通用類型之眾多封裝經提議用於各種應用。最常見地，此等封裝包括介電質元件，其通常被稱作具有形成為介電質上之經鍍覆或經蝕刻金屬結構的端子之「晶片載體」。通常藉由諸如沿晶粒載體延伸之薄跡線之導電特徵及藉由在晶粒之接觸件與端子或跡線之間延伸的精細引線或電線將端子連接至晶粒之接觸件(例如，結合墊或金屬柱)。在表面黏著操作中，封裝可置放至電路板上，以使得封裝上之每一端子與電路板上之對應接觸墊對準。通常將焊料或其他結合材料設置於端子與接觸墊之間。可藉由加熱組裝件以便熔化或「回焊」焊料或以其他方式活化結合材料來將封裝永久地結合在適當的位置。
許多封裝包括呈典型地直徑介於約0.025mm與約0.8mm(1密耳與30密耳)之間且附接至封裝之端子的焊球形式的焊料固體。具有自其底部表面(例如，與晶粒之正面相對的表面)突起的焊球之陣列的封裝通常被稱作球狀柵格陣列或「BGA」封裝。藉由自焊料形成之較薄層或焊盤將被稱作焊盤柵格陣列或「LGA」封裝之其他封裝固定至基板。此種類型之封裝可係非常緊密的。通常被稱作「晶片級封裝」之某些封裝佔據等於或僅略大於併入於封裝中之裝置之面積的電路板之面積。此比例係有利的，此係因為其降低組裝件之整體大小且准許在基板上之各種裝置之間使用短互連件，此隨後限制裝置之間的信號傳播時間且因此便於以高速操作組裝件。
半導體晶粒亦可經設置於「堆疊式」配置中，其中例如，一個 晶粒設置於載體上，且另一晶粒安裝在第一晶粒之頂部。此等配置可允許將多個不同晶粒安裝於電路板上之單個覆蓋面積內，且可進一步藉由在晶粒之間提供短互連件來便於高速操作。通常，此互連距離可僅略大於晶粒自身之厚度。對於將在晶粒封裝之堆疊內達成的互連，用於機械及電氣連接之互連結構可設置於每一晶粒封裝(除了最高封裝)以外之兩側(例如，面)上。此已例如藉由在安裝有晶粒之基板的兩側上設置接觸墊或焊盤來得以實現，該些墊藉由導電通孔或其類似者經由基板連接。堆疊式晶片配置及互連結構之實例提供於美國專利申請公開案第2010/0232129號中，該公開案之揭示內容以引用的方式併入本文中。
晶粒或晶圓亦可以其他三維配置堆疊而作為各種微電子封裝方案之部分。此可包括將一或多個晶粒或晶圓之層堆疊在較大基底晶粒或晶圓上、以豎直或水平配置堆疊多個晶粒或晶圓或堆疊類似或不同基板，其中基板中之一或多者可含有電氣或非電氣元件、光學或機械元件及/或此等元件之各種組合。晶粒或晶圓可使用各種結合技術以堆疊式配置結合，該些結合技術包括直接介電質結合、無黏著劑技術(諸如ZiBond®)或混合式結合技術(諸如DBI®)，兩者可自Invensas結合技術公司(先前是Ziptronix公司)、Xperi公司購得(例如，參見美國專利第6,864,585號及第7,485,968號，其全文併入本文中)。當使用直接結合技術結合堆疊式晶粒時，通常需要待結合之晶粒的表面極扁平且平滑。舉例而言，通常，該些表面之表面拓樸應具有極小變化，使得該些表面可緊密地配合以形成持續結合。舉例而言，通常較佳的是，結合表面之粗糙度之變化小於3nm且較佳地小於1.0nm。
一些堆疊式晶粒配置對堆疊式晶粒之一個或兩個表面上之顆粒或污染的存在敏感。舉例而言，自處理步驟剩餘之顆粒或來自晶粒處理或工具之污染可產生堆疊式晶粒之間的經不佳結合之區或其類似者。晶粒處理期間之 額外處置步驟可進一步加重問題，從而留下非所需殘留物。
本發明的一態樣為一種形成微電子組裝件之方法，其包含：在基板之一個或兩個表面上提供保護層；將該基板固定至載體上；將該基板單一化成固定至該載體之一定數量之晶粒；當該些晶粒固定至該載體時處理該些晶粒之至少一第一表面；圍繞第一晶粒之周邊切割該載體，該切割形成固定至該第一晶粒之第二表面之該載體的一部分；當該載體之該部分固定至該第一晶粒之該第二表面時自該一定數量之晶粒移除該第一晶粒；以及將該第一晶粒附接至基板之經製備表面，該第一晶粒之該第一表面附接至該基板之該經製備表面。
本發明的另一態樣為一種形成微電子組裝件之方法，其包含：將保護塗層沈積至基板之一個或兩個表面上；將該基板固定至切割片上；將該基板單一化成固定至該切割片之一定數量之經單一化元件；當該些經單一化元件固定至該切割片時清潔該些經單一化元件之第一表面；將該些經單一化元件暴露至紫外線幅射；拉伸該切割片以在固定至該切割片之該些經單一化元件之間形成或延伸間隙；當該些經單一化元件固定至該切割片時清潔來自該些經單一化元件之該第一表面之該保護塗層；當該些經單一化元件固定至該切割片時電漿灰化該些經單一化元件之該第一表面；當該些經單一化元件固定至該切割片時重新清潔該些經單一化元件之該第一表面；當該些經單一化元件固定至該切割片時電漿活化該些經單一化元件之該第一表面；當該些經單一化元件固定至該切割片時再次清潔該些經單一化元件之該第一表面；沿著該些間隙在該切割片中形成穿孔；沿著該切割片中之該些穿孔運用真空工具自該切割片衝壓第一經單一化元件，該切割片之一部分固定至該第一經單一化元件之第二表面且 保護該第一經單一化元件之該第二表面免受該真空工具影響；將該第一經單一化元件置放至經製備基板表面上；將該第一經單一化元件附接至該經製備基板表面，該第一經單一化元件之該第一表面附接至該經製備基板表面；熱處理該第一經單一化元件及該經製備基板表面；清潔該第一經單一化元件之該第二表面；電漿活化該第一經單一化元件之該第二表面；運用該真空工具自該切割片衝壓第二經單一化元件，該切割片之另一部分固定至該第二經單一化元件之第二表面且保護該第二經單一化元件之該第二表面免於受該真空工具影響；將該第二經單一化元件之第一表面附接至該第一經單一化元件之該第二表面以形成堆疊式微電子配置；以及熱處理該堆疊式微電子配置。
本發明的又一態樣為一種系統，其包含：超高頻音波轉換器，其經配置以安置成與待清潔之表面相距預定近程，該超高頻音波轉換器經配置以將音波能量施加至該待清潔之表面；以及一或多個刷子，其耦接至該轉換器或與該轉換器成一體，該一或多個刷子經配置以在預定接觸壓力下與該待清潔之表面接觸，且經配置以在該超高頻音波轉換器將該音波能量施加至該待清潔之表面時刷洗該待清潔之表面。
本發明的另一態樣為一種方法，其包含：將一或多個微電子組件裝載至處理表面上；將整合式超高頻音波刷子系統定位成接近於該些微電子組件，該整合式超高頻音波刷子系統包括超高頻音波轉換器及耦接至該超高頻音波轉換器或與該超高頻音波轉換器成一體之一或多個刷子；經由該超高頻音波轉換器將音波能量施加至該一或多個微電子組件；以及當該超高頻音波轉換器將該音波能量施加至該一或多個微電子組件時經由該一或多個刷子同時刷洗該一或多個微電子組件之一或多個表面。
本發明的又一態樣為一種形成微電子組裝件之方法，其包含：在基板之一個或兩個表面上提供保護層；將該基板固定至載體上；將該基板單 一化成固定至該載體之一定數量之晶粒；當該些晶粒固定至該載體時處理該些晶粒之至少一第一表面；圍繞第一已知良好晶粒之周邊切割該載體；自該載體移除該第一已知良好晶粒，其中該載體之至少一部分固定至該第一已知良好晶粒之第二表面；將該第一已知良好晶粒附接至經製備基板表面，該第一已知良好晶粒之第一表面附接至該經製備基板表面；以及自該第一已知良好晶粒之該第二表面移除該載體之該部分。
本發明的一態樣為一種形成微電子組裝件之方法，其包含：清潔載體上之經單一化第一已知良好晶粒；圍繞該第一已知良好晶粒之周邊切割該載體；自該載體移除該第一已知良好晶粒，其中該載體之至少一部分固定至該第一已知良好晶粒之第二表面；將該第一已知良好晶粒之第一表面附接至經製備基板之表面；以及自該第一已知良好晶粒之該第二表面移除該載體之該部分。
本發明的又一態樣為一種形成微電子組裝件之方法，其包含：自載體切割經清潔且經單一化之第一已知良好晶粒；自該載體移除該第一已知良好晶粒，其中該載體之至少一部分固定至該第一已知良好晶粒之第二表面；將該第一已知良好晶粒之第一表面附接至經製備基板之表面；以及自該第一已知良好晶粒之該第二表面移除該載體之該部分。
本發明的另一態樣為一種形成微電子組裝件之方法，其包含：自載體切割經單一化且經清潔之已知良好晶粒，該載體之至少一部分固定至該已知良好晶粒之第二表面；將該已知良好晶粒之第一表面附接至經製備基板之表面；以及自該已知良好晶粒之該第二表面移除該載體之該部分。
本發明的一態樣為一種形成微電子組裝件之方法，其包含：自載體切割經單一化且經清潔之第一已知良好晶粒；將該第一已知良好晶粒之經清潔表面附接至經製備基板之表面。
100:實例晶粒或裝置處理序列
200:實例晶粒處理序列/程序
302:晶圓
304:保護塗層/抗蝕劑層/抗蝕劑
306:切割片/載體
308:黏著劑/黏著劑層
310:晶粒/已知良好晶粒
312:非PVA旋轉刷子
314:收納表面/結合表面/基板
316:額外晶粒/已知良好晶粒
402:夾環
404:間隙
406:工具/經加熱刀
408:真空工具/裝置拾取頭部/真空拾取裝置
410:孔
600:第二實例具體實例
700:實例晶粒處理序列/程序
902:處理設備/轉台
904:超高頻音波轉換器
906:刷子
1000:整合式超高頻音波刷子系統
1002:超高頻音波轉換器
1004:刷子/刷子頭部
1006:流體高度感測器
1008:旋轉單元
1010:導管
參考附圖闡述詳細描述。在該些圖中，參考數字之最左側數位識別首次出現該參考數字之圖。在不同圖中使用相同參考數字指示類似或相同物件。
對此論述，在圖中所說明之裝置及系統展示為具有大量組件。如本文中所描述，裝置和/或系統之各種實施可包括較少組件且保持在本發明之範圍內。替代地，裝置及/或系統之其他實施可包括額外組件或所描述組件之各種組合，且保持在本發明之範疇內。
[圖1]為說明使用旋轉板之實例晶粒處理序列之文本流程圖。
[圖2]為根據一具體實例之說明對切割帶或裝置處理膜或表面執行之實例晶粒處理序列的文本流程圖。
[圖3]為根據一具體實例之圖2之實例晶粒處理序列的圖形流程圖。
[圖4]圖解說明根據一具體實例之用於將晶粒自切割片傳送至晶圓或表面之實例步驟。
[圖5]說明根據一具體實例之晶粒被移除之實例切割片。
[圖6]為根據一第二具體實例之說明對切割帶或裝置處理膜或表面執行之實例晶粒處理序列的文本流程圖。
[圖7]為根據一第三具體實例之說明對切割帶或裝置處理膜或表面執行之實例晶粒處理序列的文本流程圖。
[圖8]為根據一具體實例之圖7之實例晶粒處理序列的圖形流程圖。
[圖9A及圖9B]說明根據各種具體實例之實例晶粒清潔系統。
[圖10A及圖10B]說明根據其他具體實例之實例晶粒清潔系統。
概述
揭示用於處理積體電路(IC)之技術及系統之各種實施例。經製備用於緊密的表面結合(至其他晶粒、至基板、至另一表面等)之晶粒可運用最小處置來處理，以防止晶粒之表面或邊緣之污染。
根據各種具體實例，該些技術包括當晶粒在切割片或其他裝置處理膜或表面上時處理晶粒。舉例而言，當晶粒在切割片上時，可清潔、灰化且活化晶粒(從而在處理期間去除針對污染之數個處理步驟及機會)。舉例而言，該處理可製備待以堆疊式配置結合之晶粒。在處理之後，可直接自切割片拾取晶粒且晶粒可置放於經製備晶粒收納表面(另一晶粒、基板等)上以用於結合至表面。
在各種具體實例中，使用所揭示之技術可降低晶粒製造及處理成本且可降低製造包括晶粒之電子封裝之複雜性。待使用「ZIBOND®」及「直接結合互連(DBI®)」技術堆疊及結合之晶粒可尤其受益，該些晶粒可能易受顆粒及污染物影響。不論製造程序是否包括使用兩個對應的半導體及/或絕緣層之間的低溫共價鍵結合兩個表面(該程序被稱為ZIBOND®)，或不論該製造程序是否亦包括形成互連以及結合技術(該程序被稱為DBI®)，通常都需要橫跨結合表面之高程度之平坦度及清潔度。
所揭示之技術亦可有益於其他應用，其中例如裝置之結合區可包含可流動塊狀材料，諸如用於結合之任何形式的可焊材料。最小化或去除結合表面之間的顆粒或污跡可顯著地改良良率及可靠性。在一實施中，在使用較 大晶粒或晶圓載體，諸如較大切割片、使用多個晶粒或晶圓載體等等之情況下，可一次處理大批次晶粒。
在一些具體實例中，可去除若干程序步驟，從而降低製造複雜性及成本，同時改良晶粒之總體清潔度(例如，降低顆粒、污染物、殘留物等之出現)。晶粒之縮減的處置亦可最小化顆粒產生。
圖1處展示流程圖，其說明在處理期間使用旋轉板來固持晶粒之實例晶粒或裝置處理序列100。在區塊1至4處，該程序藉由以下操作製備基板例如矽晶圓而開始：將保護塗層施加至晶圓之一個或兩個側；將晶圓單一化成切割片或其類似者上之晶粒(亦即，第一組晶粒)；將晶粒及切割片暴露至紫外線(ultraviolet；UV)輻射且拉伸切割片；以及將晶粒傳送至旋轉板，其中晶粒面向上。在區塊5至9處，該程序包括以下步驟：清潔來自晶粒之有機層；電漿灰化晶粒之頂部表面以移除晶粒上之任何剩餘的有機殘留物；以及運用去離子水(DI)進一步清潔晶粒，例如電漿活化晶粒之頂部表面及重新清潔晶粒。
在區塊10處，晶粒經傳送至翻板，以將晶粒定位成面向下(亦即，晶粒之主動表面(例如，第一表面)面向下或朝向翻板)。在區塊11處，晶粒經傳送至取放台。在此配置中，晶粒自其背表面(例如，與面、前表面或第一表面相對之表明或主動表面)拾取且在經製備收納表面上置放成面向下以用於結合。為了拾取晶粒，拾取真空工具(例如)接觸與經結合表面相對之晶粒之背表面或第二表面。
收納表面可包括經製備表面，諸如基板、另一晶粒、介電質表面、聚合層、導電層、插入件之表面、另一封裝、平板之表面或甚至另一電路或矽晶圓或非矽晶圓之表面。晶粒之材料可與收納基板之材料類似或相異。並且，晶粒之表面可與收納基板之表面相異。
在區塊13處，置放於基板上之晶粒經熱處理以增強晶粒之表面與基板之收納表面之間的結合。在一些具體實例中，額外晶粒可附接至經結合晶粒之背(例如，第二)表面或可用表面。背表面可於其中另外具有主動裝置。
在區塊14至18處，清潔、電漿灰化、重新清潔、電漿活化且再次清潔經結合晶粒之收納表面，例如基板，及經暴露背表面。在區塊19處，第二組晶粒(具有如在區塊1至11處所描述之先前製備之頂部表面)可附接至第一組晶粒(其形成堆疊式晶粒配置)。在一實例中，第二晶粒之經製備前表面(例如，第一表面)附接至第一晶粒之經暴露背表面(例如，第二表面)。在區塊20處，具有第一及第二晶粒之組裝件經熱處理以增強堆疊之結合。對於待添加至堆疊式晶粒配置之額外晶粒(例如，第三或更多晶粒)，該程序循環返回至區塊14，且繼續直至所要晶粒數量已經添加至每一堆疊為止。
在各種實例中，如所描述之製造程序可使用至少或大約13+7(n-1)；n>0個步驟來完成(其中n=堆疊中之所要晶粒數量)。
在一些狀況下，儘管該程序中把包括許多清潔步驟，但晶粒仍在晶粒之一或多個表面上留有一些污染物或顆粒。舉例而言，晶粒之頂部或前表面可被清潔而不含污染物，而晶粒之底部或背表面可留有顆粒或污染物。另外，在多個處理步驟期間處置晶粒可將顆粒或污染物添加至晶粒。舉例而言，在處置期間使用之工具可將污染物傳送至晶粒。顆粒或缺陷在晶粒上之位置可判定顆粒或缺陷對於堆疊式配置是否可能潛在地成問題。舉例而言，一些顆粒及且缺陷可造成堆疊式晶粒之間的不佳結合等等。在另一實例中，裝置翻轉步驟可為污染物或缺陷之來源，因為裝置之經清潔頂部表面在翻轉操作之後與另一表面接觸。
實例實施
圖2為根據一具體實例之說明實例晶粒處理序列200之流程圖，其中晶粒在諸如切割帶(「切割片」)或其他處理片之載體上經處理。圖3展示根據一實例實施之程序200之圖形流程圖表示。參考圖2及圖3論述程序200，然而，除非另外規定，否則在此論述中提及之「區塊」指代圖2處之經編號區塊。
在區塊1處，處理晶圓302，包括將一或多個保護層或塗層304添加至晶圓302之一個或兩個表面(區塊2)。保護層304可包括光阻劑或類似保護劑。晶圓302經傳送至切割片306且運用黏著劑308暫時固定至切割片306。在區塊3處，晶圓302在切割片306上時經單一化成晶粒310。
在區塊4處，當晶粒310附接至切割片306時，清潔晶粒310包括晶粒310之邊緣以移除顆粒。可機械地及/或化學地執行清潔。舉例而言，晶粒310可受精細CO2顆粒轟擊及/或暴露於刷子清潔步驟，該刷子清潔步驟可超音波或超高頻音波增強。刷子312(如圖3中所展示)可相對於晶粒310表面在任何方向上旋轉或以其他方式移動。晶粒310可另外或替代地暴露於濕式蝕刻、噴水器等等。在區塊5處，切割片306可稍微拉伸以在晶粒310之間產生空間，從而適應清潔晶粒310之邊緣。切割片306上之晶粒310可暴露於紫外線(UV)輻射以分解抗蝕劑304及/或黏著劑308層。若需要製備晶粒310以用於自切割片306移除，則切割片306可經進一步拉伸。
在區塊6處，當晶粒310在切割片306上時，抗蝕劑層304之剩餘殘留物係自晶粒310之經暴露表面(例如，第一表面)清潔掉。可使用清潔溶液以及諸如本文中所描述之其他化學及/或機械清潔技術。另外，當晶粒310保留在切割片306上時，晶粒310之第一(例如，經暴露)表面經電漿灰化(例如，氧灰化)，以移除任何非所需有機殘留物。
在區塊7處，使用濕式清潔技術(例如，去離子水、清潔溶液 等)再次清潔晶粒310之第一表面，該濕式清潔技術可包括超高頻音波洗滌、機械刷子擦洗或攪動或其他適合的清潔技術。舉例而言，在一些情況下，在灰化步驟之後，額外清潔可藉由濕式清潔及/或藉由CO2顆粒流、或旋轉刷子、噴水器、或超高頻音波輔助濕式清潔技術或其組合來執行。
在區塊8處，晶粒310之第一表面經電漿活化(例如，氮電漿等)以產生或增強用於堆疊晶粒310之結合。在區塊9處，經活化晶粒310使用濕式清潔技術(例如，去離子水、熱去離子水、水蒸氣或高pH清潔溶液等)加以清潔，該濕式清潔技術可運用超高頻音波或上文所描述之清潔技術之組合或其類似者來增強。
在區塊10處，晶粒310(例如，已知良好晶粒)310自切割片306傳送至收納表面314(經製備晶粒、基板等)以用於結合至收納表面314。在一些狀況下，可對晶粒310之經暴露表面及/或收納表面314執行上文所論述之各種清潔及表面活化程序。
在各種具體實例中，晶粒310使用「衝壓」技術自切割片306傳送(如圖4及圖5中所說明)。衝壓技術允許傳送晶粒310(例如，已知良好晶粒)且不污染晶粒310之表面或邊緣。並且，衝壓技術允許晶粒310(例如，已知良好晶粒)使用DBI混合結合技術、焊料焊凸或其類似者結合至「面向下」之結合表面314，該結合表面314與面向收納表面314之晶粒310之第一表面在一起。
在一個實例中，如圖4(A)、圖5(A)及圖5(B)中所展示，經拉伸切割片306係由夾環402或框架或其類似者固持。切割片306上之晶粒310係由間隙404(約2um至200um寬)分離，該些間隙可至少部分地歸因於拉伸。如圖4(B)及圖4(C)處所展示，可使用各種工具406諸如切割葉片、熱刀、光學刀(雷射切除)等中之一或多者沿著晶粒310之間的間隙404對切割 片306進行穿孔。在一具體實例中，穿孔允許自切割片306個別地衝壓晶粒310(例如，已知良好晶粒)，從而使其他晶粒310在切割片306上處於適當位置。真空工具408或其類似者(亦即，「拾取頭部」)可用於例如自經穿孔切割片306(如圖4(B)所展示)、自切割片306之背部衝壓個別晶粒310。真空工具408能夠自與晶粒310相對之切割帶306之表面傳送晶粒310(例如，已知良好晶粒)，其中切割帶306(或處理片)之一部分在工具408與晶粒310之間處於適當位置。因此，晶粒310(例如，已知良好晶粒)到達結合表面314，且真空工具408不污染晶粒310之待結合表面或邊緣。保持附接至晶粒310(例如，已知良好晶粒)之背表面之帶306的部分進而保護晶粒310免於與工具408接觸而被污染。
圖4(D)展示其中晶粒310被移除之切割片306之剖面圖。切割片306中存在孔410，此係由於切割片306之一部分及晶粒310被移除。(此在圖5(A)至圖5(C)處進一步展示)圖4(E)展示置放於基板314上以用於結合之數個晶粒310。
在另一具體實例中，裝置拾取頭部408(例如，真空工具)藉由切割片306自晶粒310(例如，已知良好晶粒)之背側拾取晶粒310(例如，已知良好晶粒)，與此同時對應的工具運用雷射源(或其類似者)圍繞晶粒310之周邊切除切割片306。在一些應用中，在藉由真空工具408自背側拾取晶粒310期間，經加熱刀406邊緣可用於圍繞晶粒310熔融切割片306以將晶粒310與切割片306完全分離。惰性氣體可施加至晶粒310之表面以防止來自裝置分離步驟之煙霧或其他污染物污染晶粒310之經清潔表面。在其他具體實例中，真空可用於代替惰性氣體，而在另外的具體實例中，惰性氣體及真空兩者用於在裝置分離程序期間保護晶粒310之表面。
在各種實施中，晶粒310之經清潔暴露表面不被除收納基板314 之表面之外的任何另一表面或材料觸摸。此與一些先前技術相反，其中晶粒310(例如，已知良好晶粒)之經清潔表面通常接觸收納翻板之某一部分。在其他常見技術中，真空拾取裝置408例如可藉由觸摸經清潔晶粒310表面之一部分來拾取清潔晶粒310(例如，已知良好晶粒)，此可致使污染經觸摸表面。
返回參考圖2及圖3，在區塊11處，具有最新堆疊式晶粒310之晶圓或基板314經熱處理(例如，至50至150℉)以加強晶粒310與基板314之結合。在區塊12處，晶粒310之當前經暴露表面(「背表面」或「第二表面」)及基板314藉由化學及/或機械清潔技術(例如，界面活性劑、非PVA旋轉刷子、超高頻音波等)加以製備。此自晶粒310之背表面移除任何剩餘黏著劑308、切割片306、保護層304或其他殘留物。在區塊13處，晶粒310之背表面經電漿活化以準備進一步結合。
在區塊14處，額外經製備晶粒316藉由本文中所揭示之技術分離且與「面向下」(例如，主動側向下、經製備側向下等)之第一表面一起安置在先前置放於例如基板314上之晶粒310之經製備背(例如，第二)表面上。最新添加之晶粒316經熱處理(例如，區塊11)以加強至晶粒310之結合。對於待添加至堆疊式晶粒配置之額外晶粒316(例如，第三或更多晶粒)，該程序循環返回至區塊12，且繼續直至所要晶粒310、316數量已經添加至每一堆疊為止。
在各種實例中，如所描述之製造程序可使用大約11+2(n-1)；n>0個步驟來完成(其中n=堆疊中之所要晶粒310、316數量)。當相較於相對於圖1描述之程序：(13+7(n-1))時，此表示製造步驟之顯著縮減。縮減程序步驟不僅降低來製造成本及複雜性，且亦縮減了污染晶粒310之機會，從而在較低成本之情況下產生較佳品質及較高產出率。經縮減處理步驟轉變為每晶粒310之成本節省，且旋轉板(或類似處理組件)之去除轉變為另外的製 造成本節省。舉例而言，可使用旋轉板一次處理大約50至100個晶粒310，且可使用如所描述之切割片306程序一次處理大約200至10,000個晶粒310或更多。
圖6處展示用於處理切割片306上之晶粒310之第二實例具體實例600。實例具體實例600說明程序步驟中之一些可以不同次序執行，亦包括縮減程序步驟。舉例而言，如先前所描述，在區塊1至3處，晶圓302運用保護塗層304加以處理、在切割片306上經單一化成晶粒310且在切割片306上經清潔。視情況，切割片306可經一定拉伸以適應晶粒310之間的清潔，及/或晶粒310可暴露於UV光以分解抗蝕劑304及黏著劑308。在區塊4處，當晶粒310保留在切割片306上時，晶粒310之第一表面經電漿灰化(例如，氧灰化)，以自第一表面移除任何非所需有機殘留物(或其他污染物)。
在區塊5處，晶粒310之經灰化表面使用如上文所描述之濕式清潔技術(例如，去離子水、清潔溶液等)加以清潔，該濕式清潔技術可包括超高頻音波或其類似者。在區塊6處，晶粒310之第一表面經電漿活化(例如，氮電漿等)以產生或增強用於堆疊晶粒310之結合。在區塊7處，經活化晶粒310暴露於UV光且切割片306部分地拉伸。在區塊8處，經活化晶粒310使用濕式清潔技術(例如，去離子水、熱去離子水、水蒸氣或高pH清潔溶液等)加以清潔，該濕式清潔技術可運用超高頻音波或上文所描述之清潔技術之組合或其類似者來增強。
在區塊9處，晶粒310自切割片306傳送至結合表面314，且使用例如DBI混合結合技術、焊料焊凸或其類似者與「面向下」之第一表面結合。在各種具體實例中，晶粒310使用上文所描述之「衝壓」技術自切割片306傳送(包括對切割片306進行穿孔及使用真空工具408或其類似者傳送晶粒310，而切割片306之一部分保留在晶粒310上以保護晶粒310免於受真空工具408污染)。在區塊10處，晶粒310及基板314經熱處理(例如，至50至150℉)以加 強晶粒310與基板314之結合。在區塊11處，晶粒310之經暴露表面(「背表面」或「第二表面」)及基板314使用化學及/或機械清潔技術(例如，界面活性劑、非PVA旋轉刷子312、超高頻音波等)加以清潔。此自晶粒310之背表面移除任何剩餘黏著劑308或其他殘留物。在區塊12處，晶粒310之背表面經電漿活化以準備進一步結合。
在區塊13處，額外晶粒316可自經穿孔切割片306(如上文所描述)被衝壓且「面向下」置放在先前置放於例如基板314上之晶粒310的背(例如，經暴露)表面上。最新經添加晶粒316經熱處理(例如，區塊10)以加強結合。對於待添加至堆疊式晶粒配置之額外晶粒310、316(例如，第三或更多晶粒)，該程序循環返回至區塊11，且繼續直至所要晶粒310、316數量已經添加至每一堆疊為止。
在各種實例中，如所描述之製造程序可使用大約10+2(n-1)；n>0個步驟來完成(其中n=堆疊中之所要晶粒310、316數量)，從而引起步驟、複雜性及成本之進一步縮減。
圖7為根據第三具體實例之說明對切割帶306執行之另一實例晶粒310處理序列700之流程圖。圖8為根據一實例實施之圖7之實例晶粒處理序列700的圖形表示。在圖7及圖8之實例具體實例中，去除電漿灰化步驟(亦即，圖6之區塊4)，從而縮減程序步驟。
如先前所述，在區塊1至3處，晶圓302運用保護塗層304加以處理、在切割片306上經單一化成晶粒310且在切割片306上經清潔。視情況，切割片306可經一定拉伸以適應晶粒310之間的清潔，及/或晶粒310可暴露於UV光以分解抗蝕劑304及黏著劑308。在區塊4處，晶粒310之第一表面經電漿活化(例如，氮電漿等)以產生或增強用於堆疊晶粒310之結合。在區塊5處，經活化晶粒310使用濕式清潔技術(例如，去離子水、高ph清潔溶液等)加以清 潔，該濕式清潔技術可包括超高頻音波洗滌、攪動或其他適合的清潔技術。在區塊6處，經活化晶粒310暴露於UV光且切割片306部分地拉伸。
在區塊7處，晶粒310自切割片306傳送至結合表面314，且使用DBI混合結合技術、焊料焊凸或其類似者與「面向下」之第一表面結合。在各種具體實例中，晶粒310使用上文所描述之「衝壓」技術自切割片306傳送(包括對切割片306進行穿孔及使用真空工具408或其類似者傳送晶粒310，而切割片306之一部分保留在晶粒310上以保護晶粒310免於受真空工具408污染)。在區塊8處，晶粒310及基板314經熱處理(例如，至50至150℉)以加強晶粒310與基板314之結合。在區塊9處，晶粒310之經暴露表面(「背表面」或「第二表面」)及基板314使用化學及/或機械清潔技術(例如，界面活性劑、甲醇、非PVA旋轉刷子312、超高頻音波等)加以清潔。此自晶粒310之背表面移除任何剩餘黏著劑308或其他殘留物。在區塊10處，晶粒310之背表面經電漿活化以準備進一步結合。
在區塊11處，額外晶粒316可自經穿孔切割片306衝壓且在先前置放於例如基板314上之晶粒310之背表面(例如，經暴露表面)上置放成「面向下」(例如，經製備側向下)。最新經添加晶粒316經熱處理(例如，區塊8)以加強結合。對於待添加至堆疊式晶粒配置之額外晶粒310、316(例如，第三或更多晶粒310、316)，該程序循環返回至區塊9，且繼續直至所要晶粒310、316數量已經添加至每一堆疊為止。
在各種實例中，如所描述之製造程序可使用大約8+2(n-1)；n>0個步驟來完成(其中n=堆疊中之所要晶粒310、316數量)，從而引起步驟、複雜性及成本之進一步縮減。在裝置堆疊步驟之後，堆疊式晶粒310及收納表面314可經進一步處理至後續較高溫度。處理溫度可在介於15分鐘至達至5個小時或更長之時間內介於80至370℃之範圍內。溫度愈低，則處理時間愈 長。
在程序700之一個具體實例中，待處理/切割之晶圓302可在經暴露或第一表面上包括互連件，諸如焊料凸塊或其他可回焊接合材料(未展示)或其類似者。在該具體實例中，可回焊互連接合結構經常以可回焊特徵不直接接觸切割片306之黏著劑層308之方式在切割片306或處理片上安置成面向上。晶圓302可運用覆蓋可回焊互連結構之保護塗層304加以處理。晶圓302在位於切割片306上時經單一化成晶粒310，且在切割片306上時經清潔，如先前相對於以上區塊1至3所描述。視情況，切割片306可經一定拉伸以適應晶粒310與晶粒310之邊緣之間的清潔，及/或晶粒310可暴露於UV光以分解抗蝕劑304及黏著劑308。
在區塊4處，晶粒310之第一表面(例如，經暴露表面)可運用電漿清潔方法(例如，氧灰化等)加以清潔。在區塊5處，切割片306上之晶粒310可使用如上文所描述之濕式清潔技術(例如，去離子水、高ph清潔溶液等)加以進一步清潔，該濕式清潔技術可視需要包括超高頻音波、攪動或其類似者。在區塊6處，經清潔晶粒310及切割片306可暴露於UV光且切割片306可經進一步拉伸。
在區塊7處，晶粒310自切割片306傳送至收納表面314，且使用本文中所描述之技術與「面向下」之第一表面(例如，向下之經製備表面)結合。舉例而言，在一些具體實例中，收納基板314可包含聚合層、非填充底膠或黏著片之部分。在各種具體實例中，晶粒310使用上文所描述之「衝壓」技術自切割片306傳送(包括對切割片306進行穿孔及使用真空工具408或其類似者傳送晶粒310，而切割片306之一部分保留在晶粒310中之每一者上以保護晶粒310免於受真空工具408污染)。
在區塊8處，晶粒310及基板314可經熱處理以將晶粒310電耦接 至收納基板314。在一些應用中，底膠材料可圍繞經結合裝置310形成以將裝置310進一步機械地耦接至基板314收納表面。在區塊9處，經傳送晶粒310之經暴露表面及基板314使用化學及/或機械清潔技術(例如，界面活性劑、甲醇、非PVA旋轉刷子312、超高頻音波等)加以清潔。此自晶粒310之背表面移除任何剩餘黏著劑308或其他殘留物。在區塊10處，經傳送晶粒310之經暴露表面經電漿活化以準備進一步結合。在一些應用中，經結合裝置310可在用以將晶粒310電耦接至收納基板314之熱處理之前加以清潔。
如上文所論述，在各種處理步驟或階段處，晶粒310、316及/或基板314使用化學及/或機械清潔技術(例如，界面活性劑、甲醇、非PVA旋轉刷子312、超高頻音波等)加以清潔。圖9A及圖9B說明根據各種具體實例之實例晶粒清潔系統，其可用於此目的。清潔程序及系統參考晶粒310或基板314之收納表面加以描述，但應理解，該些程序及系統適用於晶粒310、316及基板314以及介電質表面、聚合層、導電層、插入件、封裝、面板、電路、矽或非矽晶圓等等。
參考圖9A，在一實例清潔序列中，待清潔之物件(例如，晶粒310或載體等)經裝載至處理設備902(諸如如所展示之轉台或旋轉板)上以供清潔及/或其他處理。清潔程序包括當晶粒310可在轉台902上旋轉時經由超高頻音波轉換器904將近接超高頻音波能量施加至清潔流體。轉換器904可在晶粒310旋轉時被來回掃描以改良音波能量至晶粒310之均勻施加。音波能量有助於疏鬆顆粒，否則其可能難以自晶粒310表面移除。
參考圖9B，接著移除轉換器904，且晶粒310之表面可運用刷子906刷乾淨。舉例而言，刷子906可在轉台902旋轉時被來回掃描。若此清潔程序不能成功移除足夠顆粒，則該程序可視需要重複。當該清潔程序完成時，晶粒310被沖洗好且已乾燥。然而，在一些狀況下，此可能需要多個循環，且仍 可能不足以自晶粒310清潔掉所有殘留物。
參考圖10A及圖10B，技術及系統在單個程序中提供對晶粒/晶圓/基板表面之經改良清潔。圖10A及圖10B說明根據各種具體實例之實例晶粒310清潔系統1000。揭示整合式超高頻音波刷子系統1000，其包括超高頻音波轉換器1002及一或多個刷子頭部1004。
在第一具體實例中，如圖10A處所展示，整合式超高頻音波刷子系統1000置放成接近轉台902(或其他處理表面)上之晶粒310。整合式超高頻音波刷子系統1000定位成使得轉換器1002與晶粒310表面相距最佳距離，且使得刷子1004在晶粒310表面上具有所要接觸壓力。舉例而言，清潔流體經施加至晶粒310表面。當轉換器1002經由清潔流體將音波能量施加至晶粒310表面時，刷子1004同時自晶粒310表面刷掉顆粒。在各種實施中，晶粒310在轉台902上旋轉及/或整合式超高頻音波刷子系統1000被來回掃描以供均勻清潔。
在實施中，例如，流體高度感測器1006在將信號發送至清潔流體儲存器之情況下輔助控制經施加至晶粒310表面之清潔流體的量。在實施中，流體高度感測器1006定位在晶粒310上方且經配置以偵測晶粒310上方之流體之高度。流體高度感測器1006經配置以在流體之高度小於第一預定量時將至少第一信號發送至流體源，且在流體之高度大於第二預定量時將第二信號發送至流體源。單個系統及程序中之超高頻音波及刷洗之組合允許單個程序中之較徹底清潔，從而可去除重複的清潔反覆。
在第二具體實例中，如圖10B處所展示，一或多個刷子1004可在刷洗晶粒310之表面時經由旋轉單元1008旋轉。舉例而言，刷子1004可使用經由導管1010、電纜或其類似者遞送之水力學或任何其他適合手段(氣動、電動、機械等)旋轉(例如，旋轉單元1008可旋轉刷子1004)。刷子1004之額外旋轉可輔助在單個清潔系統及程序中自晶粒310之表面移除頑固顆粒。
該些技術及系統可藉由運用較少程序步驟提供較乾淨結合表面而製備待在堆疊式配置中結合之晶粒310。在處理及清潔之後，晶粒310可被拾取且置放於晶粒收納表面314(另一晶粒、基板等)上以用於結合至收納表面314，如上文所描述。待使用「Zibond®」及「直接結合互連(DBI®)」技術堆疊及結合之晶粒310可尤其受益，該些晶粒可能易受顆粒及污染物影響。所揭示之技術亦可有益於其他應用，其中例如晶粒310之結合區可包括可流動塊狀材料，諸如用於結合之任何形式的可焊材料。最小化或去除結合表面之間的顆粒或污跡可顯著地改良良率及可靠性。額外益處包括清潔程序及清潔設備之經改良效率、較簡化程序步驟及製程設備、清潔循環時間之顯著縮減等等。
其中可採用所揭示技術及系統之清潔循環之實例包括：在CMP程序之後、在蝕刻之後等等清潔晶粒310；自晶粒310清潔掉有機(或無機)製造及處理層；在電漿灰化晶粒310之表面之後用去離子水(DI)、鹼性或酸性溶液或弱鹼性或弱酸性配方、溶劑或其各種組合清潔晶粒310；在電漿活化晶粒310之表面之後重新清潔晶粒310，等等。舉例而言，在各種具體實例中，灰化步驟可省去且晶粒310可在圖10A及圖10B中所描述之設備中加以清潔。在一個具體實例中，例如，保護層304可使用圖10A及圖10B中所描述之設備使用經施加音波能量及刷子1004之機械動作清潔掉，從而運用適合溶劑移除保護層304。為防止工具及裝置之交叉污染，在後續步驟中，經清潔晶粒310可經傳送至參考圖10A及圖10B所描述之類型的另一清潔台以供額外清潔例如從而去除灰化步驟，或在晶粒310之活化之後經傳送至該另一清潔台。
如各種先前段落中所描述，經單一化晶粒310可在載體306上加以處理。在一些具體實例中，已知良好晶粒310自載體306移除，其中載體306之至少部分附接至已知良好晶粒310之第二表面。第一已知良好晶粒310在第一已知良好晶粒310之第一表面處附接至基板314之經製備表面。類似地，第一已 知良好晶粒310之第二表面可經清潔(包括清潔掉載體306之部分)且經製備以用於結合另一已知良好晶粒316。實務上，經結合晶粒310、316中之任一者之背側(例如，第二側)可經製備，且額外晶粒310、316可經結合於其上。任何額外晶粒310、316可視需要結合至先前經結合晶粒310、316。在各種具體實例中，堆疊式經結合晶粒(310、316等)可介於1至200個晶粒310、316的範圍內，且較佳地在1至100個晶粒310、316之間且仍較佳地在1至20個已知良好晶粒310、316之間。
所描述之技術可針對ZiBond®及DBI®製造之裝置等等產生較佳裝置及封裝可靠性、較高效能及經改良利潤邊際。所揭示技術之其他優點對於熟習此項技術者亦將係顯而易見的。
總結
儘管已以特定針對於結構特徵及/或方法行動之語言描述本發明之實施，但應理解，實施不一定限於所描述特定特徵或行動。確切而言，將特定特徵及行動揭示為實施實例裝置及技術之代表性形式。
本文之每項技術方案構成單獨具體實例，且組合不同技術方案之具體實例及/或不同具體實例在本發明之範圍內，且將在查閱本發明之後即刻對於一般熟習此項技術者顯而易見。
200:實例晶粒處理序列/程序

Claims (18)

  1. 一種用於處理半導體晶粒構件的方法，其包含：向包括晶圓的基板施加保護層到所述晶圓的結合表面；將所述晶圓和所述保護層單一化成多個半導體晶粒構件；以及去除所述保護層以暴露所述多個半導體晶粒構件中的一個或更多個半導體晶粒構件的個別結合表面。
  2. 如請求項1所述的方法，其進一步包括：清潔所述多個半導體晶粒構件中的所述一個或更多個半導體晶粒構件的所述個別結合表面。
  3. 如請求項2所述的方法，其中，清潔所述多個半導體晶粒構件中的所述一個或更多個半導體晶粒構件的所述個別結合表面包括機械清潔所述多個半導體晶粒構件中的所述一個或更多個半導體晶粒構件的所述個別結合表面。
  4. 如請求項2所述的方法，其中，清潔所述多個半導體晶粒構件中的所述一個或更多個半導體晶粒構件的所述個別結合表面包括化學清潔所述多個半導體晶粒構件中的所述一個或更多個半導體晶粒構件的所述個別結合表面。
  5. 如請求項2所述的方法，其中，清潔所述多個半導體晶粒構件中的所述一個或更多個半導體晶粒構件的所述個別結合表面包括濕式清潔所述多個半導體晶粒構件中的所述一個或更多個半導體晶粒構件的所述個別結合表面。
  6. 如請求項1所述的方法，其進一步包括：電漿活化所述多個半導體晶粒構件中的所述一個或更多個半導體晶粒構件的所述個別結合表面。
  7. 如請求項1所述的方法，其進一步包括：拉伸耦接至所述基板的載體，以在固定於所述載體的所述多個半導體晶粒構件中的所述一個或更多個半導體晶粒構件之間形成間隙；以及沿著所述間隙中的一或多個間隙對所述載體進行穿孔。
  8. 如請求項7所述的方法，其中，沿著所述間隙中的所述一或多個間隙對所述載體進行穿孔包括使用切割葉片、熱刀或光學刀中的一或多個來沿著所述間隙中的所述一或多個間隙對所述載體進行穿孔。
  9. 如請求項7所述的方法，其進一步包括：清潔所述多個半導體晶粒構件中的所述一個或更多個半導體晶粒構件的一或多個邊緣，同時所述多個半導體晶粒構件中的所述一個或更多個半導體晶粒構件固定到所述載體，所述邊緣暴露在所述間隙中的所述一或多個間隙中。
  10. 如請求項7所述的方法，其中，所述載體包括切割片。
  11. 如請求項1所述的方法，其中，所述保護層是在所述晶圓的第一結合表面上的第一保護層，並且所述基板包括在所述晶圓的第二結合表面上的第二保護層，所述第二結合表面不同於所述第一結合表面，並且所述方法還包括：在將所述晶圓單一化成所述多個半導體晶粒構件之後，去除所述第二保護層。
  12. 一種用於處理半導體晶粒構件的方法，其包含：向包括晶圓的基板施加保護層到所述晶圓的結合表面，所述基板耦接至載體；將所述晶圓和所述保護層單一化成多個半導體晶粒構件；拉伸所述載體，以在固定於所述載體的所述多個半導體晶粒構件中的一個或更多個半導體晶粒構件之間形成間隙；以及 在拉伸所述載體後，去除所述保護層以暴露所述多個半導體晶粒構件中的所述一個或更多個半導體晶粒構件的個別結合表面。
  13. 如請求項12所述的方法，其進一步包括：電漿活化所述多個半導體晶粒構件中的所述一個或更多個半導體晶粒構件的所述個別結合表面。
  14. 如請求項12所述的方法，其進一步包括：沿著所述間隙中的一或多個間隙對所述載體進行穿孔。
  15. 如請求項14所述的方法，其中，沿著所述間隙中的所述一或多個間隙對所述載體進行穿孔包括使用切割葉片、熱刀或光學刀中的一或多個來沿著所述間隙中的所述一或多個間隙對所述載體進行穿孔。
  16. 如請求項14所述的方法，其進一步包括：清潔所述多個半導體晶粒構件中的所述一個或更多個半導體晶粒構件的所述個別結合表面；以及清潔所述多個半導體晶粒構件中的所述一個或更多個半導體晶粒構件的邊緣，其中所述邊緣暴露於所述間隙中。
  17. 如請求項16所述的方法，其中，清潔所述多個半導體晶粒構件中的所述一個或更多個半導體晶粒構件的所述個別結合表面包括以下至少一種：(i)機械清潔所述個別結合表面；(ii)化學清潔所述個別結合表面；以及(iii)濕式清潔所述個別結合表面。
  18. 如請求項12所述的方法，其中，所述保護層是在所述晶圓的第一結合表面上的第一保護層，並且所述基板包括在所述晶圓的第二結合表面上的第二保護層，所述第二結合表面不同於所述第一結合表面，並且所述方法還包括：在將所述晶圓單一化成所述多個半導體晶粒構件之後，去除所述第二保護 層。
TW110142410A 2017-04-21 2018-04-03 用於處理半導體晶粒構件的方法 TWI790817B (zh)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US201762488340P 2017-04-21 2017-04-21
US62/488,340 2017-04-21
US201762563847P 2017-09-27 2017-09-27
US62/563,847 2017-09-27
US15/936,075 US10269756B2 (en) 2017-04-21 2018-03-26 Die processing
US15/936,075 2018-03-26

Publications (2)

Publication Number Publication Date
TW202209590A TW202209590A (zh) 2022-03-01
TWI790817B true TWI790817B (zh) 2023-01-21

Family

ID=63856348

Family Applications (3)

Application Number Title Priority Date Filing Date
TW110142410A TWI790817B (zh) 2017-04-21 2018-04-03 用於處理半導體晶粒構件的方法
TW107111790A TWI748080B (zh) 2017-04-21 2018-04-03 晶粒處理
TW111148903A TW202322304A (zh) 2017-04-21 2018-04-03 用於處理半導體晶粒構件的方法

Family Applications After (2)

Application Number Title Priority Date Filing Date
TW107111790A TWI748080B (zh) 2017-04-21 2018-04-03 晶粒處理
TW111148903A TW202322304A (zh) 2017-04-21 2018-04-03 用於處理半導體晶粒構件的方法

Country Status (7)

Country Link
US (6) US10269756B2 (zh)
EP (1) EP3613073A4 (zh)
JP (1) JP7106575B2 (zh)
KR (1) KR102391159B1 (zh)
CN (2) CN118099028A (zh)
TW (3) TWI790817B (zh)
WO (1) WO2018194827A1 (zh)

Families Citing this family (92)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
US8735219B2 (en) 2012-08-30 2014-05-27 Ziptronix, Inc. Heterogeneous annealing method and device
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US9852988B2 (en) 2015-12-18 2017-12-26 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
US10446532B2 (en) 2016-01-13 2019-10-15 Invensas Bonding Technologies, Inc. Systems and methods for efficient transfer of semiconductor elements
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10446487B2 (en) 2016-09-30 2019-10-15 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10719762B2 (en) 2017-08-03 2020-07-21 Xcelsis Corporation Three dimensional chip structure implementing machine trained network
US10580735B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Stacked IC structure with system level wiring on multiple sides of the IC die
TWI822659B (zh) 2016-10-27 2023-11-21 美商艾德亞半導體科技有限責任公司 用於低溫接合的結構和方法
US10002844B1 (en) 2016-12-21 2018-06-19 Invensas Bonding Technologies, Inc. Bonded structures
US10796936B2 (en) 2016-12-22 2020-10-06 Invensas Bonding Technologies, Inc. Die tray with channels
US20180182665A1 (en) 2016-12-28 2018-06-28 Invensas Bonding Technologies, Inc. Processed Substrate
CN110178212B (zh) 2016-12-28 2024-01-09 艾德亚半导体接合科技有限公司 堆栈基板的处理
KR20230156179A (ko) 2016-12-29 2023-11-13 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 집적된 수동 컴포넌트를 구비한 접합된 구조체
TWI738947B (zh) 2017-02-09 2021-09-11 美商英帆薩斯邦德科技有限公司 接合結構與形成接合結構的方法
WO2018169968A1 (en) 2017-03-16 2018-09-20 Invensas Corporation Direct-bonded led arrays and applications
US10515913B2 (en) 2017-03-17 2019-12-24 Invensas Bonding Technologies, Inc. Multi-metal contact structure
US10508030B2 (en) 2017-03-21 2019-12-17 Invensas Bonding Technologies, Inc. Seal for microelectronic assembly
US10784191B2 (en) 2017-03-31 2020-09-22 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10269756B2 (en) 2017-04-21 2019-04-23 Invensas Bonding Technologies, Inc. Die processing
US10529634B2 (en) 2017-05-11 2020-01-07 Invensas Bonding Technologies, Inc. Probe methodology for ultrafine pitch interconnects
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
US10446441B2 (en) 2017-06-05 2019-10-15 Invensas Corporation Flat metal features for microelectronics applications
US10217720B2 (en) 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11195748B2 (en) 2017-09-27 2021-12-07 Invensas Corporation Interconnect structures and methods for forming same
US11031285B2 (en) 2017-10-06 2021-06-08 Invensas Bonding Technologies, Inc. Diffusion barrier collar for interconnects
US10658313B2 (en) 2017-12-11 2020-05-19 Invensas Bonding Technologies, Inc. Selective recess
US11011503B2 (en) 2017-12-15 2021-05-18 Invensas Bonding Technologies, Inc. Direct-bonded optoelectronic interconnect for high-density integrated photonics
US11380597B2 (en) 2017-12-22 2022-07-05 Invensas Bonding Technologies, Inc. Bonded structures
US10923408B2 (en) 2017-12-22 2021-02-16 Invensas Bonding Technologies, Inc. Cavity packages
US11101260B2 (en) * 2018-02-01 2021-08-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a dummy die of an integrated circuit having an embedded annular structure
US10727219B2 (en) 2018-02-15 2020-07-28 Invensas Bonding Technologies, Inc. Techniques for processing devices
US11169326B2 (en) 2018-02-26 2021-11-09 Invensas Bonding Technologies, Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US11256004B2 (en) 2018-03-20 2022-02-22 Invensas Bonding Technologies, Inc. Direct-bonded lamination for improved image clarity in optical devices
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US11244916B2 (en) 2018-04-11 2022-02-08 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US10790262B2 (en) 2018-04-11 2020-09-29 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US10964664B2 (en) 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer
US11004757B2 (en) 2018-05-14 2021-05-11 Invensas Bonding Technologies, Inc. Bonded structures
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US20190363018A1 (en) * 2018-05-24 2019-11-28 Semiconductor Components Industries, Llc Die cleaning systems and related methods
CN112514059B (zh) 2018-06-12 2024-05-24 隔热半导体粘合技术公司 堆叠微电子部件的层间连接
WO2019241417A1 (en) 2018-06-13 2019-12-19 Invensas Bonding Technologies, Inc. Tsv as pad
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
US10910344B2 (en) 2018-06-22 2021-02-02 Xcelsis Corporation Systems and methods for releveled bump planes for chiplets
US11664357B2 (en) 2018-07-03 2023-05-30 Adeia Semiconductor Bonding Technologies Inc. Techniques for joining dissimilar materials in microelectronics
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US11158606B2 (en) 2018-07-06 2021-10-26 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
US11515291B2 (en) 2018-08-28 2022-11-29 Adeia Semiconductor Inc. Integrated voltage regulator and passive components
US20200075533A1 (en) 2018-08-29 2020-03-05 Invensas Bonding Technologies, Inc. Bond enhancement in microelectronics by trapping contaminants and arresting cracks during direct-bonding processes
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11244920B2 (en) 2018-12-18 2022-02-08 Invensas Bonding Technologies, Inc. Method and structures for low temperature device bonding
WO2020150159A1 (en) 2019-01-14 2020-07-23 Invensas Bonding Technologies, Inc. Bonded structures
US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
US10854578B2 (en) 2019-03-29 2020-12-01 Invensas Corporation Diffused bitline replacement in stacked wafer memory
US11205625B2 (en) 2019-04-12 2021-12-21 Invensas Bonding Technologies, Inc. Wafer-level bonding of obstructive elements
US11373963B2 (en) 2019-04-12 2022-06-28 Invensas Bonding Technologies, Inc. Protective elements for bonded structures
US11610846B2 (en) 2019-04-12 2023-03-21 Adeia Semiconductor Bonding Technologies Inc. Protective elements for bonded structures including an obstructive element
US11355404B2 (en) 2019-04-22 2022-06-07 Invensas Bonding Technologies, Inc. Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
US11385278B2 (en) 2019-05-23 2022-07-12 Invensas Bonding Technologies, Inc. Security circuitry for bonded structures
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
CN110892521B (zh) 2019-10-12 2021-01-29 长江存储科技有限责任公司 用于裸片对裸片进行键合的方法和结构
US11862602B2 (en) 2019-11-07 2024-01-02 Adeia Semiconductor Technologies Llc Scalable architecture for reduced cycles across SOC
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
US11876076B2 (en) 2019-12-20 2024-01-16 Adeia Semiconductor Technologies Llc Apparatus for non-volatile random access memory stacks
WO2021133741A1 (en) 2019-12-23 2021-07-01 Invensas Bonding Technologies, Inc. Electrical redundancy for bonded structures
US11721653B2 (en) 2019-12-23 2023-08-08 Adeia Semiconductor Bonding Technologies Inc. Circuitry for electrical redundancy in bonded structures
US11742314B2 (en) 2020-03-31 2023-08-29 Adeia Semiconductor Bonding Technologies Inc. Reliable hybrid bonded apparatus
US11735523B2 (en) 2020-05-19 2023-08-22 Adeia Semiconductor Bonding Technologies Inc. Laterally unconfined structure
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
JP7289579B2 (ja) * 2020-07-31 2023-06-12 ボンドテック株式会社 チップ接合システムおよびチップ接合方法
US20220059406A1 (en) * 2020-08-21 2022-02-24 Advanced Semiconductor Engineering, Inc. Method for manufacturing semiconductor package
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die
KR20230095110A (ko) * 2020-10-29 2023-06-28 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 직접 접합 방법 및 구조체
WO2022094587A1 (en) * 2020-10-29 2022-05-05 Invensas Bonding Technologies, Inc. Direct bonding methods and structures
KR102567863B1 (ko) * 2021-01-14 2023-08-18 (주)인터체크 스크러버를 이용한 레티클 세정장치
KR20230164716A (ko) * 2021-03-31 2023-12-04 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 직접 결합 방법 및 구조
KR102588869B1 (ko) * 2021-06-16 2023-10-16 정라파엘 다이 본딩 방법
WO2023044308A1 (en) * 2021-09-14 2023-03-23 Adeia Semiconductor Bonding Technologies Inc. Method of bonding thin substrates
WO2023066461A1 (de) * 2021-10-19 2023-04-27 Ev Group E. Thallner Gmbh Verfahren und vorrichtung zum transferieren und bereitstellen von bauteilen
US20230369136A1 (en) * 2022-05-13 2023-11-16 Adeia Semiconductor Bonding Technologies Inc. Bonding surface validation on dicing tape
US20240170443A1 (en) * 2022-11-18 2024-05-23 Applied Materials, Inc. Integrated process flows for hybrid bonding

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201401573A (zh) * 2012-06-29 2014-01-01 Nitto Denko Corp 被覆有螢光體層之ｌｅｄ、其製造方法及ｌｅｄ裝置
WO2016003709A1 (en) * 2014-06-30 2016-01-07 Applied Materials, Inc. Wafer dicing using hybrid laser and plasma etch approach with mask application by vacuum lamination

Family Cites Families (255)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2626408B1 (fr) 1988-01-22 1990-05-11 Thomson Csf Capteur d'image a faible encombrement
JPH07193294A (ja) 1993-11-01 1995-07-28 Matsushita Electric Ind Co Ltd 電子部品およびその製造方法
JPH0831785A (ja) * 1994-07-12 1996-02-02 Sony Corp ウェーハの洗浄方法および装置
KR960009074A (ko) 1994-08-29 1996-03-22 모리시다 요이치 반도체 장치 및 그 제조방법
US6097096A (en) 1997-07-11 2000-08-01 Advanced Micro Devices Metal attachment method and structure for attaching substrates at low temperatures
FR2787241B1 (fr) 1998-12-14 2003-01-31 Ela Medical Sa Composant microelectronique cms enrobe, notamment pour un dispositif medical implantable actif, et son procede de fabrication
KR20010052451A (ko) 1999-03-30 2001-06-25 롤페스 요하네스 게라투스 알베르투스 반도체 웨이퍼 세척 장치 및 방법
JP3532788B2 (ja) 1999-04-13 2004-05-31 唯知 須賀 半導体装置及びその製造方法
JP2000355165A (ja) 1999-06-16 2000-12-26 Fuji Photo Film Co Ltd 感熱記録材料
US6984571B1 (en) 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6500694B1 (en) 2000-03-22 2002-12-31 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
JP3440057B2 (ja) 2000-07-05 2003-08-25 唯知 須賀 半導体装置およびその製造方法
US6423640B1 (en) 2000-08-09 2002-07-23 Taiwan Semiconductor Manufacturing Co., Ltd. Headless CMP process for oxide planarization
TW522531B (en) 2000-10-20 2003-03-01 Matsushita Electric Ind Co Ltd Semiconductor device, method of manufacturing the device and mehtod of mounting the device
JP2002134658A (ja) 2000-10-24 2002-05-10 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP2002353416A (ja) 2001-05-25 2002-12-06 Sony Corp 半導体記憶装置およびその製造方法
US6793759B2 (en) 2001-10-09 2004-09-21 Dow Corning Corporation Method for creating adhesion during fabrication of electronic devices
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US7105980B2 (en) 2002-07-03 2006-09-12 Sawtek, Inc. Saw filter device and method employing normal temperature bonding for producing desirable filter production and performance characteristics
JP4083502B2 (ja) 2002-08-19 2008-04-30 株式会社フジミインコーポレーテッド 研磨方法及びそれに用いられる研磨用組成物
US6822326B2 (en) 2002-09-25 2004-11-23 Ziptronix Wafer bonding hermetic encapsulation
US7023093B2 (en) 2002-10-24 2006-04-04 International Business Machines Corporation Very low effective dielectric constant interconnect Structures and methods for fabricating the same
US6962835B2 (en) 2003-02-07 2005-11-08 Ziptronix, Inc. Method for room temperature metal direct bonding
US6908027B2 (en) 2003-03-31 2005-06-21 Intel Corporation Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
TWI318649B (en) * 2003-06-06 2009-12-21 Hitachi Chemical Co Ltd Sticking sheep, connecting sheet unified with dicing tape,and fabricating method of semiconductor device
GB2404280B (en) 2003-07-03 2006-09-27 Xsil Technology Ltd Die bonding
JP3980539B2 (ja) 2003-08-29 2007-09-26 唯知 須賀 基板接合方法、照射方法、および基板接合装置
US6867073B1 (en) 2003-10-21 2005-03-15 Ziptronix, Inc. Single mask via method and device
US20060057945A1 (en) 2004-09-16 2006-03-16 Chia-Lin Hsu Chemical mechanical polishing process
TWI303864B (en) 2004-10-26 2008-12-01 Sanyo Electric Co Semiconductor device and method for making the same
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
DE102005042074A1 (de) * 2005-08-31 2007-03-08 Forschungsverbund Berlin E.V. Verfahren zur Erzeugung von Durchkontaktierungen in Halbleiterwafern
JP2007081037A (ja) 2005-09-13 2007-03-29 Disco Abrasive Syst Ltd デバイスおよびその製造方法
US20070075417A1 (en) 2005-10-05 2007-04-05 Samsung Electro-Mechanics Co., Ltd. MEMS module package using sealing cap having heat releasing capability and manufacturing method thereof
US7662668B2 (en) * 2005-11-16 2010-02-16 Denso Corporation Method for separating a semiconductor substrate into a plurality of chips along with a cutting line on the semiconductor substrate
US7550366B2 (en) 2005-12-02 2009-06-23 Ayumi Industry Method for bonding substrates and device for bonding substrates
US7193423B1 (en) 2005-12-12 2007-03-20 International Business Machines Corporation Wafer-to-wafer alignments
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
JP4160083B2 (ja) 2006-04-11 2008-10-01 シャープ株式会社 光学装置用モジュール及び光学装置用モジュールの製造方法
US7750488B2 (en) 2006-07-10 2010-07-06 Tezzaron Semiconductor, Inc. Method for bonding wafers to produce stacked integrated circuits
JP2008130603A (ja) 2006-11-16 2008-06-05 Toshiba Corp イメージセンサ用ウェハレベルパッケージ及びその製造方法
JP4840174B2 (ja) 2007-02-08 2011-12-21 パナソニック株式会社 半導体チップの製造方法
US7803693B2 (en) 2007-02-15 2010-09-28 John Trezza Bowed wafer hybridization compensation
US7919410B2 (en) 2007-03-14 2011-04-05 Aptina Imaging Corporation Packaging methods for imager devices
JP2008244080A (ja) * 2007-03-27 2008-10-09 Sharp Corp 半導体素子の製造方法
TWI332790B (en) 2007-06-13 2010-11-01 Ind Tech Res Inst Image sensor module with a three-dimensional dies-stacking structure
KR101413380B1 (ko) 2007-08-28 2014-06-30 쓰리엠 이노베이티브 프로퍼티즈 캄파니 반도체 다이의 제조방법, 상기 방법으로 제조된 반도체다이를 포함하는 반도체 소자
US20090127667A1 (en) 2007-11-21 2009-05-21 Powertech Technology Inc. Semiconductor chip device having through-silicon-via (TSV) and its fabrication method
KR20090061996A (ko) * 2007-12-12 2009-06-17 삼성전자주식회사 칩 뒷면 보호 필름, 그 제조 방법 및 이를 이용한 반도체패키지의 제조 방법
EP2257608A1 (en) 2008-03-07 2010-12-08 3M Innovative Properties Company Dicing tape and die attach adhesive with patterned backing
KR20090106822A (ko) 2008-04-07 2009-10-12 삼성전자주식회사 웨이퍼 본딩 방법 및 그 방법에 의해 본딩된 웨이퍼 구조체
US8349635B1 (en) 2008-05-20 2013-01-08 Silicon Laboratories Inc. Encapsulated MEMS device and method to form the same
FR2931585B1 (fr) 2008-05-26 2010-09-03 Commissariat Energie Atomique Traitement de surface par plasma d'azote dans un procede de collage direct
US20090320875A1 (en) 2008-06-25 2009-12-31 Applied Materials, Inc. Dual chamber megasonic cleaner
US8193632B2 (en) 2008-08-06 2012-06-05 Industrial Technology Research Institute Three-dimensional conducting structure and method of fabricating the same
JP6045772B2 (ja) * 2008-08-27 2016-12-14 日立化成株式会社 感光性接着剤組成物、フィルム状接着剤、接着シート、接着剤パターン、接着剤層付半導体ウェハ、半導体装置、及び半導体装置の製造方法
US9893004B2 (en) 2011-07-27 2018-02-13 Broadpak Corporation Semiconductor interposer integration
US8168458B2 (en) 2008-12-08 2012-05-01 Stats Chippac, Ltd. Semiconductor device and method of forming bond wires and stud bumps in recessed region of peripheral area around the device for electrical interconnection to other devices
US8476165B2 (en) 2009-04-01 2013-07-02 Tokyo Electron Limited Method for thinning a bonding wafer
US8263434B2 (en) 2009-07-31 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP
US8482132B2 (en) 2009-10-08 2013-07-09 International Business Machines Corporation Pad bonding employing a self-aligned plated liner for adhesion enhancement
JP2011104633A (ja) * 2009-11-19 2011-06-02 Stanley Electric Co Ltd スクライブ方法
JP2011128140A (ja) 2009-11-19 2011-06-30 Dainippon Printing Co Ltd センサデバイス及びその製造方法
JP5807221B2 (ja) 2010-06-28 2015-11-10 アユミ工業株式会社 接合構造体製造方法および加熱溶融処理方法ならびにこれらのシステム
JP5517800B2 (ja) 2010-07-09 2014-06-11 キヤノン株式会社 固体撮像装置用の部材および固体撮像装置の製造方法
US8481406B2 (en) 2010-07-15 2013-07-09 Soitec Methods of forming bonded semiconductor structures
FR2963158B1 (fr) 2010-07-21 2013-05-17 Commissariat Energie Atomique Procede d'assemblage par collage direct entre deux elements comprenant des portions de cuivre et de materiaux dielectriques
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
FR2964112B1 (fr) * 2010-08-31 2013-07-19 Commissariat Energie Atomique Traitement avant collage d'une surface mixte cu-oxyde, par un plasma contenant de l'azote et de l'hydrogene
FR2966283B1 (fr) 2010-10-14 2012-11-30 Soi Tec Silicon On Insulator Tech Sa Procede pour realiser une structure de collage
US8377798B2 (en) 2010-11-10 2013-02-19 Taiwan Semiconductor Manufacturing Co., Ltd Method and structure for wafer to wafer bonding in semiconductor packaging
US8620164B2 (en) 2011-01-20 2013-12-31 Intel Corporation Hybrid III-V silicon laser formed by direct bonding
JP5682327B2 (ja) 2011-01-25 2015-03-11 ソニー株式会社 固体撮像素子、固体撮像素子の製造方法、及び電子機器
US20120194719A1 (en) 2011-02-01 2012-08-02 Scott Churchwell Image sensor units with stacked image sensors and image processors
WO2012133760A1 (ja) * 2011-03-30 2012-10-04 ボンドテック株式会社 電子部品実装方法、電子部品実装システムおよび基板
US8716105B2 (en) 2011-03-31 2014-05-06 Soitec Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures and intermediate structures formed using such methods
US8501537B2 (en) 2011-03-31 2013-08-06 Soitec Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures formed using such methods
DE102011018295B4 (de) 2011-04-20 2021-06-24 Austriamicrosystems Ag Verfahren zum Schneiden eines Trägers für elektrische Bauelemente
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
EP2717300B1 (en) 2011-05-24 2020-03-18 Sony Corporation Semiconductor device
US9252172B2 (en) 2011-05-31 2016-02-02 Stats Chippac, Ltd. Semiconductor device and method of forming EWLB semiconductor package with vertical interconnect structure and cavity region
JP5982748B2 (ja) 2011-08-01 2016-08-31 ソニー株式会社 半導体装置、半導体装置の製造方法、および電子機器
US8697493B2 (en) 2011-07-18 2014-04-15 Soitec Bonding surfaces for direct bonding of semiconductor structures
US8552567B2 (en) 2011-07-27 2013-10-08 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
US8728863B2 (en) * 2011-08-09 2014-05-20 Soitec Methods of forming bonded semiconductor structures including interconnect layers having one or more of electrical, optical, and fluidic interconnects therein, and bonded semiconductor structures formed using such methods
US8441131B2 (en) 2011-09-12 2013-05-14 Globalfoundries Inc. Strain-compensating fill patterns for controlling semiconductor chip package interactions
JP5780228B2 (ja) 2011-11-11 2015-09-16 住友ベークライト株式会社 半導体装置の製造方法
FR2987626B1 (fr) 2012-03-05 2015-04-03 Commissariat Energie Atomique Procede de collage direct utilisant une couche poreuse compressible
US20130260510A1 (en) * 2012-04-02 2013-10-03 Infineon Technologies Ag 3-D Integrated Circuits and Methods of Forming Thereof
CN103377911B (zh) 2012-04-16 2016-09-21 中国科学院微电子研究所 提高化学机械平坦化工艺均匀性的方法
KR102138042B1 (ko) * 2012-04-16 2020-07-28 루미리즈 홀딩 비.브이. W-메사 스트리트를 형성하기 위한 방법 및 장치
JP5664592B2 (ja) 2012-04-26 2015-02-04 信越半導体株式会社 貼り合わせウェーハの製造方法
US9142517B2 (en) 2012-06-05 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding mechanisms for semiconductor wafers
US9048283B2 (en) 2012-06-05 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding systems and methods for semiconductor wafers
US8809123B2 (en) 2012-06-05 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Three dimensional integrated circuit structures and hybrid bonding methods for semiconductor wafers
US8969177B2 (en) * 2012-06-29 2015-03-03 Applied Materials, Inc. Laser and plasma etch wafer dicing with a double sided UV-curable adhesive film
US8735219B2 (en) 2012-08-30 2014-05-27 Ziptronix, Inc. Heterogeneous annealing method and device
US9136293B2 (en) 2012-09-07 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for sensor module
TW201423873A (zh) 2012-12-03 2014-06-16 Powertech Technology Inc 包含晶圓級撿晶之覆晶接合方法
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US20140175655A1 (en) 2012-12-22 2014-06-26 Industrial Technology Research Institute Chip bonding structure and manufacturing method thereof
US8946784B2 (en) 2013-02-18 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for image sensor packaging
CN103165479B (zh) * 2013-03-04 2015-10-14 华进半导体封装先导技术研发中心有限公司 多芯片系统级封装结构的制作方法
US9443796B2 (en) 2013-03-15 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Air trench in packages incorporating hybrid bonding
US8802538B1 (en) 2013-03-15 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for hybrid wafer bonding
JP6157911B2 (ja) 2013-04-17 2017-07-05 富士通株式会社 光半導体装置
US9064937B2 (en) 2013-05-30 2015-06-23 International Business Machines Corporation Substrate bonding with diffusion barrier structures
US9929050B2 (en) 2013-07-16 2018-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure
US8860229B1 (en) 2013-07-16 2014-10-14 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bonding with through substrate via (TSV)
US9723716B2 (en) 2013-09-27 2017-08-01 Infineon Technologies Ag Contact pad structure, an electronic component, and a method for manufacturing a contact pad structure
US9257399B2 (en) 2013-10-17 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. 3D integrated circuit and methods of forming the same
JP2015115446A (ja) 2013-12-11 2015-06-22 株式会社東芝 半導体装置の製造方法
US9437572B2 (en) 2013-12-18 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pad structure for hybrid bonding and methods of forming same
US9018079B1 (en) 2014-01-29 2015-04-28 Applied Materials, Inc. Wafer dicing using hybrid laser scribing and plasma etch approach with intermediate reactive post mask-opening clean
US20150255349A1 (en) 2014-03-07 2015-09-10 JAMES Matthew HOLDEN Approaches for cleaning a wafer during hybrid laser scribing and plasma etching wafer dicing processes
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9299736B2 (en) 2014-03-28 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding with uniform pattern density
US9230941B2 (en) 2014-03-28 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding structure for stacked semiconductor devices
US9449837B2 (en) * 2014-05-09 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. 3D chip-on-wafer-on-substrate structure with via last process
WO2015175322A1 (en) * 2014-05-16 2015-11-19 Applied Materials, Inc. Carrier with thermally resistant film frame for supporting wafer during singulation
US9472458B2 (en) 2014-06-04 2016-10-18 Semiconductor Components Industries, Llc Method of reducing residual contamination in singulated semiconductor die
KR102275705B1 (ko) 2014-07-11 2021-07-09 삼성전자주식회사 웨이퍼 대 웨이퍼 접합 구조
JP2016072316A (ja) * 2014-09-29 2016-05-09 日立オートモティブシステムズ株式会社 半導体装置の製造方法
US9536848B2 (en) 2014-10-16 2017-01-03 Globalfoundries Inc. Bond pad structure for low temperature flip chip bonding
JP6367084B2 (ja) 2014-10-30 2018-08-01 株式会社東芝 半導体チップの接合方法及び半導体チップの接合装置
US9394161B2 (en) 2014-11-14 2016-07-19 Taiwan Semiconductor Manufacturing Co., Ltd. MEMS and CMOS integration with low-temperature bonding
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US9899442B2 (en) 2014-12-11 2018-02-20 Invensas Corporation Image sensor device
US9971777B2 (en) 2014-12-18 2018-05-15 International Business Machines Corporation Smart archiving of real-time performance monitoring data
JP6738591B2 (ja) 2015-03-13 2020-08-12 古河電気工業株式会社 半導体ウェハの処理方法、半導体チップおよび表面保護テープ
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US9656852B2 (en) 2015-07-06 2017-05-23 Taiwan Semiconductor Manufacturing Company Ltd. CMOS-MEMS device structure, bonding mesa structure and associated method
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10075657B2 (en) 2015-07-21 2018-09-11 Fermi Research Alliance, Llc Edgeless large area camera system
US9728521B2 (en) 2015-07-23 2017-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bond using a copper alloy for yield improvement
CN106409650B (zh) * 2015-08-03 2019-01-29 沈阳硅基科技有限公司 一种硅片直接键合方法
US9559081B1 (en) 2015-08-21 2017-01-31 Apple Inc. Independent 3D stacking
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
WO2017052652A1 (en) * 2015-09-25 2017-03-30 Intel Corporation Combination of semiconductor die with another die by hybrid bonding
US9496239B1 (en) 2015-12-11 2016-11-15 International Business Machines Corporation Nitride-enriched oxide-to-oxide 3D wafer bonding
US9852988B2 (en) 2015-12-18 2017-12-26 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
US9923011B2 (en) 2016-01-12 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure with stacked semiconductor dies
US10446532B2 (en) 2016-01-13 2019-10-15 Invensas Bonding Technologies, Inc. Systems and methods for efficient transfer of semiconductor elements
US10026716B2 (en) 2016-04-15 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC formation with dies bonded to formed RDLs
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
KR102505856B1 (ko) 2016-06-09 2023-03-03 삼성전자 주식회사 웨이퍼 대 웨이퍼 접합 구조체
US9941241B2 (en) 2016-06-30 2018-04-10 International Business Machines Corporation Method for wafer-wafer bonding
US9892961B1 (en) 2016-08-09 2018-02-13 International Business Machines Corporation Air gap spacer formation for nano-scale semiconductor devices
US10446487B2 (en) 2016-09-30 2019-10-15 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10672663B2 (en) 2016-10-07 2020-06-02 Xcelsis Corporation 3D chip sharing power circuit
US10719762B2 (en) 2017-08-03 2020-07-21 Xcelsis Corporation Three dimensional chip structure implementing machine trained network
US10580735B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Stacked IC structure with system level wiring on multiple sides of the IC die
US10163750B2 (en) 2016-12-05 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure for heat dissipation
US10453832B2 (en) 2016-12-15 2019-10-22 Taiwan Semiconductor Manufacturing Co., Ltd. Seal ring structures and methods of forming same
US10002844B1 (en) 2016-12-21 2018-06-19 Invensas Bonding Technologies, Inc. Bonded structures
CN110178212B (zh) 2016-12-28 2024-01-09 艾德亚半导体接合科技有限公司 堆栈基板的处理
US20180182665A1 (en) 2016-12-28 2018-06-28 Invensas Bonding Technologies, Inc. Processed Substrate
US20180190583A1 (en) 2016-12-29 2018-07-05 Invensas Bonding Technologies, Inc. Bonded structures with integrated passive component
KR20230156179A (ko) 2016-12-29 2023-11-13 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 집적된 수동 컴포넌트를 구비한 접합된 구조체
US10276909B2 (en) 2016-12-30 2019-04-30 Invensas Bonding Technologies, Inc. Structure comprising at least a first element bonded to a carrier having a closed metallic channel waveguide formed therein
US10431614B2 (en) 2017-02-01 2019-10-01 Semiconductor Components Industries, Llc Edge seals for semiconductor packages
TWI738947B (zh) 2017-02-09 2021-09-11 美商英帆薩斯邦德科技有限公司 接合結構與形成接合結構的方法
WO2018169968A1 (en) 2017-03-16 2018-09-20 Invensas Corporation Direct-bonded led arrays and applications
US10515913B2 (en) 2017-03-17 2019-12-24 Invensas Bonding Technologies, Inc. Multi-metal contact structure
US10508030B2 (en) 2017-03-21 2019-12-17 Invensas Bonding Technologies, Inc. Seal for microelectronic assembly
JP6640780B2 (ja) 2017-03-22 2020-02-05 キオクシア株式会社 半導体装置の製造方法および半導体装置
US10784191B2 (en) 2017-03-31 2020-09-22 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10269756B2 (en) 2017-04-21 2019-04-23 Invensas Bonding Technologies, Inc. Die processing
US10580823B2 (en) 2017-05-03 2020-03-03 United Microelectronics Corp. Wafer level packaging method
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
US10446441B2 (en) 2017-06-05 2019-10-15 Invensas Corporation Flat metal features for microelectronics applications
US10217720B2 (en) 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
CN107331759A (zh) 2017-08-21 2017-11-07 厦门华联电子股份有限公司 免有机胶的晶圆级封装方法和led倒装芯片封装体
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11195748B2 (en) 2017-09-27 2021-12-07 Invensas Corporation Interconnect structures and methods for forming same
US11031285B2 (en) 2017-10-06 2021-06-08 Invensas Bonding Technologies, Inc. Diffusion barrier collar for interconnects
US11251157B2 (en) 2017-11-01 2022-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Die stack structure with hybrid bonding structure and method of fabricating the same and package
US10672820B2 (en) 2017-11-23 2020-06-02 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bonded structure
US20190196208A1 (en) 2017-12-11 2019-06-27 North Inc. Wavelength combiner photonic integrated circuit with grating coupling of lasers
US11011503B2 (en) 2017-12-15 2021-05-18 Invensas Bonding Technologies, Inc. Direct-bonded optoelectronic interconnect for high-density integrated photonics
US11380597B2 (en) 2017-12-22 2022-07-05 Invensas Bonding Technologies, Inc. Bonded structures
US10923408B2 (en) 2017-12-22 2021-02-16 Invensas Bonding Technologies, Inc. Cavity packages
US11127738B2 (en) 2018-02-09 2021-09-21 Xcelsis Corporation Back biasing of FD-SOI circuit blocks
JP6900006B2 (ja) 2018-02-14 2021-07-07 東芝デバイス＆ストレージ株式会社 チップ移載部材、チップ移載装置、およびチップ移載方法
US10727219B2 (en) 2018-02-15 2020-07-28 Invensas Bonding Technologies, Inc. Techniques for processing devices
US11169326B2 (en) 2018-02-26 2021-11-09 Invensas Bonding Technologies, Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US11256004B2 (en) 2018-03-20 2022-02-22 Invensas Bonding Technologies, Inc. Direct-bonded lamination for improved image clarity in optical devices
US10991804B2 (en) 2018-03-29 2021-04-27 Xcelsis Corporation Transistor level interconnection methodologies utilizing 3D interconnects
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US10790262B2 (en) 2018-04-11 2020-09-29 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US10964664B2 (en) 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer
US11398258B2 (en) 2018-04-30 2022-07-26 Invensas Llc Multi-die module with low power operation
US10403577B1 (en) 2018-05-03 2019-09-03 Invensas Corporation Dielets on flexible and stretchable packaging for microelectronics
US11004757B2 (en) 2018-05-14 2021-05-11 Invensas Bonding Technologies, Inc. Bonded structures
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
IT201800005778A1 (it) 2018-05-28 2019-11-28 Dispositivo microfluidico per l'espulsione di fluidi, in particolare per la stampa con inchiostri, e relativo procedimento di fabbricazione
US10923413B2 (en) 2018-05-30 2021-02-16 Xcelsis Corporation Hard IP blocks with physically bidirectional passageways
CN112514059B (zh) 2018-06-12 2024-05-24 隔热半导体粘合技术公司 堆叠微电子部件的层间连接
WO2019241417A1 (en) 2018-06-13 2019-12-19 Invensas Bonding Technologies, Inc. Tsv as pad
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
US10910344B2 (en) 2018-06-22 2021-02-02 Xcelsis Corporation Systems and methods for releveled bump planes for chiplets
US10937755B2 (en) 2018-06-29 2021-03-02 Advanced Micro Devices, Inc. Bond pads for low temperature hybrid bonding
US11664357B2 (en) 2018-07-03 2023-05-30 Adeia Semiconductor Bonding Technologies Inc. Techniques for joining dissimilar materials in microelectronics
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US11158606B2 (en) 2018-07-06 2021-10-26 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
US20200035641A1 (en) 2018-07-26 2020-01-30 Invensas Bonding Technologies, Inc. Post cmp processing for hybrid bonding
US11515291B2 (en) 2018-08-28 2022-11-29 Adeia Semiconductor Inc. Integrated voltage regulator and passive components
US20200075533A1 (en) 2018-08-29 2020-03-05 Invensas Bonding Technologies, Inc. Bond enhancement in microelectronics by trapping contaminants and arresting cracks during direct-bonding processes
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11244920B2 (en) 2018-12-18 2022-02-08 Invensas Bonding Technologies, Inc. Method and structures for low temperature device bonding
WO2020150159A1 (en) 2019-01-14 2020-07-23 Invensas Bonding Technologies, Inc. Bonded structures
US11387202B2 (en) 2019-03-01 2022-07-12 Invensas Llc Nanowire bonding interconnect for fine-pitch microelectronics
US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
GB2582388A (en) 2019-03-22 2020-09-23 Cirrus Logic Int Semiconductor Ltd Composite structures
US10854578B2 (en) 2019-03-29 2020-12-01 Invensas Corporation Diffused bitline replacement in stacked wafer memory
US11373963B2 (en) 2019-04-12 2022-06-28 Invensas Bonding Technologies, Inc. Protective elements for bonded structures
US11610846B2 (en) 2019-04-12 2023-03-21 Adeia Semiconductor Bonding Technologies Inc. Protective elements for bonded structures including an obstructive element
US11205625B2 (en) 2019-04-12 2021-12-21 Invensas Bonding Technologies, Inc. Wafer-level bonding of obstructive elements
US11355404B2 (en) 2019-04-22 2022-06-07 Invensas Bonding Technologies, Inc. Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
US11385278B2 (en) 2019-05-23 2022-07-12 Invensas Bonding Technologies, Inc. Security circuitry for bonded structures
US20200395321A1 (en) 2019-06-12 2020-12-17 Invensas Bonding Technologies, Inc. Sealed bonded structures and methods for forming the same
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US20210098412A1 (en) 2019-09-26 2021-04-01 Invensas Bonding Technologies, Inc. Direct gang bonding methods and structures
US20210118864A1 (en) 2019-10-21 2021-04-22 Invensas Corporation Non-Volatile Dynamic Random Access Memory
US11862602B2 (en) 2019-11-07 2024-01-02 Adeia Semiconductor Technologies Llc Scalable architecture for reduced cycles across SOC
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
US11876076B2 (en) 2019-12-20 2024-01-16 Adeia Semiconductor Technologies Llc Apparatus for non-volatile random access memory stacks
US11721653B2 (en) 2019-12-23 2023-08-08 Adeia Semiconductor Bonding Technologies Inc. Circuitry for electrical redundancy in bonded structures
WO2021133741A1 (en) 2019-12-23 2021-07-01 Invensas Bonding Technologies, Inc. Electrical redundancy for bonded structures
US20210242152A1 (en) 2020-02-05 2021-08-05 Invensas Bonding Technologies, Inc. Selective alteration of interconnect pads for direct bonding
US11742314B2 (en) 2020-03-31 2023-08-29 Adeia Semiconductor Bonding Technologies Inc. Reliable hybrid bonded apparatus
US11735523B2 (en) 2020-05-19 2023-08-22 Adeia Semiconductor Bonding Technologies Inc. Laterally unconfined structure
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die
WO2022094587A1 (en) 2020-10-29 2022-05-05 Invensas Bonding Technologies, Inc. Direct bonding methods and structures
KR20230095110A (ko) 2020-10-29 2023-06-28 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 직접 접합 방법 및 구조체
WO2022147430A1 (en) 2020-12-28 2022-07-07 Invensas Bonding Technologies, Inc. Structures with through-substrate vias and methods for forming the same
EP4268273A1 (en) 2020-12-28 2023-11-01 Adeia Semiconductor Bonding Technologies Inc. Structures with through-substrate vias and methods for forming the same
EP4272249A1 (en) 2020-12-30 2023-11-08 Adeia Semiconductor Bonding Technologies Inc. Structure with conductive feature and method of forming same
JP2024504035A (ja) 2020-12-30 2024-01-30 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド 直接接合構造体
EP4302325A1 (en) 2021-03-03 2024-01-10 Adeia Semiconductor Bonding Technologies Inc. Contact structures for direct bonding
KR20230164716A (ko) 2021-03-31 2023-12-04 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 직접 결합 방법 및 구조
JP2024515033A (ja) 2021-03-31 2024-04-04 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド 担体の直接ボンディング及び剥離
CN117296132A (zh) 2021-03-31 2023-12-26 美商艾德亚半导体接合科技有限公司 载体的直接接合和去接合
WO2023278605A1 (en) 2021-06-30 2023-01-05 Invensas Bonding Technologies, Inc. Element with routing structure in bonding layer
CN117859202A (zh) 2021-07-16 2024-04-09 美商艾德亚半导体接合科技有限公司 用于接合结构的光学阻塞保护元件
US20230036441A1 (en) 2021-08-02 2023-02-02 Invensas Bonding Technologies, Inc. Protective semiconductor elements for bonded structures
WO2023034738A1 (en) 2021-09-01 2023-03-09 Adeia Semiconductor Technologies Llc Stacked structure with interposer
US20230067677A1 (en) 2021-09-01 2023-03-02 Invensas Bonding Technologies, Inc. Sequences and equipment for direct bonding

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201401573A (zh) * 2012-06-29 2014-01-01 Nitto Denko Corp 被覆有螢光體層之ｌｅｄ、其製造方法及ｌｅｄ裝置
WO2016003709A1 (en) * 2014-06-30 2016-01-07 Applied Materials, Inc. Wafer dicing using hybrid laser and plasma etch approach with mask application by vacuum lamination
TW201612965A (en) * 2014-06-30 2016-04-01 Applied Materials Inc Wafer dicing using hybrid laser and plasma etch approach with mask application by vacuum lamination

Also Published As

Publication number Publication date
TW202209590A (zh) 2022-03-01
TWI748080B (zh) 2021-12-01
WO2018194827A1 (en) 2018-10-25
CN118099028A (zh) 2024-05-28
US20190189588A1 (en) 2019-06-20
KR102391159B1 (ko) 2022-04-26
EP3613073A1 (en) 2020-02-26
US20180308819A1 (en) 2018-10-25
US20240021572A1 (en) 2024-01-18
US10269756B2 (en) 2019-04-23
US10714449B2 (en) 2020-07-14
US20210233888A1 (en) 2021-07-29
US20190371761A1 (en) 2019-12-05
US20200321307A1 (en) 2020-10-08
US10985133B2 (en) 2021-04-20
JP7106575B2 (ja) 2022-07-26
US10515925B2 (en) 2019-12-24
CN110546754A (zh) 2019-12-06
US11742315B2 (en) 2023-08-29
TW202322304A (zh) 2023-06-01
JP2020518133A (ja) 2020-06-18
TW201842634A (zh) 2018-12-01
KR20190133256A (ko) 2019-12-02
CN110546754B (zh) 2024-01-26
EP3613073A4 (en) 2021-06-02

Similar Documents

Publication Publication Date Title
TWI790817B (zh) 用於處理半導體晶粒構件的方法
TWI778223B (zh) 用於處理裝置的技術
TWI744443B (zh) 堆疊基板的處理
KR20230095110A (ko) 직접 접합 방법 및 구조체
KR20190140967A (ko) 처리된 적층 다이들
US7846776B2 (en) Methods for releasably attaching sacrificial support members to microfeature workpieces and microfeature devices formed using such methods
US20180182654A1 (en) Die tray with channels
JP2000091274A (ja) 半導体チップの形成方法およびそれを用いた半導体装置の製造方法
TWI836575B (zh) 用於處理裝置的技術
JP2017163059A (ja) 電極接合方法