JP2016054282A - 記憶装置、及び半導体装置 - Google Patents
記憶装置、及び半導体装置 Download PDFInfo
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- JP2016054282A JP2016054282A JP2015076806A JP2015076806A JP2016054282A JP 2016054282 A JP2016054282 A JP 2016054282A JP 2015076806 A JP2015076806 A JP 2015076806A JP 2015076806 A JP2015076806 A JP 2015076806A JP 2016054282 A JP2016054282 A JP 2016054282A
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Classifications
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
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- G—PHYSICS
- G11—INFORMATION STORAGE
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
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- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1069—I/O lines read out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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Abstract
【解決手段】第1の配線BLa及び第2の配線BLbと電気的に接続され、なおかつ第1の層に位置するセンスアンプ11と、第1の層上の第2の層に位置する第1の回路12a及び第2の回路12bと、を有する。第1の回路12aは、第3の配線WLaの電位に従って導通状態が制御される第1のスイッチ13と、第1のスイッチ13を介して第1の配線BLaに電気的に接続されている第1の容量素子14と、を有する。第2の回路12bは、第4の配線WLbの電位に従って導通状態が制御される第2のスイッチ13と、第2のスイッチ13を介して第2の配線BLbに電気的に接続されている第2の容量素子14と、を有する。第1の配線BLaは、第2の層において、第3の配線WLaとのみ交差し、第2の配線BLbは、第2の層において、第4の配線WLbとのみ交差する。
【選択図】図1
Description
図1に、本発明の一態様にかかる記憶装置の構成を、一例として示す。図1に示す記憶装置10は、センスアンプ11と、センスアンプ11に電気的に接続されたメモリセル12a及びメモリセル12bとを有する。そして、本発明の一態様では、センスアンプ11が第1の層に位置し、メモリセル12a及びメモリセル12bが、第1の層上の第2の層に位置する。
次いで、本発明の一態様に係る記憶装置10の、具体的な構成の一例について説明する。
図10に、本発明の一態様にかかる記憶装置の断面構造を、一例として示す。なお、図10では、図6に示す記憶装置10が有するトランジスタ13と、容量素子14と、トランジスタ30の断面図を、例示している。そして、図10では、第1の層に、単結晶のシリコン基板にチャネル形成領域を有するトランジスタ30が位置し、第1の層上の第2の層に、容量素子14と、酸化物半導体膜にチャネル形成領域を有するトランジスタ13とが位置する場合の、記憶装置の断面構造を例示している。
次いで、酸化物半導体膜にチャネル形成領域を有するトランジスタ90の構成例について説明する。
図13に、本発明の一態様にかかる記憶装置の断面構造を、一例として示す。なお、図13では、図6に示す記憶装置10が有するトランジスタ13と、容量素子14とトランジスタ30の断面図を、例示している。具体的に、破線A1−A2で示す領域では、トランジスタ13、容量素子14、およびトランジスタ30の、チャネル長方向における構造を示しており、破線A3−A4で示す領域では、トランジスタ13およびトランジスタ30の、チャネル幅方向における構造を示している。ただし、本発明の一態様では、1つのトランジスタのチャネル長方向と、別の一つのトランジスタのチャネル長方向とが、必ずしも一致していなくともよい。
本発明の一態様に係る記憶装置は、表示機器、パーソナルコンピュータ、記録媒体を備えた画像再生装置(代表的にはDVD:Digital Versatile Disc等の記録媒体を再生し、その画像を表示しうるディスプレイを有する装置)に用いることができる。その他に、本発明の一態様に係る記憶装置を用いることができる電子機器として、携帯電話、携帯型を含むゲーム機、携帯情報端末、電子書籍端末、ビデオカメラ、デジタルスチルカメラ等のカメラ、ゴーグル型ディスプレイ(ヘッドマウントディスプレイ)、ナビゲーションシステム、音響再生装置(カーオーディオ、デジタルオーディオプレイヤー等)、複写機、ファクシミリ、プリンタ、プリンタ複合機、現金自動預け入れ払い機(ATM)、自動販売機、医療機器などが挙げられる。これら電子機器の具体例を図14(A)乃至(F)に示す。
本実施例では、本発明の一態様に係るセルアレイについて行った各種評価について説明する。
11 センスアンプ
11−1 センスアンプ
11−2 センスアンプ
11−3 センスアンプ
11−4 センスアンプ
12a メモリセル
12b メモリセル
13 トランジスタ
14 容量素子
15a 領域
15b 領域
20 プリチャージ回路
21 スイッチ回路
22 駆動回路
23 メインアンプ
30 トランジスタ
31 トランジスタ
32 トランジスタ
33 トランジスタ
34 トランジスタ
35 トランジスタ
36 トランジスタ
37 トランジスタ
38 トランジスタ
40 アレイ
41 セルアレイ
42 ローデコーダ
43 駆動回路
44 記憶装置
45 バッファ
46 カラムデコーダ
47 回路
48 ローデコーダ
90 トランジスタ
91 絶縁膜
92a 酸化物半導体膜
92b 酸化物半導体膜
92c 酸化物半導体膜
93 導電膜
94 導電膜
95 絶縁膜
96 導電膜
97 基板
100 テスト回路
101 スイッチ回路
102 セルアレイ
103 ソースフォロワ回路
110 メモリセル
111 トランジスタ
112 容量素子
400 基板
401 素子分離領域
402 不純物領域
403 不純物領域
404 チャネル形成領域
405 絶縁膜
406 ゲート電極
411 絶縁膜
412 導電膜
413 導電膜
416 導電膜
417 導電膜
420 絶縁膜
421 絶縁膜
422 絶縁膜
430 半導体膜
430a 酸化物半導体膜
430b 酸化物半導体膜
430c 酸化物半導体膜
431 ゲート絶縁膜
432 導電膜
433 導電膜
434 ゲート電極
440 導電膜
601 半導体基板
610 素子分離領域
611 絶縁膜
612 絶縁膜
613 絶縁膜
625 導電膜
626 導電膜
634 導電膜
635 導電膜
637 導電膜
644 導電膜
651 導電膜
652 導電膜
653 導電膜
655 導電膜
661 絶縁膜
662 ゲート絶縁膜
663 絶縁膜
701 半導体膜
710 領域
711 領域
721 導電膜
722 導電膜
731 ゲート電極
5001 筐体
5002 筐体
5003 表示部
5004 表示部
5005 マイクロホン
5006 スピーカー
5007 操作キー
5008 スタイラス
5301 筐体
5302 筐体
5303 鏡
5304 接続部
5401 筐体
5402 表示部
5403 キーボード
5404 ポインティングデバイス
5601 筐体
5602 筐体
5603 表示部
5604 表示部
5605 接続部
5606 操作キー
5701 筐体
5702 表示部
5901 筐体
5902 表示部
5903 カメラ
5904 スピーカー
5905 ボタン
5906 外部接続部
5907 マイク
Claims (4)
- 第1の配線及び第2の配線と電気的に接続され、なおかつ第1の層に位置するセンスアンプと、前記第1の層上の第2の層に位置する第1の回路及び第2の回路と、を有し、
前記第1の回路は、第3の配線の電位に従って導通状態が制御される第1のスイッチと、前記第1のスイッチを介して前記第1の配線に電気的に接続されている第1の容量素子と、を有し、
前記第2の回路は、第4の配線の電位に従って導通状態が制御される第2のスイッチと、前記第2のスイッチを介して前記第2の配線に電気的に接続されている第2の容量素子と、を有し、
前記第1の配線は、前記第2の層において、前記第3の配線及び前記第4の配線のうち前記第3の配線とのみ交差し、
前記第2の配線は、前記第2の層において、前記第3の配線及び前記第4の配線のうち前記第4の配線とのみ交差する記憶装置。 - 請求項1において、
前記第1のスイッチまたは前記第2のスイッチはトランジスタを有し、
前記トランジスタは、酸化物半導体膜を有し、酸化物半導体膜はチャネル形成領域を有する記憶装置。 - 請求項2において、
前記酸化物半導体膜は、In、Ga、及びZnを含む記憶装置。 - 請求項1乃至請求項3のいずれか1項に記載の記憶装置と、論理回路とを有する半導体装置。
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2015
- 2015-03-31 TW TW104110454A patent/TWI695375B/zh not_active IP Right Cessation
- 2015-03-31 TW TW110123846A patent/TWI767772B/zh active
- 2015-03-31 TW TW109113198A patent/TWI735206B/zh active
- 2015-04-01 WO PCT/IB2015/052387 patent/WO2015155635A1/en active Application Filing
- 2015-04-01 KR KR1020167031080A patent/KR102351193B1/ko active IP Right Grant
- 2015-04-03 JP JP2015076806A patent/JP6661280B2/ja active Active
- 2015-04-06 US US14/679,111 patent/US9478276B2/en active Active
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WO2016181256A1 (ja) * | 2015-05-12 | 2016-11-17 | 株式会社半導体エネルギー研究所 | 半導体装置、電子部品および電子機器 |
JP2017224377A (ja) * | 2016-06-10 | 2017-12-21 | 株式会社半導体エネルギー研究所 | メモリ装置、およびそれを有する半導体装置 |
US10210915B2 (en) | 2016-06-10 | 2019-02-19 | Semiconductor Energy Laboratory Co., Ltd. | Memory device and semiconductor device including the same |
US11270997B2 (en) | 2017-11-30 | 2022-03-08 | Semiconductor Energy Laboratory Co., Ltd. | Memory device |
WO2019162802A1 (ja) * | 2018-02-23 | 2019-08-29 | 株式会社半導体エネルギー研究所 | 記憶装置およびその動作方法 |
JPWO2019162802A1 (ja) * | 2018-02-23 | 2021-02-25 | 株式会社半導体エネルギー研究所 | 記憶装置およびその動作方法 |
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WO2020217138A3 (ja) * | 2019-04-26 | 2021-02-18 | 株式会社半導体エネルギー研究所 | 半導体装置、及び半導体装置の動作方法 |
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JP2023109895A (ja) | 2023-08-08 |
US9865325B2 (en) | 2018-01-09 |
TW202141490A (zh) | 2021-11-01 |
WO2015155635A1 (en) | 2015-10-15 |
TWI695375B (zh) | 2020-06-01 |
JP2020098932A (ja) | 2020-06-25 |
US20170040048A1 (en) | 2017-02-09 |
TW202032553A (zh) | 2020-09-01 |
US20150294710A1 (en) | 2015-10-15 |
TWI767772B (zh) | 2022-06-11 |
JP6661280B2 (ja) | 2020-03-11 |
TW201541454A (zh) | 2015-11-01 |
TWI735206B (zh) | 2021-08-01 |
JP2021192437A (ja) | 2021-12-16 |
US9478276B2 (en) | 2016-10-25 |
KR20160145069A (ko) | 2016-12-19 |
KR102351193B1 (ko) | 2022-01-17 |
JP6952145B2 (ja) | 2021-10-20 |
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