JP2013222966A - 密封膜を含むパッケージオンパッケージ電子装置及びその製造方法 - Google Patents
密封膜を含むパッケージオンパッケージ電子装置及びその製造方法 Download PDFInfo
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- JP2013222966A JP2013222966A JP2013081768A JP2013081768A JP2013222966A JP 2013222966 A JP2013222966 A JP 2013222966A JP 2013081768 A JP2013081768 A JP 2013081768A JP 2013081768 A JP2013081768 A JP 2013081768A JP 2013222966 A JP2013222966 A JP 2013222966A
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Classifications
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Abstract
【解決手段】本発明によるパッケージオンパッケージ装置では上部半導体パッケージと下部半導体パッケージとの間に密封膜が存在して上部半導体パッケージと下部半導体パッケージとの間の接触面積が増加して歪みの程度を緩和させ得る。この方法では下部ソルダバンプ及び上部ソルダバンプの中で少なくとも1つをフラックス機能がある密封膜樹脂溶液で塗布し、加熱することによって、簡単であり、速く連結ソルダバンプと密封膜を形成できる。
【選択図】図1A
Description
3、7、34、36:パッド
11、13、26:下部ソルダバンプ
20:下部半導体チップ
22:下部モールド膜
23:上部面
24:連結ホール
30:上部ソルダバンプ
32:上部パッケージ基板
33:連結ソルダバンプ
38、40、52:上部半導体チップ
42:上部モールド膜
50:下部半導体パッケージ
54:貫通ビア
56:内部ソルダバンプ
60、70:上部半導体パッケージ
85、95:密封膜
85a:密封膜樹脂溶液
87:アンダーフィル樹脂膜
90:容器
100〜106:パッケージオンパッケージ装置
Claims (36)
- 第1及び第2パッケージ基板と、
前記第1及び第2パッケージ基板の間を電気的及び機械的に連結させるソルダ連結と、
前記第1及び第2パッケージ基板の間の第1及び第2密封膜と、を含むパッケージオンパッケージ電子装置。 - 前記第1及び第2密封膜の各々は第1及び第2エポキシ密封膜を含む請求項1に記載のパッケージオンパッケージ電子装置。
- 前記第2エポキシ密封膜はソルダフラックス剤を含み、前記第1エポキシ密封膜は前記第2エポキシ密封膜より低い濃度の前記ソルダフラックス剤を有する請求項2に記載のパッケージオンパッケージ電子装置。
- 前記第1密封膜は前記第1パッケージ基板を貫通するビアを含む前記第1パッケージ基板の上でモールド膜を含み、前記ソルダ連結は前記ビアを通じて延長され、前記第2密封膜の一部は前記モールド膜と前記ソルダ連結との間で前記ビア内にある請求項1から3の何れか一項に記載のパッケージオンパッケージ電子装置。
- 前記第2密封膜の一部は前記モールド膜と前記第2パッケージ基板との間にある請求項4に記載のパッケージオンパッケージ電子装置。
- 前記モールド膜と前記第2密封膜との間で境界が定義される請求項4に記載のパッケージオンパッケージ電子装置。
- 前記モールド膜を通じた前記ビアの側壁は前記第1パッケージ基板から離隔された前記モールド膜の表面の表面粗さより大きい表面粗さを有する請求項4に記載のパッケージオンパッケージ電子装置。
- 前記第1及び第2密封膜は前記第1及び第2パッケージ基板との間で離隔された請求項1に記載のパッケージオンパッケージ電子装置。
- 前記第1パッケージ基板に電気的及び機械的に連結された半導体集積回路装置をさらに含み、前記半導体集積回路装置は前記第1及び第2パッケージ基板の間にあり、前記半導体集積回路装置は前記ソルダ連結から離隔された請求項1に記載のパッケージオンパッケージ電子装置。
- 前記半導体集積回路装置と前記第1パッケージ基板との間の複数個のソルダバンプをさらに含み、前記複数個のソルダバンプは前記半導体集積回路装置と前記第1パッケージ基板との間を電気的及び機械的に連結させる請求項9に記載のパッケージオンパッケージ電子装置。
- 前記半導体集積回路装置は第1半導体集積回路装置を含み、
前記パッケージオンパッケージ電子装置は前記第2パッケージ基板に電気的及び機械的に連結された第2半導体集積回路装置をさらに含み、前記第2パッケージ基板は前記第2半導体集積回路装置と前記第1パッケージ基板との間にある請求項9に記載のパッケージオンパッケージ電子装置。 - 前記第2半導体集積回路装置と前記第2パッケージ基板との間の複数個のソルダバンプをさらに含み、前記複数個のソルダバンプは前記第2半導体集積回路装置と前記第2パッケージ基板とを電気的及び機械的に連結させる請求項11に記載のパッケージオンパッケージ装置。
- 前記第2半導体集積回路装置と前記第2パッケージ基板とを電気的に連結させる複数個のワイヤボンドをさらに含む請求項11に記載のパッケージオンパッケージ装置。
- 前記第2パッケージ基板に電気的に連結された第3半導体集積回路装置をさらに含み、前記第3半導体集積回路装置は前記第2半導体集積回路装置上にあり、前記第2半導体集積回路装置が前記第3半導体集積回路装置と前記第2パッケージ基板との間にある請求項11に記載のパッケージオンパッケージ装置。
- 前記第1パッケージ基板は第1及び第2表面を含み、前記第1表面は前記第2表面と前記第2パッケージ基板との間にあり、
前記パッケージオンパッケージ電子装置は、前記第1パッケージ基板の前記第2表面上の複数個のソルダバンプをさらに含み、前記第1パッケージ基板を通じる電気的連結は前記ソルダ連結と少なくとも1つの前記複数個のソルダバンプとの間で提供される請求項1に記載のパッケージオンパッケージ電子装置。 - 第1パッケージ基板と、
前記第1パッケージ基板と電気的及び機械的に連結された半導体集積回路装置と、
前記第1パッケージ基板上に配置され、前記第1パッケージ基板との間に前記半導体集積回路装置を置く第2パッケージ基板と、
前記第1及び第2パッケージ基板を電気的及び機械的に連結させ、前記半導体集積回路装置と離隔されたソルダ連結と、
前記第1及び第2パッケージ基板の間で前記ソルダ連結上の密封膜を含むパッケージオンパッケージ電子装置。 - 前記密封膜は前記半導体集積回路装置と離隔された請求項16に記載のパッケージオンパッケージ電子装置。
- 前記ソルダ連結は第1ソルダ連結を含み、
前記パッケージオンパッケージ電子装置は、前記第1及び第2パッケージ基板の間を電気的及び機械的に連結させる第2ソルダ連結をさらに含み、前記第2ソルダ連結は前記第1ソルダ連結と前記半導体集積回路装置から離隔される請求項16又は17に記載のパッケージオンパッケージ電子装置。 - 前記密封膜は第1密封膜を含み、
前記パッケージオンパッケージ電子装置は、前記第1及び第2パッケージ基板の間で前記第2ソルダ連結上の第2密封膜をさらに含み、前記第1及び第2密封膜は前記第1及び第2ソルダ連結構造から離隔された請求項18に記載のパッケージオンパッケージ電子装置。 - 前記密封膜は前記第1及び第2パッケージ基板の間で前記第1及び第2ソルダ連結構造上の連続的な密封膜を含む請求項18に記載のパッケージオンパッケージ電子装置。
- 前記密封膜は前記第1及び第2パッケージ基板の間で前記半導体集積回路装置上で、そして前記ソルダ連結上で連続的な密封膜を含む請求項16に記載のパッケージオンパッケージ電子装置。
- 前記半導体集積回路装置と前記第1パッケージ基板との間を電気的及び機械的に連結する複数のソルダバンプと、
前記半導体集積回路装置と前記第1パッケージ基板との間の前記複数個のソルダバンプ上のアンダーフィル物質をさらに含む請求項16に記載のパッケージオンパッケージ電子装置。 - 前記アンダーフィル物質と前記密封膜は互いに離隔された請求項22に記載のパッケージオンパッケージ電子装置。
- 前記密封膜はエポキシとソルダフラックス剤とを含む請求項16に記載のパッケージオンパッケージ電子装置。
- 前記第1及び第2パッケージ基板の間でモールド膜をさらに含み、
前記モールド膜はこれを貫通するビアを含み、前記ソルダ連結は前記第1及び第2パッケージ基板の間で前記ビアを貫通して延長され、前記密封膜の一部は前記モールド膜と前記ソルダ連結との間で前記ビア内にある請求項16に記載のパッケージオンパッケージ電子装置。 - 前記密封膜の一部は前記モールド膜と前記第2パッケージ基板との間にある請求項25に記載のパッケージオンパッケージ電子装置。
- 前記第2パッケージ基板に隣接する前記半導体集積回路装置の表面には前記モールド膜が無い請求項25に記載のパッケージオンパッケージ電子装置。
- 前記モールド膜の一部は前記半導体集積回路装置と前記第2パッケージ基板との間へ延長される請求項25に記載のパッケージオンパッケージ電子装置。
- 前記モールド膜を通じた前記ビアの側壁は前記第1パッケージ基板と離隔された前記モールド膜の表面の表面粗さより大きい表面粗さを有する請求項25に記載のパッケージオンパッケージ電子装置。
- 前記半導体集積回路装置は第1半導体集積回路装置を含み、
前記パッケージオンパッケージ電子装置は、前記第2パッケージ基板と電気的及び機械的に連結された第2半導体集積回路装置をさらに含み、前記第2パッケージ基板は前記第2半導体集積回路装置と前記第1パッケージ基板との間にある請求項16に記載のパッケージオンパッケージ電子装置。 - 第1半導体集積回路装置に電気的及び機械的に連結された第1パッケージ基板を提供する段階と、
第2半導体集積回路装置に電気的及び機械的に連結された第2パッケージ基板を提供する段階と、
前記第1半導体集積回路装置を前記第1及び第2パッケージ基板の間に位置するようにした状態で前記第1及び第2パッケージ基板の間にソルダ連結を提供し、前記第1半導体集積回路装置を前記ソルダ連結と離隔されるようにする段階と、
前記ソルダ連結上に密封膜を提供する段階と、を含むパッケージオンパッケージ電子装置の製造方法。 - 前記ソルダ連結を提供する段階は、前記第1パッケージ基板及び前記第2パッケージ基板の中で少なくとも1つの上に連結ソルダ構造を提供する段階と、前記連結ソルダ構造を加熱して前記第1及び第2パッケージ基板の間に前記ソルダ連結を提供する段階と、を含む請求項31に記載のパッケージオンパッケージ電子装置の製造方法。
- 前記密封膜を提供する段階は、前記連結ソルダ構造を加熱する前に前記連結ソルダ構造上に液体密封物質を提供する段階と、前記液体密封物質を加熱して前記密封膜を形成する段階と、を含む請求項32に記載のパッケージオンパッケージ電子装置の製造方法。
- 前記液体密封物質は液体エポキシ密封物質とソルダフラックス剤を含む請求項33に記載のパッケージオンパッケージ電子装置の製造方法。
- 内部を貫通するビアを含む密封膜を第1パッケージ基板上に提供する段階と、
前記第1パッケージ基板と第2パッケージ基板との間にソルダ連結を提供し、前記ソルダ連結は前記ビアの中へ延長されて前記第1及び第2パッケージ基板の間を電気的及び機械的に連結させる段階と、
モールド膜と前記第2パッケージ基板との間及び/又は前記モールド膜と前記複数のソルダ連結との間で前記ビア内に密封膜を提供する段階を含むパッケージオンパッケージ電子装置の製造方法。 - 前記モールド膜を貫通する前記ビアの側壁は前記第1パッケージ基板から離隔された前記モールド膜の表面の表面粗さより大きい表面粗さを有する請求項35に記載のパッケージオンパッケージ電子装置の製造方法。
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US (2) | US8779606B2 (ja) |
JP (1) | JP6173753B2 (ja) |
KR (1) | KR101867955B1 (ja) |
TW (1) | TWI611524B (ja) |
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KR20130116100A (ko) | 2013-10-23 |
US20130270685A1 (en) | 2013-10-17 |
TWI611524B (zh) | 2018-01-11 |
KR101867955B1 (ko) | 2018-06-15 |
US8779606B2 (en) | 2014-07-15 |
US9245867B2 (en) | 2016-01-26 |
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