TWI611524B - 包含密封層之堆疊封裝電子元件及其相關製造方法 - Google Patents

包含密封層之堆疊封裝電子元件及其相關製造方法 Download PDF

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TWI611524B
TWI611524B TW102112261A TW102112261A TWI611524B TW I611524 B TWI611524 B TW I611524B TW 102112261 A TW102112261 A TW 102112261A TW 102112261 A TW102112261 A TW 102112261A TW I611524 B TWI611524 B TW I611524B
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package substrate
package
sealing layer
electronic component
integrated circuit
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TW102112261A
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TW201351578A (zh
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任忠彬
柳慧楨
朴泰成
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三星電子股份有限公司
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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Abstract

堆疊封裝電子元件可包括第一封裝基板與第二封裝基板、提供所述第一封裝基板與所述第二封裝基板之間的電性與機械耦接的焊料接點、以及在第一封裝基板與第二封裝基板之間的第一密封層與第二密封層。第一密封層與第二密封層分別為第一環氧樹脂密封層與第二環氧樹脂密封層。進而，第二環氧樹脂密封層可包括助焊劑，且相較於第二環氧樹脂密封層，第一環氧樹脂密封層具有較低濃度的助焊劑。

Description

包含密封層之堆疊封裝電子元件及其相關製造方法 【對相關申請案之交叉參考】
此申請案主張2012年4月13日申請的韓國專利申請案第10-2012-0038268號的優先權，其揭露內容在此併入本文作為參考。
本發明是有關於一種堆疊封裝元件及其製造方法。
在持續發展的電子業中，已越來越需要高性能、高速、且小型的電子組件。對應此些趨勢已提出各種半導體安裝技術，例如可將多個半導體晶片安裝在一封裝基板上或可堆疊封裝。例如，堆疊封裝(package-on-package，POP)元件可包括多個堆疊封裝，每個堆疊封裝包括半導體積體電路元件與封裝基板。因此，POP元件的總厚度會增加。為了減小POP元件的總厚度，薄的半導體晶片可用於每個堆疊封裝，然而薄的半導體晶片及/或堆疊封裝會翹曲。
本發明概念的實施例可提供減緩翹曲現象的堆疊封裝元件。
本發明概念的實施例亦可提供快速又簡便地製造減緩翹曲現象的堆疊封裝元件的方法。
根據本發明概念的一些實施例，堆疊封裝元件可包括：具有下部封裝基板與安裝在下部封裝基板上的下部半導體晶片的下部半導體封裝；具有設置在下部半導體封裝上的上部封裝基板與安裝在上部封裝基板上的上部半導體封裝的上部半導體封裝；將下部封裝基板連接至上部封裝基板的連接的焊料凸塊；接觸下部半導體封裝及上部半導體封裝的密封層，密封層覆蓋連接的焊料凸塊的側壁。密封層可包括環氧樹脂且具有助焊功能。
在一些實施例中，下部半導體封裝可更包括覆蓋下部封裝基板的上表面與下部半導體晶片的側壁的下模層。下模層可包括設置有連接的焊料凸塊的連接孔。連接孔的側壁可與連接的焊料凸塊的側壁隔開。密封層可填充連接孔。連接孔的側壁的表面粗糙度大於與下部封裝基板隔開的下模層的上表面的表面粗糙度。
分層區可存在於下模層的上表面與密封層之間。
在其他實施例中，密封層可延伸而填充下部半導體封裝與上部半導體封裝之間的間隙。
在其他實施例中，密封層可包括與連接的焊料凸塊的側壁接觸的第一密封層及填充下部半導體晶片與上部封裝基板之間的間隙的第二密封層。此時，第二密封層可不具備助焊功能。
在其他實施例中，利用覆晶接合方法下部半導體晶片可安裝在下部封裝基板上。
在其他實施例中，上部半導體晶片可不同於下部半導體晶片。
根據本發明概念的一些其他觀點，堆疊封裝元件的製造方法可包括：製造具有下部封裝基板的下部半導體封裝、設置在下部封裝基板上的下部半導體晶片、以及在下部封裝基板上且與下部半導體晶片隔開的下部焊料凸塊；以及製造具有上部封裝基板的上部半導體封裝、設置在上部封裝基板上的上部半導體晶片、以及在上部封裝基板的底面上的上部焊料凸塊。至少一個的下部焊料凸塊與上部焊料凸塊可塗覆有密封層樹脂溶液。可將下部焊料凸塊與上部焊料凸塊熔化並接合以形成連接的焊料凸塊，與密封層。密封層可覆蓋連接的焊料凸塊的側壁，且密封層可接觸上部半導體封裝與下部半導體封裝。
在一些實施例中，下部半導體封裝可更包括覆蓋下部封裝基板的上表面與下部半導體晶片的側壁的下模層，且連接孔可暴露出下部焊料凸塊。此時，形成連接的焊料凸塊與密封層可包括：分散密封層樹脂溶液於連接孔中；將上部半導體封裝設置於 下部半導體封裝上以將上部焊料凸塊設置於連接孔中；以及加熱上部焊料凸塊與下部焊料凸塊。
在其他實施例中，以密封層樹脂溶液塗覆下部焊料凸塊與上部焊料凸塊的至少一者可包括將上部焊料凸塊浸漬於密封層樹脂溶液、及/或在下部焊料凸塊上供應密封層樹脂溶液。
在其他實施例中，密封層樹脂溶液可包括環氧樹脂並具有助焊功能。
根據本發明概念的其他觀點，堆疊封裝元件可包括第一封裝基板與第二封裝基板。焊料接點可提供第一封裝基板與第二封裝基板之間的電性與機械耦接，且可在第一封裝基板與第二封裝基板之間供應第一密封層與第二密封層。
根據本發明概念的一些其他觀點，堆疊封裝元件可包括第一封裝基板與在第一封裝基板上的第二封裝基板。半導體積體電路(IC)元件可電性與機械耦接至第一封裝基板，且半導體積體電路元件可在第一封裝基板與第二封裝基板之間。焊料接點可提供第一封裝基板與第二封裝基板之間的電性與機械耦接，焊料接點與半導體積體電路元件隔開，且在第一封裝基板與第二封裝基板之間的焊料接點上可供應密封層。
根據本發明概念的其他實施例，堆疊封裝元件的形成方法可包括供應第一封裝基板，所述第一封裝基板具有與其電性與機械耦接的第一半導體積體電路元件；並供應第二封裝基板，所述第二封裝基板具有與其電性與機械耦接的第二半導體積體電路 元件。在第一封裝基板與第二封裝基板之間供應焊料接點，在第一封裝基板與第二封裝基板之間具有與焊料接點隔開的第一半導體積體電路元件。此外，在焊料接點上供應密封層。
根據本發明概念的其他觀點，堆疊封裝元件的形成方法可包括提供在第一封裝基板上的的模層，其中所述模層具有穿透所述模層的連接孔。在第一封裝基板與第二封裝基板之間可供應焊料接點，其中焊料接點延伸通過連接孔以提供第一封裝基板與第二封裝基板之間的電性與機械耦接。在模層與第二封裝基板之間、及/或在模層與焊料接點之間的連接孔中可供應密封層。
1‧‧‧下部封裝基板
3‧‧‧第一下墊片
7‧‧‧第二下墊片
11‧‧‧第一下部焊料凸塊
13‧‧‧第三下部焊料凸塊
20‧‧‧下部半導體晶片
22‧‧‧下模層
23‧‧‧上表面
24‧‧‧連接孔
26‧‧‧第二焊料凸塊
30‧‧‧上部焊料凸塊
32‧‧‧上部封裝基板
33‧‧‧連接的焊料凸塊
34‧‧‧第一上墊片
36‧‧‧第二上墊片
38、40、52‧‧‧上部半導體晶片
42‧‧‧上模層
50‧‧‧下部半導體封裝
54‧‧‧貫孔
56‧‧‧上部內焊料凸塊
60、70‧‧‧上部半導體封裝
85‧‧‧密封層
85a‧‧‧密封層樹脂溶液
87‧‧‧底膠樹脂層
90‧‧‧容器
95‧‧‧第二密封層
100、101a、101b、102、103、104、105、106‧‧‧堆疊封裝元件
1000、1100‧‧‧電子元件
1110‧‧‧主體
1120‧‧‧微處理單元
1130‧‧‧電源單元
1140‧‧‧作用單元
1150‧‧‧顯示控制單元
1160‧‧‧顯示單元
1170‧‧‧外部裝置
1180‧‧‧通訊單元
1300‧‧‧電子系統
1310‧‧‧控制器
1320‧‧‧輸入/輸出元件
1330‧‧‧記憶元件
1340‧‧‧介面
1350‧‧‧匯流排
A‧‧‧A部分
DX‧‧‧分層區
鑒於隨附圖式及之後詳細的描述將對本發明更清楚。
圖1A為根據本發明概念的實施例的堆疊封裝元件的平面圖。
圖1B為沿著圖1A的I-I’截面線所裁切的截面圖。
圖1C與圖1D為圖1B的A部分的放大圖。
圖2與圖3為繪示根據本發明概念的實施例的圖1A與圖1B的POP元件的製造方法的截面圖。
圖4與圖5為繪示根據本發明概念的其他實施例的圖1A與圖1B的POP元件的製造方法的截面圖。
圖6為繪示根據本發明概念的再另外的實施例的圖1A與圖1B的POP元件的製造方法的截面圖。
圖7A、圖7B、及圖7C為繪示根據本發明概念的其他實施例的POP元件的截面圖。
圖8為繪示根據本發明概念的實施例的圖7A的POP元件的製造方法的截面圖。
圖9為繪示根據本發明概念的其他實施例的圖7A的POP元件的製造方法的截面圖。
圖10至圖13為繪示根據本發明概念的其他實施例的POP元件的截面圖。
圖14A為根據本發明概念的其他實施例的POP元件的平面圖。
圖14B為沿著圖14A的I-I’截面線所裁切的截面圖。
圖15為繪示包括根據本發明概念的實施例的至少一種半導體封裝的電子元件的透視圖。
圖16為繪示根據本發明概念的實施例的包括至少一種半導體封裝的電子元件的系統方塊圖。
圖17為繪示根據本發明概念的實施例包括至少一個半導體封裝的電子系統的示範的方塊圖。
現將參考繪示本發明概念的示範實施例的以下隨附圖式更完整地描述本發明概念。由於參考附圖而更詳細描述的以下示範實施例，本發明概念的優點與特徵以及達成其的方法將更清楚。然而，本發明概念可按照不同形式體現且不應侷限於以下示範實施例。因此，僅提供這些示範實施例以揭示本發明概念，並使所屬技術領域中具通常知識者了解本發明概念之範疇。在圖式 中，本發明概念的實施例不侷限於本文所提的具體實例，且為清楚起見可誇示。
本文所使用的術語僅是為了描述特定的實施例且並非傾向於限制本發明。除非上下文中另外清楚地說明，作為本文中所使用的單數詞彙的「一(a/an)」及「該(the)」傾向於亦包括多數形。本文中所使用的「及/或(and/or)」包括一個以上的相關列出項目的任一及全部的組合。應當理解的是，當提到元件為「連接」或「耦接」於另一元件時，其可以為直接連接或直接耦接於其他的元件，或可存在介入其中的元件。
相似地，應當理解的是，當提及例如膜層、區域或基板的元件是「在」另一元件「上」，其可以直接在其他元件上或可存在介入其中的元件。相較而言，詞彙「直接地(directly)」意指不具有介入其中的元件。更應當理解的是，當本文中使用詞彙「包括(comprise/comprising/include/including)」時，則指存在特定的特徵、整體、步驟、操作、元件及/或組件，但不排除一個以上之其他特徵、整體、步驟、操作、元件、組件及/或其族群的存在或添加。
此外，將以作為本發明概念的理想示範視圖的截面圖來描述詳細敘述中的實施例。因此，可根據製造技術及/或可容許的誤差改良示範視圖的形狀。因此，本發明概念的實施例並不受限於示範視圖中所繪示的特定形成，但是本發明概念的實施例可包括因製造製程而產生的其他形狀。例示於圖式中的區域具有通常 特性，且是用來繪示元件的特定形狀。因此，此不應當被視為限制本發明概念的範疇。
應當理解的是，雖然本文中可能使用詞彙第一、第二、第三等以描述多種元件，這些元件不應被這些詞彙所限制。這些詞彙僅使用於區別一個元件及另一個元件。因此，若不違背本發明的教示，一些實施例中的第一元件可以在其他實施例中稱為第二元件。本文中所解釋及繪示的本發明概念的示範實施例的態樣包括其互補的對應體。通篇說明書中，相同的參考元件符號或相同的參考代號是指相同的元件。
再者，本文參照理想化的示範繪圖的橫截面繪圖及/或平面繪圖描述示範實施例。因此，可以預期由於例如製造技術及/或公差的緣故，與繪圖的形狀有所不同。因此，不應將示範實施例視為限於本文所繪示區域的形狀，但示範實施例將包括例如製造時產生的形狀誤差。舉例而言，繪示為矩形的蝕刻區域將典型地具有圓形或弧形的特徵。因此，圖式中所繪示的區域為例示其自然特性，而非傾向於繪示元件的區域的真實形狀，且並非傾向於限制示範實施例的範疇。
圖1A為根據本發明概念的一些實施例的堆疊封裝元件的平面圖。圖1B為沿著圖1A的I-I’截面線所裁切的截面圖。圖1C與圖1D為圖1B的A部分的放大圖。
參考圖1A與圖1B，根據本發明實施例堆疊封裝元件100可包括下部半導體封裝50與上部半導體封裝60。
下部半導體封裝50可包括下部封裝基板1、安裝在下部封裝基板1上的下部半導體晶片20、以及覆蓋下部封裝基板1與下部半導體晶片20的下模層22。第一下墊片3設置於下部封裝基板1的上表面，且第二下墊片7設置於下部封裝基板1的下表面。第一下墊片3與第二下墊片7可被絕緣層覆蓋。下部半導體晶片20透過第一下部焊料凸塊11與第一下墊片3電性連接。利用覆晶接合(flip chip bonding)方法可將下部半導體晶片20安裝在封裝基板1上。第二焊料凸塊26分別設置於第二下墊片7上。下模層22可覆蓋下部半導體晶片20的側壁，並可暴露出下部半導體晶片20的上表面。換言之，下部半導體晶片20的上表面不會被下模層22覆蓋。下模層22可包括與下部半導體晶片20隔開的連接孔24。
上部半導體封裝60包括上部封裝基板32、安裝在上部封裝基板32上的上部半導體晶片38與40、以及覆蓋上部半導體晶片38與40及上部封裝基板32的上模層42。上部半導體晶片38與40藉由打線接合(wire bonding)的方式與上部封裝基板32電性耦接。第一上墊片34設置於上部封裝基板32的上表面，且第二上墊片36設置於上部封裝基板32的下表面。每個上模層42與下模層22可包括樹脂層與分散於樹脂層的多個填充粒子。樹脂層可包括聚合物。填充粒子可包括諸如二氧化矽及/或二氧化鋁的材料。
上部半導體封裝60堆疊在下部半導體封裝50上。上部半導體封裝60與下部半導體封裝50藉由在其之間的連接的焊料 凸塊33彼此電性連接。每個連接的焊料凸塊33分別接觸第二上墊片36與第一下墊片3。參考圖1C與圖1D，可將每個連接的焊料凸塊33設置於各別的連接孔24(亦稱為接觸窗)中。每個連接的焊料凸塊33的側壁可與各別的連接孔24的內側壁隔開。在連接的焊料凸塊33的側壁與連接孔24的內側壁之間的間隙可填充密封層85。可延伸密封層85以同時接觸上部半導體封裝60的下表面與下部半導體封裝50的上表面。連接孔24的側壁的表面粗糙度會大於與下部封裝基板1隔開的下模層22的上表面23的表面粗糙度。因為連接孔24的側壁的表面積由於增大的表面粗糙度而增大，在密封層85與連接孔24的側壁之間的吸附力會增加。如圖1C所示，密封層85可直接接觸下模層22的上表面23。如圖1D所示，分層區DX可存在於密封層85與下模層22的上表面23之間。
密封層85可包括環氧樹脂，例如環氧樹脂可為雙酚F型環氧樹脂。進而，密封層可具有助焊(flux)功能。例如，環氧樹脂可具有助焊功能以致密封層85具有助焊功能。或者，密封層85所含的其他成分部分可具助焊功能。例如，密封層85可更包括硬化劑以硬化環氧樹脂，且硬化劑可具助焊功能。例如，具助焊功能的硬化劑可包括酚樹脂、酚系羧酸、酸酐、羧酸、及/或芳香族醯肼。在其他實施例中，密封層85可更另外包括具助焊功能的助焊成分部分。例如，助焊成分部分可包括羧酸、含有硫、松香 (rosin)、松香的衍生物、及/或合成樹脂的酚化合物。密封層85可更包括如二氧化矽的無機物填料。
因為密封層85包圍連接的焊料凸塊33的側壁並接觸上部半導體封裝60與下部半導體封裝50，可減少及/或避免連接的焊料凸塊33破裂，並可保護連接的焊料凸塊33。例如，可減少上部半導體封裝60與下部半導體封裝50之間的接合裂開。此外，藉由密封層85可增加上部半導體封裝60與下部半導體封裝50之間的接觸面積，或可減小上部半導體封裝60與下部半導體封裝50之間的非接觸面積，從而可減小整個POP元件100的翹曲程度。進而，藉由密封層85可保護連接的焊料凸塊33、上部半導體封裝60、及/或下部半導體封裝50免於潮濕、外部汙染、及/或腐蝕。
圖2與圖3繪示根據本發明概念的一些實施例的圖1A與圖1B的POP元件的製造方法的截面圖。
參考圖2，準備含有密封層樹脂溶液85a的容器90。密封層樹脂溶液85a可包括環氧樹脂並具助焊功能。例如，環氧樹脂可包括雙酚F型環氧樹脂。環氧樹脂可具有助焊功能，因此密封層樹脂溶液85a具有助焊功能。或者，密封層樹脂溶液85a所含的其他成分部份可提供助焊功能。例如，密封層樹脂溶液85a可更包括硬化劑以硬化環氧樹脂，且硬化劑可提供助焊功能。例如，具助焊功能的硬化劑可包括酚樹脂、酚系羧酸、酸酐、羧酸、及/或芳香族醯肼。在其他實施例中，密封層樹脂溶液85a可更另外包括提供助焊功能的助焊成分部份。例如，助焊成分部份可包 括羧酸、含有硫、松香(rosin)、松香的衍生物、及/或合成樹脂的酚化合物。密封層樹脂溶液85a可更包括如二氧化矽的無機物填料。密封層樹脂溶液85a可更包括溶解/分散環氧樹脂、硬化劑、及/或助焊成分部份的溶劑。
上部半導體封裝60設置於容器90上。參考圖1A所述，上部半導體封裝60包括上部封裝基板32、安裝在上部封裝基板32上的上部半導體晶片38與40、覆蓋上部封裝基板32及上部半導體晶片38與40的上模層42、第一上墊片34、以及第二上墊片36。此外，上部焊料凸塊30分別黏附至第二上墊片36。將上部半導體封裝60降低，使密封層樹脂溶液85a僅大致塗覆在上部焊料凸塊30的表面。
參考圖3，上部半導體封裝60設置在下部半導體封裝50上。參考圖1A所述，下部半導體封裝50可包括下部封裝基板1、安裝在下部封裝基板1上的下部半導體晶片20、覆蓋下部封裝基板1與下部半導體晶片20的下模層22、第一下墊片3、第二下墊片7、第一下部焊料凸塊11、以及第二下部焊料凸塊26。此外，下部半導體封裝50可更包括位於與第一下部焊料凸塊11隔開的第一下墊片3上的第三下部焊料凸塊13。在各個連接孔24中可露出第三下部焊料凸塊13。藉由對下模層22雷射鑽孔可形成連接孔24。因此，藉由雷射鑽孔，每個連接孔24的側壁的表面粗糙度會大於與下部封裝基板1隔開的下模層22的上表面的表面粗糙度。當上部半導體封裝60設置在下部半導體封裝50上時，塗覆有密 封層樹脂溶液85a的上部焊料凸塊30對準在連接孔24中，並與各個第三下部焊料凸塊13接合。連接孔24可用來作為避免/減少密封層樹脂溶液85a流到外面的容器。另外，連接孔24可固定上部半導體封裝60的位置。
再次參考圖1A、圖1B、及圖1C，在與上部焊料凸塊30與第三下部焊料凸塊13的熔點相等或更高的溫度下加熱上部焊料凸塊30與第三下部焊料凸塊13。此時，由於連接孔24中密封層樹脂溶液85a所含的助焊成分部分及/或密封層樹脂溶液85a的助焊功能，可移除/減少上部焊料凸塊30與第三下部焊料凸塊13的表面上的氧化層，並可減小焊接的表面張力。如圖1B所示，可將上部焊料凸塊30與第三下部焊料凸塊13融化並互相接合(在迴焊操作中)而形成連接的焊料凸塊33。在此過程中，將密封層樹脂溶液85a所含的環氧樹脂硬化，並將密封層樹脂溶液85a中的溶劑移除。因此，密封層樹脂溶液85a可形成密封層85。
圖4與圖5繪示根據本發明概念的其他實施例的圖1A與圖1B的POP元件的製造方法的截面圖。
參考圖4，密封層樹脂溶液85a可塗覆在下部半導體封裝50上。此時，可選擇地塗覆密封層樹脂溶液85a而設置於連接孔24中。連接孔24可用來作為避免/減少密封層樹脂溶液85a流到外面的容器。
參考圖5，上部半導體封裝60設置於下部半導體封裝50上，從而藉由密封層樹脂溶液85a，上部焊料凸塊30分別對準連接孔24。因此，上部焊料凸塊30與第三下部焊料凸塊13接合。
繼而，如上所述，進行加熱程序(在迴焊操作中)以形成連接的焊料凸塊33與密封層85。
參考圖3或圖5所繪示的POP元件的製造方法，至少一個第三下部焊料凸塊13及/或上部焊料凸塊30會塗覆有具助焊功能的密封層樹脂溶液85a，然後對其加熱。因此，能相當簡便並快速地形成連接的焊料凸塊33與密封層85。
圖1A與圖1B的POP元件的其他製造方法會不同於上述方法。圖6為繪示根據本發明概念的其他實施例的圖1A與圖1B的POP元件的製造方法的截面圖。
參考圖6，上部半導體封裝60設置於下部半導體封裝50上。將僅具助焊功能而不含環氧樹脂的溶液塗覆在上部焊料凸塊30及/或下部焊料凸塊13上，然後對其加熱而形成連接的焊料凸塊33。因此，可在上部半導體封裝60與下部半導體封裝50之間提供含有環氧樹脂的密封層樹脂溶液，然後將密封層樹脂溶液硬化而形成密封層85。
圖7A、圖7B、及圖7C為繪示根據本發明概念的其他實施例的POP元件的截面圖。
參考圖7A，在根據本實施例的POP元件101a中，圖1A的密封層85延伸而填充上部半導體封裝60與下部半導體封裝50 之間的整個間隙。如圖7A所示，密封層85可突出於上部半導體封裝60與下部半導體封裝50之間的間隙外面。POP元件101a的其他組件可與圖1B所示的對應的組件相同。圖7A中的密封層85可與下部半導體晶片20的上表面接觸。因此，可進一步減小POP元件101a的翹曲程度。
參考圖7B，在根據本實施例的POP元件101b中，下模層22可覆蓋下部半導體晶片20的上表面。POP元件101b的其他組件可與圖7A中對應的組件相同。密封層85可接觸下模層22的上表面。
參考圖7C，根據本實施例的POP元件101c可具有與圖7A的POP元件類似的結構。然而在圖7C中，密封層85可侷限在上部半導體封裝60與下部半導體封裝50之間間隙內。因此，圖7C的密封層85不會突出於上部半導體封裝60與下部半導體封裝50之間的間隙外面。圖7C的其他組件可與上述相對於圖7A的組件相同。
圖8為繪示根據本發明概念的實施例的圖7A的POP元件的製造方法的截面圖。
參考圖8，如參考圖2所示，將上部半導體封裝60的下部浸漬於密封層樹脂溶液85a。在圖8中，將密封層樹脂溶液85a塗覆在上部半導體封裝60的整個底面上。因此，上部半導體封裝60設置在下部半導體封裝50上，然後加熱(在迴焊操作中)上部 半導體封裝60與下部半導體封裝50而形成如圖7A所示的POP元件101a。
圖9為繪示根據本發明概念的其他實施例的圖7A的POP元件的製造方法的截面圖。
參考圖9，將密封層樹脂溶液85a塗覆在下部半導體封裝50的整個表面上。因此，上部半導體封裝60設置於下部半導體封裝50上，然後加熱(在迴焊操作中)上部半導體封裝60與下部半導體封裝50而形成圖7A的POP元件101a。
圖10至圖13為繪示根據本發明概念的其他實施例的POP元件的截面圖。
參考圖10，在根據本實施例的POP元件102中，下部半導體封裝50不會包括下模層22。密封層85可覆蓋連接的焊料凸塊33的側壁。此外，密封層85可延伸而同時與下部半導體封裝50及上部半導體封裝60接觸。此時，在下部半導體晶片20與下部封裝基板1之間的間隙可填充底膠樹脂層87。底膠樹脂層87可具有與密封層85相同及/或類似的組成。POP元件102的其他組件可與圖1A的對應組件相同及/或類似。圖10的POP元件102的製造方法可類似於參考圖3所示的方法。
參考圖11，在根據本實施例的POP元件103中，密封層85可覆蓋2個(或以上)相鄰連接的焊料凸塊33的側壁，並填充2個(或以上)相鄰連接的焊料凸塊33之間的間隙。因此，密封層85可設置於下部半導體晶片20與上部封裝基板32之間。POP 元件103的其他組件可與圖10的對應組件相同及/或類似。圖11的POP元件103的製造方法可類似於參考圖5所示的方法。
參考圖12，在根據本實施例的POP元件104中，在下部半導體封裝50與上部半導體封裝60之間的整個間隙可填充密封層85。POP元件104的其他實施例可與圖11的對應的組件相同及/或類似。圖12的POP元件104的製造方法可類似於參考圖5所示的方法。
參考圖13，根據本實施例的POP元件105包括下部半導體封裝50與上部半導體封裝70。上部半導體封裝70可包括上部封裝基板32與多個上部半導體晶片52。透過上部內焊料凸塊56利用覆晶接合方法可堆疊多個半導體晶片52並安裝在上部封裝基板32上。上部半導體晶片52可包括重疊上部內焊料凸塊56並位於上部半導體晶片52的貫孔54。上模層42亦可覆蓋上部內焊料凸塊56的側壁。POP元件105的其他組件可與圖1B的對應的組件相同及/或類似。
圖14A為根據本發明概念的其他實施例的POP元件的平面圖。圖14B為沿著圖14A的I-I’截面線所裁切的截面圖。
參考圖14A與圖14B，POP元件106可包括覆蓋連接的焊料凸塊33的側壁的第一密封層85以及填充在下部半導體晶片20與上部封裝基板32之間的間隙的第二密封層95。第一密封層85可與參考圖1B所示的密封層85相同。第二密封層95可包括環氧樹脂，但不具備助焊功能。因為第二密封層95不具備助焊功 能，第二密封層95與下部半導體晶片20之間及/或第二密封層95與上部封裝基板32之間可供應增大的吸附力。
利用以下操作可形成圖14A與圖14B的POP元件106。首先，在連接孔24內供應密封層樹脂溶液85a(具備或不具備助焊功能)。將另外的密封層樹脂溶液(不具備助焊功能)塗覆在下部半導體晶片20上。然後，將上部半導體封裝60設置於下部半導體封裝50上，並加熱而形成連接的焊料凸塊33、第一密封層85、及第二密封層95。其它組件及/或操作可與參考圖1B所示的組件/操作相同或類似。
上述半導體封裝技術可應用於各種半導體元件以及包括各種半導體元件的封裝模組。
圖15為繪示包括根據上述本發明概念的實施例的至少一種半導體封裝的電子元件的透視圖。
參考圖15，根據本發明概念的實施例的POP元件可應用於諸如智慧型手機的電子元件1000。因為根據上述實施例的POP元件在尺寸縮小及/或性能上可提供改良的特性，POP元件可提供減輕重量、減少厚度、縮短長度/寬度、及/或縮小同時執行各種其他功能的電子元件1000的尺寸的益處。圖15所示的電子元件1000並不限於智慧型手機。在其他實施例中，電子元件1000可實際作為諸如行動電子元件、筆記型電腦、可攜式電腦、可攜式多媒體播放器(Portable Multimedia Player，PMP)、MP3播放器、攝錄影機(camcorder)、網路平板電腦(web tablet)、無線電話、導航 裝置(navigation device)、及/或個人數位助理(PDA)的各種電子元件。
圖16為繪示根據上述本發明概念的實施例的包括至少一種半導體封裝的電子元件的系統方塊圖。
參考圖16，根據其他實施例，一個以上的POP元件100至106可應用於電子元件1100。電子元件1100可包括主體1110、微處理單元1120、電源單元1130、作用單元1140、以及顯示控制單元1150。主體1110可包括構成印刷電路板的固定板(set board)。微處理單元1120、電源單元1130、作用單元1140、及/或顯示控制單元1150可安裝在主體1110上。
電源單元1130可供應來自外部/內部電池(未圖式)的預定電壓，然後預定電壓可分成所希望的電壓位準。電源單元1130可將所希望的電壓位準供應至微處理單元1120、作用單元1140、以及顯示控制單元1150。
可將自電源單元1130的電壓供應至微處理單元1120，然後控制作用單元1140與顯示單元1160。作用單元1140可執行電子元件1100的各種功能。例如，如果電子元件1100為可攜式電話，作用單元1140可包括能執行可攜式電話功能(諸如如撥號、藉由與外部裝置1170相通的顯示單元1160的影像輸出、以及說話者的聲音輸出)的各種組件。如果電子元件1100包括照相機，作用單元1140可包括照相機影像處理器。例如，如果將電子元件1100連接至記憶卡以擴充記憶容量，作用單元1140可為記憶卡控 制器。作用單元1140可透過有線或無線的通訊單元1180與外部裝置1170相通。例如，如果電子元件1100需要通用序列匯流排(universal serial bus，USB)來擴充功能，作用單元1140可包括介面控制器。根據以上實施例的一個以上的POP元件100至106可用作至少一個微處理單元1120及/或作用單元1140。
上述半導體封裝技術可應用於電子系統。
圖17為繪示根據本發明概念的實施例包括至少一個半導體封裝的電子系統的示範的方塊圖。
參考圖17，電子系統1300可包括控制器1310、輸入/輸出元件1320、以及記憶元件1330。控制器1310、輸入/輸出元件1320、以及記憶元件1330藉由匯流排1350可互相接合/耦接。藉由傳送電子訊號，匯流排1350可對應至路徑。例如，控制器1310可包括至少一個微處理器、數位訊號處理器、微控制器、及/或其他邏輯元件。其他邏輯元件可具有類似於微處理器、數位訊號處理器、及/或微控制器的任一種的功能。根據本發明概念的實施例，控制器1310及/或記憶元件1330可包括POP元件。輸入/輸出元件1320可包括按鍵、鍵盤、及/或顯示單元。記憶元件1330可為儲存資料的元件。記憶元件1330可儲存資料及/或控制器1310所執行的命令。記憶元件1330可包括揮發性記憶元件及/或非揮發性記憶元件，或者記憶元件1330可包括快閃記憶體。快閃記憶體可實際作為固態硬碟(solid state disk，SSD)。在此情形下，電子系統1300可穩定儲存記憶元件1330中的大量資料。電子系統1300 可進一步包括可傳送電子資料至通訊網路或可接收來自通訊網路的電子資料的介面1340。利用無線或有線的資料連接可操作介面1340。例如，介面單元1340可包括用於無線通訊的天線(antenna)或用於有線通訊的收發器(transceiver)。雖然未繪示於圖式中，應用晶片組及/或照相機影像處理器(CIS)亦可應用於電子系統1300。
在根據本發明概念的實施例的POP元件中，密封層可存在於上部半導體封裝與下部半導體封裝之間。因此，上部半導體封裝與下部半導體封裝的接觸面積會增加，從而減小POP元件的翹曲程度。此外，藉由密封層可保護連接的焊料凸塊、上部半導體封裝、及下部半導體封裝免於潮濕、外部污染、及/或腐蝕。
在密封層包圍連接的焊料凸塊的側壁並接觸上部半導體封裝與下部半導體封裝的實施例中，密封層可保護連接的焊料凸塊以減少及/或避免連接的焊料凸塊破裂。利用根據所述實施例的密封層可減少及/或避免上部半導體封裝與下部半導體封裝之間的接合破裂。
因為利用覆晶接合方法將下部半導體晶片安裝在下部封裝基板上，可減小電子通道的長度。因此，可改善訊號的傳送速度。
在製造根據本發明概念的實施例的POP元件的方法中，至少一個的下部焊料凸塊與上部焊料凸塊可塗覆有具助焊功能的 密封層樹脂溶液，然後在迴焊操作中加熱。因此，可相當簡便並快速地形成連接的焊料凸塊與密封層。
雖然已參照示範實施例描述本發明概念，本技術所屬領域具有通常知識者將顯而易見的是，在不違背本發明概念的精神及範疇的情況下，可做出多種改變及改良。因此，應當理解的是，以上實施例並非限制性而是說明性。因此，本發明概念的範疇將是藉由以下申請專利範圍及其相等的最寬可允許的解釋來決定，且本發明概念的範疇不應當被前面的描述所侷限或是限制。
1‧‧‧下部封裝基板
3‧‧‧第一下墊片
7‧‧‧第二下墊片
11‧‧‧第一下部焊料凸塊
20‧‧‧下部半導體晶片
22‧‧‧下模層
24‧‧‧連接孔
26‧‧‧第二焊料凸塊
32‧‧‧上部封裝基板
33‧‧‧連接的焊料凸塊
34‧‧‧第一上墊片
36‧‧‧第二上墊片
38、40‧‧‧上部半導體晶片
42‧‧‧上模層
50‧‧‧下部半導體封裝
60‧‧‧上部半導體封裝
85‧‧‧密封層
100‧‧‧堆疊封裝元件
A‧‧‧A部分

Claims (33)

  1. 一種堆疊封裝電子元件，包括：第一封裝基板與第二封裝基板；焊料接點，提供所述第一封裝基板與所述第二封裝基板之間的電性與機械耦接；以及第一密封層與第二密封層，在所述第一封裝基板與所述第二封裝基板之間，其中所述第一密封層包括模層，所述模層在具有連接孔的所述第一封裝基板上，其中所述焊料接點延伸通過所述連接孔，且其中部分的所述第二密封層在所述模層與所述焊料接點之間的所述連接孔中。
  2. 如申請專利範圍第1項所述的堆疊封裝電子元件，其中所述第一密封層與所述第二密封層分別包括第一環氧樹脂密封層與第二環氧樹脂密封層。
  3. 如申請專利範圍第2項所述的堆疊封裝電子元件，其中所述第二環氧樹脂密封層包括助焊劑，且相較於所述第二環氧樹脂密封層，所述第一環氧樹脂密封層具有較低濃度的所述助焊劑。
  4. 如申請專利範圍第1項所述的堆疊封裝電子元件，其中部分的所述第二密封層在所述模層與所述第二封裝基板之間。
  5. 如申請專利範圍第1項所述的堆疊封裝電子元件，其中在所述模層與所述第二密封層之間定義一介面。
  6. 如申請專利範圍第1項所述的堆疊封裝電子元件，其中通過所述模層的所述連接孔的側壁的表面粗糙度大於與所述第一封裝基板隔開的所述 模層的表面的表面粗糙度。
  7. 如申請專利範圍第1項所述的堆疊封裝電子元件，其中所述第一密封層與所述第二密封層在所述第一封裝基板與所述第二封裝基板之間隔開。
  8. 如申請專利範圍第1項所述的堆疊封裝電子元件，更包括：電性及機械耦接至所述第一封裝基板的半導體積體電路元件，其中所述半導體積體電路元件在所述第一封裝基板與所述第二封裝基板之間，且所述半導體積體電路元件與所述焊料接點隔開。
  9. 如申請專利範圍第8項所述的堆疊封裝電子元件，更包括：在所述半導體積體電路元件與所述第一封裝基板之間的多數個焊料凸塊，其中所述多數個焊料凸塊提供所述半導體積體電路元件與所述第一封裝基板之間的電性與機械耦接。
  10. 如申請專利範圍第8項所述的堆疊封裝電子元件，其中所述半導體積體電路元件包括第一半導體積體電路元件，所述堆疊封裝電子元件更包括：電性及機械耦接至所述第二封裝基板的第二半導體積體電路元件，其中所述第二封裝基板在所述第二半導體積體電路元件與所述第一封裝基板之間。
  11. 如申請專利範圍第10項所述的堆疊封裝電子元件，更包括：在所述第二半導體積體電路元件與所述第二封裝基板之間的多數個焊料凸塊，其中所述多數個焊料凸塊提供所述第二半導體積體電路元件與所述第二封裝基板之間的電性與機械耦接。
  12. 如申請專利範圍第10項所述的堆疊封裝電子元件，更包括： 多數條焊線，提供所述第二半導體積體電路元件與所述第二封裝基板之間的電性耦接。
  13. 如申請專利範圍第10項所述的堆疊封裝電子元件，更包括：電性耦接至所述第二封裝基板的第三半導體積體電路元件，其中所述第三半導體積體電路元件在所述第二半導體積體電路元件上，所述第二半導體積體電路元件在所述第三半導體積體電路元件與所述第二封裝基板之間。
  14. 如申請專利範圍第1項所述的堆疊封裝電子元件，其中所述第一封裝基板具有第一表面與第二表面，其中所述第一表面在所述第二表面與所述第二封裝基板之間，所述堆疊封裝電子元件更包括：在所述第一封裝基板的第二表面上的多數個焊料凸塊，其中透過所述第一封裝基板提供所述焊料接點與至少一個的所述多數個焊料凸塊之間的電性耦接。
  15. 一種堆疊封裝電子元件，包括：第一封裝基板；電性與機械耦接至所述第一封裝基板的半導體積體電路元件；第二封裝基板，在所述第一封裝基板上，所述半導體積體電路元件在所述第一封裝基板與所述第二封裝基板之間；焊料接點，提供所述第一封裝基板與所述第二封裝基板之間的電性與機械耦接，且所述焊料接點與所述半導體積體電路元件隔開；密封層，在所述第一封裝基板與所述第二封裝基板之間的所述焊料接點上；以及 模層，設置在所述第一封裝基板與所述第二封裝基板之間，並包括貫穿所述模層的連接孔，其中所述焊料接點延伸通過在所述第一封裝基板與所述第二封裝基板之間的所述連接孔，且其中部分的所述密封層在所述模層與所述焊料接點之間的所述連接孔中。
  16. 如申請專利範圍第15項所述的堆疊封裝電子元件，其中所述密封層與所述半導體積體電路元件隔開。
  17. 如申請專利範圍第15項所述的堆疊封裝電子元件，其中所述焊料接點包括第一焊料接點，所述堆疊封裝電子元件更包括：第二焊料接點，提供所述第一封裝基板與所述第二封裝基板之間的電性與機械耦接，所述第二焊料接點與所述第一焊料接點隔開，並與所述半導體積體電路元件隔開。
  18. 如申請專利範圍第17項所述的堆疊封裝電子元件，其中所述密封層包括第一密封層，所述堆疊封裝電子元件更包括：第二密封層，在所述第一封裝基板與所述第二封裝基板之間的所述第二焊料接點上，其中所述第一密封層與所述第二密封層在所述第一焊料接點與所述第二焊料接點之間隔開。
  19. 如申請專利範圍第17項所述的堆疊封裝電子元件，其中所述密封層包括連續的密封層，在所述第一封裝基板與所述第二封裝基板之間的所述第一焊料接點與所述第二焊料接點上。
  20. 如申請專利範圍第15項所述的堆疊封裝電子元件，其中所述密封層包括連續的密封層，在所述焊料接點上及在所述第一封裝基板與所述第二封裝基板之間的所述半導體積體電路元件上。
  21. 如申請專利範圍第15項所述的堆疊封裝電子元件，更包括：多數個焊料凸塊，提供所述半導體積體電路元件與所述第一封裝基板之間的電性與機械耦接；以及底膠材料，在所述半導體積體電路元件與所述第一封裝基板之間的所述多數個焊料凸塊上。
  22. 如申請專利範圍第21項所述的堆疊封裝電子元件，其中所述底膠材料與所述密封層隔開。
  23. 如申請專利範圍第15項所述的堆疊封裝電子元件，其中所述密封層包括環氧樹脂與助焊劑。
  24. 如申請專利範圍第15項所述的堆疊封裝電子元件，其中部分的所述密封層在所述模層與所述第二封裝基板之間。
  25. 如申請專利範圍第15項所述的堆疊封裝電子元件，其中所述半導體積體電路元件相鄰所述第二封裝基板的表面沒有所述模層。
  26. 如申請專利範圍第15項所述的堆疊封裝電子元件，其中部分的所述模層在所述半導體積體電路元件與所述第二封裝基板之間延伸。
  27. 如申請專利範圍第15項所述的堆疊封裝電子元件，其中通過所述模層的所述連接孔的側壁的表面粗糙度大於與所述第一封裝基板隔開的所述模層的表面的表面粗糙度。
  28. 如申請專利範圍第15項所述的堆疊封裝電子元件，其中所述半導體積體電路元件包括第一半導體積體電路元件，所述堆疊封裝電子元件更包括：電性與機械耦接至所述第二封裝基板的第二半導體積體電路元件，所 述第二封裝基板在所述第二半導體積體電路元件與所述第一封裝基板之間。
  29. 一種堆疊封裝電子元件的形成方法，包括：供應第一封裝基板，具有與所述第一封裝基板電性與機械耦接的第一半導體積體電路元件；供應第二封裝基板，具有與所述第二封裝基板電性與機械耦接的第二半導體積體電路元件；在所述第一封裝基板與所述第二封裝基板之間供應焊料接點，並加熱所述接點焊料結構，在所述第一封裝基板與所述第二封裝基板之間具有與所述焊料接點隔開的所述第一半導體積體電路元件；以及在所述焊料接點上供應密封層，其中供應所述密封層包括在對所述接點焊料結構加熱之前在所述接點焊料結構上供應液體密封材料，並硬化所述液體密封材料以形成所述密封層。
  30. 如申請專利範圍第29項所述的堆疊封裝電子元件的形成方法，其中提供所述焊料接點包括在所述第一封裝基板及/或所述第二封裝基板的至少一者上供應接點焊料結構。
  31. 如申請專利範圍第29項所述的堆疊封裝電子元件的形成方法，其中所述液體密封材料包括液體環氧樹脂密封材料與助焊劑。
  32. 一種堆疊封裝電子元件的形成方法，包括：在第一封裝基板上供應模層，其中所述模層包括貫穿其的連接孔；在所述第一封裝基板與第二封裝基板之間供應焊料接點，其中所述焊料接點延伸通過所述連接孔，以提供所述第一封裝基板與所述第二封裝基板之間的電性與機械耦接；以及 在所述模層與所述第二封裝基板之間及在所述模層與所述焊料接點之間的所述連接孔中供應密封層。
  33. 如申請專利範圍第32項所述的堆疊封裝電子元件的形成方法，其中通過所述模層的所述連接孔的側壁的表面粗糙度大於與所述第一封裝基板隔開的所述模層的表面的表面粗糙度。
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