JP2012138604A - Soi型トランジスタ - Google Patents
Soi型トランジスタ Download PDFInfo
- Publication number
- JP2012138604A JP2012138604A JP2012046311A JP2012046311A JP2012138604A JP 2012138604 A JP2012138604 A JP 2012138604A JP 2012046311 A JP2012046311 A JP 2012046311A JP 2012046311 A JP2012046311 A JP 2012046311A JP 2012138604 A JP2012138604 A JP 2012138604A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- layer
- diffusion region
- drain
- semiconductor material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000009792 diffusion process Methods 0.000 claims abstract description 42
- 239000004065 semiconductor Substances 0.000 claims abstract description 33
- 239000000463 material Substances 0.000 claims abstract description 24
- 239000012212 insulator Substances 0.000 claims description 32
- 230000015654 memory Effects 0.000 abstract description 34
- 239000010410 layer Substances 0.000 description 74
- 235000012431 wafers Nutrition 0.000 description 23
- 239000003990 capacitor Substances 0.000 description 11
- 239000012535 impurity Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 11
- 239000000758 substrate Substances 0.000 description 9
- 230000005669 field effect Effects 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000005380 borophosphosilicate glass Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000002708 enhancing effect Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000007943 implant Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/905—Plural dram cells share common contact or common trench
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Thin Film Transistor (AREA)
Abstract
【解決手段】SOI型のトランジスタは、半導体物質層60(SOI層)と、この半導体物質層60の内部を通って走るゲート線65a,65b,66cと、このゲート線65a,65b,66cに沿ってソース拡散領域70a、70b、70cよりも遠くまで延びるドレイン拡散領域64と、このドレイン拡散領域64よりも上方にあるソース拡散領域70a、70b、70cと、ドレイン拡散領域64まで延びるドレインコンタクト79と、ソース拡散領域まで延びるソースコンタクトと、を備え、これらドレインコンタクト79及びソースコンタクトは、ゲート線65a,65b,66cと平行に走る平面内にある。
【選択図】図16
Description
絶縁体層と、
前記絶縁体層上に設けられ、上面を有する半導体物質層と、
前記半導体物質層の内部にそれを貫通して設けられ、前記半導体物質層中に縦方向に延びる細長いトランジスタゲート線であって、該ゲートが前記縦方向に延びる互いに反対側の横側面を有する、トランジスタゲート線と、
前記トランジスタゲートの前記横側面の一方上の半導体物質層の内部に収容され、前記トランジスタゲートの下方には延びず、前記トランジスタゲートの前記横側面の他方上には存在しないドレイン拡散領域であって、前記トランジスタゲートに沿ってソース拡散領域よりも遠くまで延びるドレイン拡散領域と、
前記トランジスタゲートの前記横側面の前記一方上の前記半導体物質層の内部に収容され、前記ドレイン上に上下方向に延び、前記トランジスタゲートの前記横側面の前記他方上には存在しないソース拡散領域と、
前記半導体物質層の上面まで、かつ、前記ソース拡散領域まで、下方に延びるソースコンタクトと、
前記半導体物質層の上面を貫通して、かつ、前記ドレイン拡散領域まで、下方に延びるドレインコンタクトと、を備え、
前記ソース及びドレインコンタクトは、前記ゲート線と実質的に平行に走る平面内にある。
12 バルクシリコン
14 絶縁層
16 半導体物質層(SOI層)
24 ゲート線開口
30 ゲート線
34 第一のマスク
36 第二のマスク
35、35a ソース/ドレイン拡散領域
38、38a ソース/ドレイン拡散領域
44、44a 第一のコンタクト
45、45a 第二のコンタクト
Claims (1)
- セミコンダクタ・オン・インシュレータ型のトランジスタであって、
絶縁体層と、
前記絶縁体層上に設けられ、上面を有する半導体物質層と、
前記半導体物質層の内部にそれを貫通して設けられ、前記半導体物質層中に縦方向に延びる細長いトランジスタゲート線であって、該ゲートが前記縦方向に延びる互いに反対側の横側面を有する、トランジスタゲート線と、
前記トランジスタゲートの前記横側面の一方上の半導体物質層の内部に収容され、前記トランジスタゲートの下方には延びず、前記トランジスタゲートの前記横側面の他方上には存在しないドレイン拡散領域であって、前記トランジスタゲートに沿ってソース拡散領域よりも遠くまで延びるドレイン拡散領域と、
前記トランジスタゲートの前記横側面の前記一方上の前記半導体物質層の内部に収容され、前記ドレインの上方にあり、前記トランジスタゲートの前記横側面の前記他方上には存在しないソース拡散領域と、
前記半導体物質層の上面まで、かつ、前記ソース拡散領域まで、下方に延びるソースコンタクトと、
前記半導体物質層の上面を貫通して、かつ、前記ドレイン拡散領域まで、下方に延びるドレインコンタクトと、
を備え、
前記ソース及びドレインコンタクトは、前記ゲート線と実質的に平行に走る平面内にある、セミコンダクタ・オン・インシュレータ型のトランジスタ。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/668,388 US5929476A (en) | 1996-06-21 | 1996-06-21 | Semiconductor-on-insulator transistor and memory circuitry employing semiconductor-on-insulator transistors |
US08/668,388 | 1996-06-21 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008036383A Division JP5476619B2 (ja) | 1996-06-21 | 2008-02-18 | Soi型トランジスタを用いたメモリアレイ |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012138604A true JP2012138604A (ja) | 2012-07-19 |
JP5629872B2 JP5629872B2 (ja) | 2014-11-26 |
Family
ID=24682129
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50331098A Expired - Fee Related JP3545768B2 (ja) | 1996-06-21 | 1997-06-18 | Soi型トランジスタの製造方法 |
JP2003324496A Pending JP2004104135A (ja) | 1996-06-21 | 2003-09-17 | Soi型トランジスタを用いたsoi型トランジスタ回路及びその製造方法 |
JP2008036383A Expired - Fee Related JP5476619B2 (ja) | 1996-06-21 | 2008-02-18 | Soi型トランジスタを用いたメモリアレイ |
JP2012046311A Expired - Lifetime JP5629872B2 (ja) | 1996-06-21 | 2012-03-02 | Soi型トランジスタ |
Family Applications Before (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50331098A Expired - Fee Related JP3545768B2 (ja) | 1996-06-21 | 1997-06-18 | Soi型トランジスタの製造方法 |
JP2003324496A Pending JP2004104135A (ja) | 1996-06-21 | 2003-09-17 | Soi型トランジスタを用いたsoi型トランジスタ回路及びその製造方法 |
JP2008036383A Expired - Fee Related JP5476619B2 (ja) | 1996-06-21 | 2008-02-18 | Soi型トランジスタを用いたメモリアレイ |
Country Status (6)
Country | Link |
---|---|
US (4) | US5929476A (ja) |
EP (1) | EP0907967A2 (ja) |
JP (4) | JP3545768B2 (ja) |
KR (1) | KR100519127B1 (ja) |
AU (1) | AU3492997A (ja) |
WO (1) | WO1997049134A2 (ja) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5929476A (en) | 1996-06-21 | 1999-07-27 | Prall; Kirk | Semiconductor-on-insulator transistor and memory circuitry employing semiconductor-on-insulator transistors |
US6284574B1 (en) * | 1999-01-04 | 2001-09-04 | International Business Machines Corporation | Method of producing heat dissipating structure for semiconductor devices |
US6952029B1 (en) * | 1999-01-08 | 2005-10-04 | Micron Technology, Inc. | Thin film capacitor with substantially homogenous stoichiometry |
DE29923162U1 (de) * | 1999-02-01 | 2000-04-27 | Siemens Ag | Langgestreckter Supraleiteraufbau mit Hoch-T¶c¶·-Supraleitermaterial und metallischem Träger |
US6355520B1 (en) * | 1999-08-16 | 2002-03-12 | Infineon Technologies Ag | Method for fabricating 4F2 memory cells with improved gate conductor structure |
US6500744B2 (en) | 1999-09-02 | 2002-12-31 | Micron Technology, Inc. | Methods of forming DRAM assemblies, transistor devices, and openings in substrates |
US6544837B1 (en) * | 2000-03-17 | 2003-04-08 | International Business Machines Corporation | SOI stacked DRAM logic |
JP4021602B2 (ja) * | 2000-06-16 | 2007-12-12 | 株式会社東芝 | 半導体記憶装置 |
US6537891B1 (en) * | 2000-08-29 | 2003-03-25 | Micron Technology, Inc. | Silicon on insulator DRAM process utilizing both fully and partially depleted devices |
JP3808700B2 (ja) * | 2000-12-06 | 2006-08-16 | 株式会社東芝 | 半導体装置及びその製造方法 |
US6649476B2 (en) * | 2001-02-15 | 2003-11-18 | Micron Technology, Inc. | Monotonic dynamic-static pseudo-NMOS logic circuit and method of forming a logic gate array |
KR100471164B1 (ko) * | 2002-03-26 | 2005-03-09 | 삼성전자주식회사 | 금속-절연체-금속 캐패시터를 갖는 반도체장치 및 그제조방법 |
EP1355316B1 (en) * | 2002-04-18 | 2007-02-21 | Innovative Silicon SA | Data storage device and refreshing method for use with such device |
KR100632658B1 (ko) * | 2004-12-29 | 2006-10-12 | 주식회사 하이닉스반도체 | 반도체 소자의 금속배선 형성방법 |
US7326611B2 (en) * | 2005-02-03 | 2008-02-05 | Micron Technology, Inc. | DRAM arrays, vertical transistor structures and methods of forming transistor structures and DRAM arrays |
US7501676B2 (en) * | 2005-03-25 | 2009-03-10 | Micron Technology, Inc. | High density semiconductor memory |
US20140339568A1 (en) * | 2013-05-16 | 2014-11-20 | Sumitomo Electric Industries, Ltd. | Semiconductor device with substrate via hole and method to form the same |
US9012278B2 (en) * | 2013-10-03 | 2015-04-21 | Asm Ip Holding B.V. | Method of making a wire-based semiconductor device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0216741A (ja) * | 1988-07-04 | 1990-01-19 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH0563200A (ja) * | 1991-09-03 | 1993-03-12 | Canon Inc | 半導体装置 |
JPH0661493A (ja) * | 1992-06-17 | 1994-03-04 | Internatl Business Mach Corp <Ibm> | 垂直ゲート電界効果トランジスタおよびその製造方法 |
Family Cites Families (61)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3962713A (en) * | 1972-06-02 | 1976-06-08 | Texas Instruments Incorporated | Large value capacitor |
JPS5565463A (en) * | 1978-11-13 | 1980-05-16 | Semiconductor Res Found | Semiconductor device |
US4409608A (en) * | 1981-04-28 | 1983-10-11 | The United States Of America As Represented By The Secretary Of The Navy | Recessed interdigitated integrated capacitor |
US5357131A (en) | 1982-03-10 | 1994-10-18 | Hitachi, Ltd. | Semiconductor memory with trench capacitor |
JPS6070766A (ja) | 1983-09-26 | 1985-04-22 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JPH0793365B2 (ja) * | 1984-09-11 | 1995-10-09 | 株式会社東芝 | 半導体記憶装置およびその製造方法 |
JPS61144875A (ja) * | 1984-12-18 | 1986-07-02 | Mitsubishi Electric Corp | Mos集積回路 |
JPS61206253A (ja) * | 1985-03-11 | 1986-09-12 | Nec Corp | 半導体集積回路装置 |
US4614021A (en) * | 1985-03-29 | 1986-09-30 | Motorola, Inc. | Pillar via process |
US4864375A (en) * | 1986-02-05 | 1989-09-05 | Texas Instruments Incorporated | Dram cell and method |
JPS6340376A (ja) * | 1986-08-05 | 1988-02-20 | Mitsubishi Electric Corp | 電界効果型半導体装置 |
US5124764A (en) * | 1986-10-21 | 1992-06-23 | Texas Instruments Incorporated | Symmetric vertical MOS transistor with improved high voltage operation |
FR2610141B1 (fr) | 1987-01-26 | 1990-01-19 | Commissariat Energie Atomique | Circuit integre cmos et procede de fabrication de zones d'isolation electrique dans ce circuit |
US4906585A (en) | 1987-08-04 | 1990-03-06 | Siemens Aktiengesellschaft | Method for manufacturing wells for CMOS transistor circuits separated by insulating trenches |
JPH01125858A (ja) * | 1987-11-10 | 1989-05-18 | Fujitsu Ltd | 半導体装置およびその製造方法 |
US4982266A (en) * | 1987-12-23 | 1991-01-01 | Texas Instruments Incorporated | Integrated circuit with metal interconnecting layers above and below active circuitry |
US5016068A (en) * | 1988-04-15 | 1991-05-14 | Texas Instruments Incorporated | Vertical floating-gate transistor |
US4961100A (en) * | 1988-06-20 | 1990-10-02 | General Electric Company | Bidirectional field effect semiconductor device and circuit |
US4951102A (en) * | 1988-08-24 | 1990-08-21 | Harris Corporation | Trench gate VCMOS |
EP0472726A4 (en) * | 1989-05-12 | 1992-06-03 | Oki Electric Industry Company, Limited | Field effect transistor |
JPH0352192A (ja) | 1989-07-19 | 1991-03-06 | Hitachi Ltd | 半導体メモリ |
JPH03153085A (ja) * | 1989-11-10 | 1991-07-01 | Fujitsu Ltd | 半導体記憶装置及びその製造方法 |
US5010386A (en) * | 1989-12-26 | 1991-04-23 | Texas Instruments Incorporated | Insulator separated vertical CMOS |
JPH0775247B2 (ja) * | 1990-05-28 | 1995-08-09 | 株式会社東芝 | 半導体記憶装置 |
JPH0434980A (ja) * | 1990-05-30 | 1992-02-05 | Mitsubishi Electric Corp | 半導体装置 |
MY107475A (en) * | 1990-05-31 | 1995-12-30 | Canon Kk | Semiconductor device and method for producing the same. |
JP2790362B2 (ja) * | 1990-06-04 | 1998-08-27 | キヤノン株式会社 | 半導体装置 |
JP2932635B2 (ja) * | 1990-08-11 | 1999-08-09 | 日本電気株式会社 | 半導体記憶装置 |
JP2941039B2 (ja) * | 1990-11-08 | 1999-08-25 | 沖電気工業株式会社 | 半導体メモリ装置の製造方法 |
KR920010963A (ko) * | 1990-11-23 | 1992-06-27 | 오가 노리오 | Soi형 종채널 fet 및 그 제조방법 |
JP3019430B2 (ja) * | 1991-01-21 | 2000-03-13 | ソニー株式会社 | 半導体集積回路装置 |
JPH04239767A (ja) * | 1991-01-23 | 1992-08-27 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
US5057888A (en) | 1991-01-28 | 1991-10-15 | Micron Technology, Inc. | Double DRAM cell |
JPH04268767A (ja) * | 1991-02-25 | 1992-09-24 | Fujitsu Ltd | 半導体装置 |
JPH04360572A (ja) * | 1991-06-07 | 1992-12-14 | Ricoh Co Ltd | 半導体メモリ装置 |
US5355330A (en) * | 1991-08-29 | 1994-10-11 | Hitachi, Ltd. | Capacitive memory having a PN junction writing and tunneling through an insulator of a charge holding electrode |
KR960008518B1 (en) | 1991-10-02 | 1996-06-26 | Samsung Electronics Co Ltd | Manufacturing method and apparatus of semiconductor device |
JPH05121691A (ja) * | 1991-10-25 | 1993-05-18 | Nec Corp | 半導体記憶装置 |
JP2837014B2 (ja) * | 1992-02-17 | 1998-12-14 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
US5208172A (en) * | 1992-03-02 | 1993-05-04 | Motorola, Inc. | Method for forming a raised vertical transistor |
JP3322936B2 (ja) * | 1992-03-19 | 2002-09-09 | 株式会社東芝 | 半導体記憶装置 |
US5573837A (en) | 1992-04-22 | 1996-11-12 | Micron Technology, Inc. | Masking layer having narrow isolated spacings and the method for forming said masking layer and the method for forming narrow isolated trenches defined by said masking layer |
US5528062A (en) | 1992-06-17 | 1996-06-18 | International Business Machines Corporation | High-density DRAM structure on soi |
JP2748072B2 (ja) * | 1992-07-03 | 1998-05-06 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
US5340754A (en) * | 1992-09-02 | 1994-08-23 | Motorla, Inc. | Method for forming a transistor having a dynamic connection between a substrate and a channel region |
US5508541A (en) * | 1992-09-22 | 1996-04-16 | Kabushiki Kaisha Toshiba | Random access memory device with trench-type one-transistor memory cell structure |
JPH0721779A (ja) | 1993-07-07 | 1995-01-24 | Nec Corp | 半導体スタティックメモリ集積回路 |
DE4340967C1 (de) * | 1993-12-01 | 1994-10-27 | Siemens Ag | Verfahren zur Herstellung einer integrierten Schaltungsanordnung mit mindestens einem MOS-Transistor |
JP3253782B2 (ja) * | 1993-12-02 | 2002-02-04 | 株式会社東芝 | 半導体記憶装置 |
JPH07245343A (ja) * | 1994-03-03 | 1995-09-19 | Toshiba Corp | 半導体装置及びその製造方法 |
JP3745392B2 (ja) * | 1994-05-26 | 2006-02-15 | 株式会社ルネサステクノロジ | 半導体装置 |
US5432739A (en) | 1994-06-17 | 1995-07-11 | Philips Electronics North America Corporation | Non-volatile sidewall memory cell method of fabricating same |
US5529948A (en) * | 1994-07-18 | 1996-06-25 | United Microelectronics Corporation | LOCOS technology with reduced junction leakage |
JP3270250B2 (ja) * | 1994-08-17 | 2002-04-02 | 株式会社東芝 | 半導体記憶装置及びその製造方法 |
JP3400143B2 (ja) | 1994-09-17 | 2003-04-28 | 株式会社東芝 | 半導体記憶装置 |
US5480822A (en) * | 1994-11-28 | 1996-01-02 | United Microelectronics Corporation | Method of manufacture of semiconductor memory device with multiple, orthogonally disposed conductors |
US5455190A (en) | 1994-12-07 | 1995-10-03 | United Microelectronics Corporation | Method of making a vertical channel device using buried source techniques |
US5497017A (en) * | 1995-01-26 | 1996-03-05 | Micron Technology, Inc. | Dynamic random access memory array having a cross-point layout, tungsten digit lines buried in the substrate, and vertical access transistors |
US5705409A (en) * | 1995-09-28 | 1998-01-06 | Motorola Inc. | Method for forming trench transistor structure |
US5929476A (en) | 1996-06-21 | 1999-07-27 | Prall; Kirk | Semiconductor-on-insulator transistor and memory circuitry employing semiconductor-on-insulator transistors |
US5693547A (en) * | 1996-10-22 | 1997-12-02 | Advanced Micro Devices, Inc. | Method of making vertical MOSFET with sub-trench source contact |
-
1996
- 1996-06-21 US US08/668,388 patent/US5929476A/en not_active Expired - Lifetime
-
1997
- 1997-06-18 AU AU34929/97A patent/AU3492997A/en not_active Abandoned
- 1997-06-18 WO PCT/US1997/010591 patent/WO1997049134A2/en not_active Application Discontinuation
- 1997-06-18 EP EP97931250A patent/EP0907967A2/en not_active Ceased
- 1997-06-18 JP JP50331098A patent/JP3545768B2/ja not_active Expired - Fee Related
- 1997-06-18 KR KR10-2003-7012053A patent/KR100519127B1/ko not_active IP Right Cessation
- 1997-06-24 US US08/881,852 patent/US6586304B2/en not_active Expired - Lifetime
-
1999
- 1999-04-14 US US09/494,311 patent/US6459610B1/en not_active Expired - Lifetime
- 1999-05-20 US US09/315,900 patent/US6404008B1/en not_active Expired - Lifetime
-
2003
- 2003-09-17 JP JP2003324496A patent/JP2004104135A/ja active Pending
-
2008
- 2008-02-18 JP JP2008036383A patent/JP5476619B2/ja not_active Expired - Fee Related
-
2012
- 2012-03-02 JP JP2012046311A patent/JP5629872B2/ja not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0216741A (ja) * | 1988-07-04 | 1990-01-19 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH0563200A (ja) * | 1991-09-03 | 1993-03-12 | Canon Inc | 半導体装置 |
JPH0661493A (ja) * | 1992-06-17 | 1994-03-04 | Internatl Business Mach Corp <Ibm> | 垂直ゲート電界効果トランジスタおよびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US6586304B2 (en) | 2003-07-01 |
KR20040000407A (ko) | 2004-01-03 |
US6404008B1 (en) | 2002-06-11 |
US20020048883A1 (en) | 2002-04-25 |
JP5476619B2 (ja) | 2014-04-23 |
WO1997049134A2 (en) | 1997-12-24 |
US6459610B1 (en) | 2002-10-01 |
KR100519127B1 (ko) | 2005-10-04 |
US5929476A (en) | 1999-07-27 |
JP2004104135A (ja) | 2004-04-02 |
EP0907967A2 (en) | 1999-04-14 |
JP5629872B2 (ja) | 2014-11-26 |
JP3545768B2 (ja) | 2004-07-21 |
WO1997049134A3 (en) | 1998-03-12 |
AU3492997A (en) | 1998-01-07 |
JP2000513502A (ja) | 2000-10-10 |
JP2008124519A (ja) | 2008-05-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5629872B2 (ja) | Soi型トランジスタ | |
KR900000207B1 (ko) | 반도체 기억장치와 그 제조방법 | |
CN1173404C (zh) | 一种半导体装置及其形成方法 | |
US5376575A (en) | Method of making dynamic random access memory having a vertical transistor | |
US6794238B2 (en) | Process for forming metallized contacts to periphery transistors | |
KR100404829B1 (ko) | 다중의 단일화된 플러그에서 개선된 정렬 톨러런스를 위한방법 및 구조 | |
US5492851A (en) | Method for fabricating attached capacitor cells in a semiconductor device having a thin film transistor | |
KR19980064222A (ko) | 수직 트랜지스터 및 트렌치 캐패시터를 포함하는 메모리 셀 | |
KR0128826B1 (ko) | 디램셀 제조방법 | |
JP2000164833A (ja) | メモリセル及びメモリセルを形成するための方法 | |
US6211007B1 (en) | Process for enhancing refresh in dynamic random access memory devices | |
KR100545144B1 (ko) | 감소된시트저항을가지는신뢰할수있는폴리사이드게이트스택 | |
US5216267A (en) | Stacked capacitor dynamic random access memory with a sloped lower electrode | |
KR0140044B1 (ko) | 메모리 셀중에 절연 구조를 가지는 반도체 메모리 소자 | |
US6590249B2 (en) | One-transistor memory cell configuration and method for its fabrication | |
GB2233154A (en) | Manufacturing a DRAM cell semi-conductor device | |
KR100353470B1 (ko) | 반도체소자의 제조방법 | |
US5248891A (en) | High integration semiconductor device | |
KR970000227B1 (ko) | 반도체 메모리 장치 및 그 제조방법 | |
KR100487255B1 (ko) | Soi-트랜지스터,그트랜지스터게이트어레이및soi-트랜지스터형성방법 | |
KR19990005921A (ko) | 반도체 메모리 장치 및 그 제조 방법 | |
JP2723802B2 (ja) | 半導体装置及びその製造方法 | |
KR0139834B1 (ko) | 트렌치형 1-트랜지스터 메모리셀구조를 갖춘 mos랜덤 억세스 메모리 | |
KR920001175B1 (ko) | 반도체 랜덤 액세스 메모리 쎌의 제조방법 | |
KR100272655B1 (ko) | 반도체 메모리 소자 및 그 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130913 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130924 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20131206 Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20131206 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140408 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140605 Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20140605 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140819 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20140905 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20140905 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20140905 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140905 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5629872 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
EXPY | Cancellation because of completion of term |