CN1173404C - 一种半导体装置及其形成方法 - Google Patents

一种半导体装置及其形成方法 Download PDF

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CN1173404C
CN1173404C CNB011412267A CN01141226A CN1173404C CN 1173404 C CN1173404 C CN 1173404C CN B011412267 A CNB011412267 A CN B011412267A CN 01141226 A CN01141226 A CN 01141226A CN 1173404 C CN1173404 C CN 1173404C
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ղķ˹W�����½�ɭ
詹姆斯W·阿德金森
拉马查德拉
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迪瓦卡路尼
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杰夫瑞P·加姆比诺
杰克A·曼德尔曼
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0387—Making the trench

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Abstract

本发明提出一种半导体器件，其针对一种埋置DRAM和逻辑器件的形成方法，其中DRAM器件形成在块体单晶半导体区域中，逻辑器件形成在绝缘体上硅(“SOI”)区域中，并在隐埋处，掺杂玻璃被用作掩模以形成深沟道用于在块体区域中的存储。并且也公开了由此产生的结构。

Description

一种半导体装置及其形成方法
技术领域
本发明总体涉及半导体器件领域，并且特别涉及具有块体半导体区域和绝缘体上硅(“SOI”)区域的半导体衬底。该半导体衬底还包含埋置动态随机存取存储器(“DRAM”)和逻辑器件，其中DRAM器件已形成在块体区域中，逻辑器件已形成在SOI区域中，并且掺杂多晶硅被用作掩模以在块体区域中形成隔离和/或存储沟道。本发明也提供一种形成所述结构的方法。
背景技术
动态随机存取存储器，或DRAM是一种半导体存储器，其中信息作为数据位被存储在金属氧化物半导体(“MOS”)集成电路上的电容器中。每位通常以一定量的电荷被存储在由电容器和晶体管组成的存储单元中。由于电荷泄露，电容器逐步放电并且存储单元可丢失信息。因此，为了保存信息，存储器必须定期刷新。尽管有这些不便，但由于它的高密度和由此产生的低价格，DRAM是非常通用的存储器技术。
通过将p-型或n-型材料阱植入到任一类型材料的晶片中，常规半导体DRAM器件形成在块体半导体衬底材料中。然后使用公知的方法制作栅和源/漏扩散。这些可形成被称为金属氧化物半导体场效应晶体管或MOSFET的器件。当特定的芯片使用p-型材料和n-型半导体时，它被称为互补金属氧化物半导体(“CMOS”)芯片。为了避免电路的电短路，这些类型的器件中的每一个必须和其他的器件相互电绝缘。对于各种FET来说，需要相对较大的表面面积，这在当前的总尺寸减小和较大集成的趋势中是不希望出现的。另外，由于源和/漏扩散的物理近似于其他的FET和近似于块体衬底，可出现寄生通路和结电容问题。当试图减小电路至较大电路密度所需的尺寸时，这些问题更加频繁出现。
绝缘体上硅(“SOI”)技术已逐渐用于解决这些问题。然而，SOI遭遇到自热，静电放电敏感性，低击穿电压，和动态漂移体效应问题，进而出现对通门(passgate)器件和需要紧密临界电压控制的器件的问题。所谓的“漂移体效应”在器件体未连接到固定的电位时发生，因此，器件将根据器件的历史承担电荷。漂移体效应显著影响器件的可靠性。
一些类型的半导体存储器对漂移体效应比较敏感。例如，在动态随机存取存储器(“DRAM”)中，信息被存储在MOS电路中的电容器中。因此，在DRAM中，漂移体效应是特别不利的，这是因为相关晶体管保持在“关闭”状态以阻止电荷从存储电容器中泄露是关键的。
由于SOI的一个特别目的是减小结电容，SOI的另一个特别问题是大值电容的形成(例如，用于去耦应用)是非常困难的。由于相对于块体技术SOI扩散电容是小的，使用扩散以得到去耦电容对于SOI是不实际的。
因此，需要把高性能支持器件的SOI区域和低漏存储器阵列的相邻块体器件结合在一起。
发明内容
本发明公开一种块体/SOI混合半导体衬底，其包含埋置动态随机存取存储器(“DRAM”)和逻辑器件，其中DRAM器件已形成在块体区域中，并且逻辑器件形成在SOI区域中，掺杂多晶硅被用作掩模以在块体区域中形成隔离和/或存储沟道。本发明也提供一种形成所述结构的方法。
本发明提供一种半导体装置，包括：
(a)具有基本为平面表面的包含单晶块体区域的单晶衬底，其特征为单晶块体区域具有第一导电类型；
(b)该平面表面的第一部分，所述第一部分具有第一周边，该第一周边限定了所述半导体装置的绝缘体上硅区域，所述绝缘体上硅区域与所述单晶块体区域相邻；
(c)该平面表面的第二部分，所述第二部分具有第二周边，该第二周边限定了所述半导体装置的单晶块体区域的器件部分，其中所述第二部分与所述第一部分可形成不同类型的半导体器件；
(d)形成在所述绝缘体上硅区域中的埋置的逻辑器件；
(e)形成在所述单晶块体区域的器件部分中的埋置的存储器件；和
(f)形成在所述单晶块体区域的器件部分中的由掺杂多晶硅填充的存储沟道，其中所述存储沟道延伸到所述单晶块体区域的一个掺杂部分中，所述单晶块体区域的所述掺杂部分的特征在于具有第二导电类型，其中第二导电类型与第一导电类型不同，并且所述存储沟道通过所述单晶块体区域的所述掺杂部分与所述单晶块体区域的其余部分隔开。
根据本发明的上述半导体装置，其中该单晶衬底为硅晶片。
根据本发明的上述半导体装置，其中所述沟道由埋置的氧化物掩模形成。
根据本发明的上述半导体装置，其中形成在单晶块体区域中的埋置的存储器件为动态随机存取存储器器件。
根据本发明的上述半导体装置，其中在绝缘体上硅区域中的沟道形成浅沟道隔离区域。
根据本发明的上述半导体装置，还包括导电地连接于：位线和局部互联；以及外部互联。
根据本发明的上述半导体装置，其中所述单晶块体区域具有与所述平面表面基本相同的晶体结构，该半导体装置还包括构造在单晶块体区域的器件部分中的器件阵列；连接每个器件的电触点；以及沉积在该平面表面的第一部分上的绝缘材料。
根据本发明的上述半导体装置，其中该单晶衬底为硅晶片。
根据本发明的上述半导体装置，其中每个深沟道被一个套环所限界。
根据本发明的上述半导体装置，其中该套环为二氧化硅套环。
根据本发明的上述半导体装置，其中通过掺杂多晶硅从所述深沟道的扩散，邻近所述套环形成节点电介质。
根据本发明的上述半导体装置，其中形成在单晶块体区域中的埋置的存储器件为动态随机存取存储器器件。
根据本发明的上述半导体装置，其中动态随机存取存储器器件形成阵列。
根据本发明的上述半导体装置，其中绝缘材料为硼磷硅酸盐玻璃。
根据本发明的上述半导体装置，其中绝缘体上硅区域直接接触单晶块体区域。
本发明还公开一种半导体装置的形成方法，包括以下步骤：提供具有基本为平面表面的单晶衬底；在所述平面表面的第一表面区域上形成绝缘体上硅区域；在所述平面表面的第二表面区域上形成单晶块体区域；在所述绝缘体上硅区域中形成埋置逻辑器件；在所述单晶块体区域中形成埋置存储器件；和在单晶块体区域中形成沟道。
附图说明
为了理解本发明，应当联系附图，参考下面的详细描述，其中：
图1是在执行本发明方法中的第一步骤的横截面示意图；
图2是在执行本发明方法中的第二步骤的横截面示意图；
图3是在执行本发明方法中的第三步骤的横截面示意图；
图4是在执行本发明方法中的第四步骤的横截面示意图；
图5是在执行本发明方法中的第五步骤的横截面示意图；
图6是在执行本发明方法中的第六步骤的横截面示意图；
图7是在执行本发明方法中的第七步骤的横截面示意图；
图8是在执行本发明方法中的第八和最终步骤的横截面示意图。
具体实施方式
本发明公开一种在绝缘体上硅衬底上制作埋置DRAM阵列的方法，和由此产生的装置。
参考图1，提供一种标准的绝缘体上硅(“SOI”)衬底。标准SOI是具有基本为平面的上表面的单晶半导体衬底10，其包括绝缘氧化层14和在平面表面上第一表面区域上的薄半导体层16，和晶体块体区域12。晶体块体区域12是基本具有与平面表面相同的晶体结构的单晶区域。绝缘氧化层14典型为氧化硅。晶体块体区域12为单晶半导体材料，通常为硅。可以以许多不同的方法制作衬底，包括：硅被注入氧(“SIMOX”)，其中块体晶片被高能注入大剂量的氧；接合与深腐蚀(“BE-SOI”)，其中两个块体晶片具有生长在一个表面上的氧化物，并且在其中一个晶片上包括掺杂物分布以作为标记层，这两个氧化物表面被接合在一起，然后一个晶片被深腐蚀到标记掺杂层；或者一种被称作“Smart cut”的方法，其中一个晶片在第一晶片被接合到第二晶片之前被注入氢，然后这两个晶片接合在一起，并且使用硅结构的氢，一个晶片中的多余硅被脱落，以引起合适程度的裂化；或应用其他合适的制作SOI的方法。
一旦已形成SOI衬底，典型地在大约5nm至大约10nm范围的二氧化硅的薄垫氧化物层18(看图2)，被沉积或生长在硅的薄层上。一个抛光阻止层，在该情况下为氮化硅层20，典型为大约100nm厚，被沉积在薄垫氧化物层18上。
如图3所示，晶体块体区域12被分成两个区域：将变成DRAM阵列24的晶体块体区域的第一部分，和将变成SOI区域26的第二部分，第二部分将包含支持高性能逻辑CMOS器件。使用常规处理技术，DRAM阵列24的一部分进一步加工成深沟道隔离区域。深沟道隔离区域被刻划成一阵列，其中DRAM器件将最终存在于此。
深沟道形成方法以除去垫料薄膜层(即垫料氧化物层18，氮化硅层20)，和SOI层16开始。使用已知的技术，p-型阱81形成在扩散区域43中(图4)。接下来，硼硅酸盐玻璃(“BSG”)层(未示出)被用来形成深沟道32的图案。BSG是平面化的，在DRAM阵列的边缘平滑250nm步幅(step)，使得容易执行用于刻划深沟道32图案的光刻。使用常规方法形成深沟道开口22，其延伸穿过BSG层和氧化物层14，并且进入到晶体块体区域12中。典型地通过光刻限定使用光致抗蚀剂材料(未示出)的区域然后蚀刻限定区域，形成这些沟道32。被蚀刻的材料通过BSG层和隐埋氧化物(“BOX”)层14，并且蚀刻停止在晶体块体区域12顶部。这些开口将在DRAM产品等中形成阵列块。由于BSG层和绝缘层14之间的湿蚀刻选择性，在BSG层被剥离掉后，二氧化硅的绝缘层14作为隐埋氧化物层14保留。
每个深沟道32装配有套环(collar)30。每个套环30由绝缘二氧化硅材料做成。形成套环后，通过将砷(As)或磷(P)扩散到每个深沟道的底部形成n+隐埋板76b。在沟道中形成二氧化硅(SiO2)，氮化硅(SiN)，或氮氧化硅(SiON)的薄节点电介质(例如，2至10nm)。这是用于沟道电容器的电介质。
如图4所示，接下来执行DRAM阵列24中的存储电容器的剩余部分和垂直栅的形成。所有的深沟道32用掺杂多晶硅45填充，该多晶硅用作沟道电容器的内电极。然后在每个深沟道32中的掺杂多晶硅45层被凹进。套环的上部被用湿蚀刻除去(例如，使用氢氟酸(HF))，形成掺杂多晶硅45和晶体块体区域12之间的套带连接，沟道顶部氧化物(“TTO”)层40被沉积在每个凹进的掺杂多晶硅层45上。栅氧化物被引入到DRAM阵列24中的每个扩散区域43中以形成阵列栅42。在下一步，多晶硅阵列栅导体区域44被沉积在每个深沟道32上，并且使用已知的蚀刻方法将它们的表面凹进。在DRAM阵列24的别处，BOX层14覆盖每个扩散区域43。在各种氧化步骤中，氮氧化硅(SiON)层46可生长在氮化物抛光停止层20的上表面上。在各种沉积和蚀刻步骤中，垂直的氮化物或多晶硅间隔47可建立在DRAM阵列24和块体区域26之间。
接下来，定义DRAM阵列中的有效面积。参考图5，应用常规的光刻和蚀刻技术以在DRAM阵列24中的某些扩散区域43中限定浅隔离沟道52。典型为二氧化硅的填充材料54被沉积在浅沟道52中。使用标准方法(即化学机械抛光(“CMP”))平面化填充的浅沟道52的表面。接下来，填充的浅沟道52的表面被再次凹进或深蚀刻，以露出DRAM阵列区域24中的栅多晶硅44。
在另一实施方案中，浅沟道隔离可同时形成在逻辑区域中。在DRAM阵列中的氧化物凹进蚀刻步骤中，这个方法需要额外的阻断掩模以保护逻辑区域中的浅沟道隔离。然而，这个步骤避免了在逻辑区域中使用额外的掩模以形成浅沟道隔离图案的需要。
现在看形成字线导线60的步骤。字线导线60是地址线或数据线，其在减小芯片的全部针数上是有用的，从而有助于实现小型化。参考图6，以横截面图示出了多硅化(polycide)栅叠层67，其代表字线导线60的一部分。沉积一层掺杂多晶硅62，随后沉积硅化钨(“WSi2”)层68和氮化硅(“SiN”)层64而构造多硅化栅叠层67。另一方法，任何其他的耐火的金属硅化物可取代硅化钨。在多晶硅层62上的钨(即金属)的硅化物层68的结合产生被称作多硅化层65的复合层。使用已知的光刻技术和反应离子刻蚀(“RIE”)形成这些层65，66的图案，以限定多硅化栅叠层67。然后，氮化硅间隔69被形成在形成字线60的多硅化栅叠层67的侧面上。
如图7和8所示，BOX层14被从选择的扩散区域43中除去。浅n-型扩散83a，83b形成在较深的p-型阱81中。通过n-型(例如，砷，磷)掺杂剂从沟道多晶硅45中向外扩散而形成节点扩散。这些p-和n-型区域形成DRAM阵列MOSFET中的必需元件，包括位线扩散83a，节点扩散83b，和传输器件通道81a。
然后，通过在整个DRAM阵列区域24上最初沉积氮化硅层72形成与DRAM阵列24的触点70(图7)。接下来，硼磷硅酸盐玻璃(“BPSG”)层74被沉积在DRAM阵列区域24上。然后用化学机械抛光(“CMP”)步骤将BPSG层74抛平。现在可形成阵列触点70，其提供到扩散区域43的电联通。使用已知的光刻和反应离子刻蚀(“RIE”)技术形成阵列触点开孔。然后沉积掺杂的多晶硅层并通过CMP形成图案，形成阵列触点70。
现在转向衬底10的SOI区域26，并参考图8，典型逻辑器件82的形成始于在SOI区域26中形成浅沟道隔离80。浅沟道隔离80用二氧化硅层81填充。P-型硅阱84形成在一些剩余的硅岛中。栅多晶硅叠层87也形成在p-型硅阱84上。栅多晶硅叠层87进一步被绝缘间隔89限界。将n-型掺杂剂引入到硅中在p-型硅阱84中形成扩散结86。将p-型掺杂剂引入到硅中在n-型硅阱中也形成扩散结。最后，栅多晶硅叠层87和扩散86被硅化物层85覆盖，诸如硅化钴(CoSi2)。
制作的最后步骤，在此没有图示，包括常规结束步骤，诸如沉积氮化硅层，磷硅酸盐玻璃(“PSG”)层和平面化；形成连接到逻辑区域中的栅和扩散区的，以及连接到DRAM阵列中的阵列触点的金属(例如，钨)接线柱；可能用双镶嵌方法形成的位线和局部互联；和形成任何剩余的必需互联。
尽管为了说明的目的在此描述了本发明的实施方案，本领域中的技术人员将明白很多的修改和变化。因此，附加的权利要求书意在包括所有任何的属于本发明真正精神和范围中的修改和变化。

Claims (15)

1.一种半导体装置，包括：
(a)具有基本为平面表面的包含单晶块体区域的单晶衬底，其特征为单晶块体区域具有第一导电类型；
(b)该平面表面的第一部分，所述第一部分具有第一周边，该第一周边限定了所述半导体装置的绝缘体上硅区域，所述绝缘体上硅区域与所述单晶块体区域相邻；
(c)该平面表面的第二部分，所述第二部分具有第二周边，该第二周边限定了所述半导体装置的单晶块体区域的器件部分，其中所述第二部分与所述第一部分可形成不同类型的半导体器件；
(d)形成在所述绝缘体上硅区域中的埋置的逻辑器件；
(e)形成在所述单晶块体区域的器件部分中的埋置的存储器件；和
(f)形成在所述单晶块体区域的器件部分中的由掺杂多晶硅填充的存储沟道，其中所述存储沟道延伸到所述单晶块体区域的一个掺杂部分中，所述单晶块体区域的所述掺杂部分的特征在于具有第二导电类型，其中第二导电类型与第一导电类型不同，并且所述存储沟道通过所述单晶块体区域的所述掺杂部分与所述单晶块体区域的其余部分隔开。
2.如权利要求1的半导体装置，其中该单晶衬底为硅晶片。
3.如权利要求1的半导体装置，其中所述沟道由埋置的氧化物掩模形成。
4.如权利要求1的半导体装置，其中形成在单晶块体区域中的埋置的存储器件为动态随机存取存储器器件。
5.如权利要求1的半导体装置，其中在绝缘体上硅区域中的沟道形成浅沟道隔离区域。
6.如权利要求1的半导体装置，还包括导电地连接于：
位线和局部互联；以及
外部互联。
7.如权利要求1的半导体装置，其中所述单晶块体区域具有与所述平面表面基本相同的晶体结构，该半导体装置还包括
构造在单晶块体区域的器件部分中的器件阵列；
连接每个器件的电触点；以及
沉积在该平面表面的第一部分上的绝缘材料。
8.如权利要求7的半导体装置，其中该单晶衬底为硅晶片。
9.如权利要求7的半导体装置，其中每个深沟道被一个套环所限界。
10.如权利要求9的半导体装置，其中该套环为二氧化硅套环。
11.如权利要求9的半导体装置，其中通过掺杂多晶硅从所述深沟道的扩散，邻近所述套环形成节点电介质。
12.如权利要求7的半导体装置，其中形成在单晶块体区域中的埋置的存储器件为动态随机存取存储器器件。
13.如权利要求12的半导体装置，其中动态随机存取存储器器件形成阵列。
14.如权利要求7的半导体装置，其中绝缘材料为硼磷硅酸盐玻璃。
15.如权利要求7的半导体装置，其中绝缘体上硅区域直接接触单晶块体区域。
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KR100458772B1 (ko) 2004-12-03
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US6350653B1 (en) 2002-02-26
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