JP2010520571A - フラッシュメモリ向け部分ブロック消去アーキテクチャ - Google Patents

フラッシュメモリ向け部分ブロック消去アーキテクチャ Download PDF

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Publication number
JP2010520571A
JP2010520571A JP2009552034A JP2009552034A JP2010520571A JP 2010520571 A JP2010520571 A JP 2010520571A JP 2009552034 A JP2009552034 A JP 2009552034A JP 2009552034 A JP2009552034 A JP 2009552034A JP 2010520571 A JP2010520571 A JP 2010520571A
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block
sub
word line
flash memory
voltage
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Pending
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JP2009552034A
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English (en)
Japanese (ja)
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JP2010520571A5 (enExample
Inventor
ジン−キ・キム
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Mosaid Technologies Inc
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Conversant Intellectual Property Management Inc
Mosaid Technologies Inc
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Publication of JP2010520571A publication Critical patent/JP2010520571A/ja
Publication of JP2010520571A5 publication Critical patent/JP2010520571A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
JP2009552034A 2007-03-07 2008-03-04 フラッシュメモリ向け部分ブロック消去アーキテクチャ Pending JP2010520571A (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US89343207P 2007-03-07 2007-03-07
US91484907P 2007-04-30 2007-04-30
US11/779,685 US7804718B2 (en) 2007-03-07 2007-07-18 Partial block erase architecture for flash memory
PCT/CA2008/000411 WO2008106778A1 (en) 2007-03-07 2008-03-04 Partial block erase architecture for flash memory

Related Child Applications (1)

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JP2013078709A Division JP5633890B2 (ja) 2007-03-07 2013-04-04 フラッシュメモリ向け部分ブロック消去アーキテクチャ

Publications (2)

Publication Number Publication Date
JP2010520571A true JP2010520571A (ja) 2010-06-10
JP2010520571A5 JP2010520571A5 (enExample) 2010-07-22

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Family Applications (3)

Application Number Title Priority Date Filing Date
JP2009552034A Pending JP2010520571A (ja) 2007-03-07 2008-03-04 フラッシュメモリ向け部分ブロック消去アーキテクチャ
JP2013078709A Expired - Fee Related JP5633890B2 (ja) 2007-03-07 2013-04-04 フラッシュメモリ向け部分ブロック消去アーキテクチャ
JP2014163661A Pending JP2014241185A (ja) 2007-03-07 2014-08-11 フラッシュメモリ向け部分ブロック消去アーキテクチャ

Family Applications After (2)

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JP2013078709A Expired - Fee Related JP5633890B2 (ja) 2007-03-07 2013-04-04 フラッシュメモリ向け部分ブロック消去アーキテクチャ
JP2014163661A Pending JP2014241185A (ja) 2007-03-07 2014-08-11 フラッシュメモリ向け部分ブロック消去アーキテクチャ

Country Status (8)

Country Link
US (3) US7804718B2 (enExample)
EP (2) EP2135253A4 (enExample)
JP (3) JP2010520571A (enExample)
KR (1) KR101460826B1 (enExample)
CN (1) CN101681677A (enExample)
CA (1) CA2678886A1 (enExample)
TW (1) TWI457939B (enExample)
WO (1) WO2008106778A1 (enExample)

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JP2012181890A (ja) * 2011-03-01 2012-09-20 Toshiba Corp 不揮発性半導体記憶装置
JP2015536521A (ja) * 2012-10-26 2015-12-21 マイクロン テクノロジー， インク． 部分的なページメモリ動作
JP5943153B2 (ja) * 2014-05-16 2016-06-29 富士通株式会社 情報処理装置、書き込み制御回路、書き込み制御方法、及び書き込み制御プログラム
US10170189B2 (en) 2011-08-15 2019-01-01 Micron Technology, Inc. Apparatus and methods including source gates
US10541029B2 (en) 2012-08-01 2020-01-21 Micron Technology, Inc. Partial block memory operations

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