JP2009545884A5 - - Google Patents

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JP2009545884A5
JP2009545884A5 JP2009522826A JP2009522826A JP2009545884A5 JP 2009545884 A5 JP2009545884 A5 JP 2009545884A5 JP 2009522826 A JP2009522826 A JP 2009522826A JP 2009522826 A JP2009522826 A JP 2009522826A JP 2009545884 A5 JP2009545884 A5 JP 2009545884A5
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substrate
heating
dichlorosilane
silane
temperature less
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JP2009522826A
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JP2009545884A (ja
JP5175285B2 (ja
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Priority claimed from PCT/US2007/017053 external-priority patent/WO2008033186A1/en
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JP2009522826A 2006-07-31 2007-07-30 エピタキシャル層形成中の形態制御方法 Expired - Fee Related JP5175285B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US82095606P 2006-07-31 2006-07-31
US60/820,956 2006-07-31
PCT/US2007/017053 WO2008033186A1 (en) 2006-07-31 2007-07-30 Methods of controlling morphology during epitaxial layer formation

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JP2009545884A JP2009545884A (ja) 2009-12-24
JP2009545884A5 true JP2009545884A5 (enExample) 2010-09-02
JP5175285B2 JP5175285B2 (ja) 2013-04-03

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US (1) US7588980B2 (enExample)
JP (1) JP5175285B2 (enExample)
KR (1) KR101369355B1 (enExample)
CN (1) CN101496150B (enExample)
DE (1) DE112007001813T5 (enExample)
TW (1) TWI390606B (enExample)
WO (1) WO2008033186A1 (enExample)

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CN103779278A (zh) * 2012-10-22 2014-05-07 中芯国际集成电路制造(上海)有限公司 Cmos管的形成方法
JP5931780B2 (ja) * 2013-03-06 2016-06-08 東京エレクトロン株式会社 選択エピタキシャル成長法および成膜装置
KR102422158B1 (ko) 2015-12-23 2022-07-20 에스케이하이닉스 주식회사 반도체장치 및 그 제조 방법
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