JP2009044160A5 - - Google Patents

Download PDF

Info

Publication number
JP2009044160A5
JP2009044160A5 JP2008206689A JP2008206689A JP2009044160A5 JP 2009044160 A5 JP2009044160 A5 JP 2009044160A5 JP 2008206689 A JP2008206689 A JP 2008206689A JP 2008206689 A JP2008206689 A JP 2008206689A JP 2009044160 A5 JP2009044160 A5 JP 2009044160A5
Authority
JP
Japan
Prior art keywords
semiconductor chip
sealing portion
conductive
pad
embedded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008206689A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009044160A (ja
JP5470510B2 (ja
Filing date
Publication date
Priority claimed from KR1020070080595A external-priority patent/KR100885924B1/ko
Application filed filed Critical
Publication of JP2009044160A publication Critical patent/JP2009044160A/ja
Publication of JP2009044160A5 publication Critical patent/JP2009044160A5/ja
Application granted granted Critical
Publication of JP5470510B2 publication Critical patent/JP5470510B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2008206689A 2007-08-10 2008-08-11 埋め込まれた導電性ポストを備える半導体パッケージ Active JP5470510B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2007-0080595 2007-08-10
KR1020070080595A KR100885924B1 (ko) 2007-08-10 2007-08-10 묻혀진 도전성 포스트를 포함하는 반도체 패키지 및 그제조방법
US12/104,333 2008-04-16
US12/104,333 US8093703B2 (en) 2007-08-10 2008-04-16 Semiconductor package having buried post in encapsulant and method of manufacturing the same

Publications (3)

Publication Number Publication Date
JP2009044160A JP2009044160A (ja) 2009-02-26
JP2009044160A5 true JP2009044160A5 (enExample) 2011-10-06
JP5470510B2 JP5470510B2 (ja) 2014-04-16

Family

ID=40345696

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008206689A Active JP5470510B2 (ja) 2007-08-10 2008-08-11 埋め込まれた導電性ポストを備える半導体パッケージ

Country Status (5)

Country Link
US (2) US8093703B2 (enExample)
JP (1) JP5470510B2 (enExample)
KR (1) KR100885924B1 (enExample)
CN (1) CN101364579B (enExample)
TW (1) TWI438883B (enExample)

Families Citing this family (85)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US7791199B2 (en) 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
JP5584474B2 (ja) 2007-03-05 2014-09-03 インヴェンサス・コーポレイション 貫通ビアによって前面接点に接続された後面接点を有するチップ
US8193615B2 (en) 2007-07-31 2012-06-05 DigitalOptics Corporation Europe Limited Semiconductor packaging process using through silicon vias
US20090212381A1 (en) * 2008-02-26 2009-08-27 Tessera, Inc. Wafer level packages for rear-face illuminated solid state image sensors
US20100053407A1 (en) * 2008-02-26 2010-03-04 Tessera, Inc. Wafer level compliant packages for rear-face illuminated solid state image sensors
US7964450B2 (en) * 2008-05-23 2011-06-21 Stats Chippac, Ltd. Wirebondless wafer level package with plated bumps and interconnects
US20110073357A1 (en) * 2008-06-02 2011-03-31 Nxp B.V. Electronic device and method of manufacturing an electronic device
US7855439B2 (en) * 2008-08-28 2010-12-21 Fairchild Semiconductor Corporation Molded ultra thin semiconductor die packages, systems using the same, and methods of making the same
US8704350B2 (en) * 2008-11-13 2014-04-22 Samsung Electro-Mechanics Co., Ltd. Stacked wafer level package and method of manufacturing the same
US8183677B2 (en) * 2008-11-26 2012-05-22 Infineon Technologies Ag Device including a semiconductor chip
US8008125B2 (en) * 2009-03-06 2011-08-30 General Electric Company System and method for stacked die embedded chip build-up
TWI446498B (zh) * 2009-03-13 2014-07-21 泰斯拉公司 具有延伸穿越銲墊之通孔的堆疊微電子總成
US8258010B2 (en) * 2009-03-17 2012-09-04 Stats Chippac, Ltd. Making a semiconductor device having conductive through organic vias
US8026608B2 (en) 2009-03-24 2011-09-27 General Electric Company Stackable electronic package
JP5330065B2 (ja) 2009-04-13 2013-10-30 新光電気工業株式会社 電子装置及びその製造方法
TWI405306B (zh) * 2009-07-23 2013-08-11 日月光半導體製造股份有限公司 半導體封裝件、其製造方法及重佈晶片封膠體
US8367470B2 (en) * 2009-08-07 2013-02-05 Stats Chippac, Ltd. Semiconductor device and method of forming cavity in build-up interconnect structure for short signal path between die
EP2302403A1 (en) * 2009-09-28 2011-03-30 Imec Method and device for testing TSVs in a 3D chip stack
US20110084372A1 (en) * 2009-10-14 2011-04-14 Advanced Semiconductor Engineering, Inc. Package carrier, semiconductor package, and process for fabricating same
TWI497679B (zh) * 2009-11-27 2015-08-21 日月光半導體製造股份有限公司 半導體封裝件及其製造方法
US8569894B2 (en) * 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8372689B2 (en) * 2010-01-21 2013-02-12 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof
TWI411075B (zh) 2010-03-22 2013-10-01 日月光半導體製造股份有限公司 半導體封裝件及其製造方法
US8759209B2 (en) 2010-03-25 2014-06-24 Stats Chippac, Ltd. Semiconductor device and method of forming a dual UBM structure for lead free bump connections
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
CN102244972A (zh) * 2010-04-08 2011-11-16 王忠诚 电路板及其应用
US8421210B2 (en) 2010-05-24 2013-04-16 Stats Chippac Ltd. Integrated circuit packaging system with dual side connection and method of manufacture thereof
US8987878B2 (en) * 2010-10-29 2015-03-24 Alpha And Omega Semiconductor Incorporated Substrateless power device packages
US9620455B2 (en) * 2010-06-24 2017-04-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming anisotropic conductive film between semiconductor die and build-up interconnect structure
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8193610B2 (en) * 2010-08-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming B-stage conductive polymer over contact pads of semiconductor die in Fo-WLCSP
TWI426587B (zh) * 2010-08-12 2014-02-11 矽品精密工業股份有限公司 晶片尺寸封裝件及其製法
KR101695352B1 (ko) * 2010-08-12 2017-01-12 삼성전자 주식회사 리드 프레임 및 이를 갖는 반도체 패키지
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
JP2012099648A (ja) * 2010-11-02 2012-05-24 Fujitsu Semiconductor Ltd 半導体装置とその製造方法
US8941222B2 (en) 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
KR101059490B1 (ko) 2010-11-15 2011-08-25 테세라 리써치 엘엘씨 임베드된 트레이스에 의해 구성된 전도성 패드
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US8736065B2 (en) 2010-12-22 2014-05-27 Intel Corporation Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same
KR20120091694A (ko) * 2011-02-09 2012-08-20 삼성전자주식회사 반도체 패키지
TWI462201B (zh) * 2011-03-04 2014-11-21 群成科技股份有限公司 半導體封裝結構及其製造方法
US8461691B2 (en) * 2011-04-29 2013-06-11 Infineon Technologies Ag Chip-packaging module for a chip and a method for forming a chip-packaging module
US8288209B1 (en) * 2011-06-03 2012-10-16 Stats Chippac, Ltd. Semiconductor device and method of using leadframe bodies to form openings through encapsulant for vertical interconnect of semiconductor die
US9123763B2 (en) 2011-10-12 2015-09-01 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) structure having at least one package comprising one die being disposed in a core material between first and second surfaces of the core material
US8975741B2 (en) 2011-10-17 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Process for forming package-on-package structures
JP5870626B2 (ja) * 2011-11-01 2016-03-01 富士通株式会社 半導体装置及び半導体装置の製造方法
EP2613349B1 (en) 2012-01-05 2019-11-20 Nxp B.V. Semiconductor package with improved thermal properties
US8658473B2 (en) 2012-03-27 2014-02-25 General Electric Company Ultrathin buried die module and method of manufacturing thereof
KR101985236B1 (ko) 2012-07-10 2019-06-03 삼성전자주식회사 멀티-칩 패키지 및 그의 제조 방법
US8963336B2 (en) 2012-08-03 2015-02-24 Samsung Electronics Co., Ltd. Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same
KR101970291B1 (ko) * 2012-08-03 2019-04-18 삼성전자주식회사 반도체 패키지의 제조 방법
US9496211B2 (en) * 2012-11-21 2016-11-15 Intel Corporation Logic die and other components embedded in build-up layers
US9293404B2 (en) * 2013-01-23 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Pre-applying supporting materials between bonded package components
US9379041B2 (en) 2013-12-11 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fan out package structure
US9184128B2 (en) * 2013-12-13 2015-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC package and methods of forming the same
CN103681372B (zh) * 2013-12-26 2016-07-06 华进半导体封装先导技术研发中心有限公司 扇出型圆片级三维半导体芯片的封装方法
MY171261A (en) * 2014-02-19 2019-10-07 Carsem M Sdn Bhd Stacked electronic packages
US9527723B2 (en) 2014-03-13 2016-12-27 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming microelectromechanical systems (MEMS) package
JP6317629B2 (ja) * 2014-06-02 2018-04-25 株式会社東芝 半導体装置
JP6318016B2 (ja) * 2014-06-10 2018-04-25 株式会社ディスコ 積層デバイスの製造方法
US10257937B2 (en) * 2014-07-07 2019-04-09 Infineon Technologies Austria Ag Device for electrically coupling a plurality of semiconductor device layers by a common conductive layer
CN106158772B (zh) * 2015-03-27 2018-12-18 蔡亲佳 板级嵌入式封装结构及其制作方法
US9576918B2 (en) * 2015-05-20 2017-02-21 Intel IP Corporation Conductive paths through dielectric with a high aspect ratio for semiconductor devices
KR101651362B1 (ko) * 2015-05-22 2016-08-25 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지
US10090241B2 (en) * 2015-05-29 2018-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. Device, package structure and method of forming the same
KR102420125B1 (ko) * 2015-12-10 2022-07-13 삼성전자주식회사 반도체 패키지 및 이의 제조방법
KR20170085833A (ko) * 2016-01-15 2017-07-25 삼성전기주식회사 전자 부품 패키지 및 그 제조방법
US9818729B1 (en) * 2016-06-16 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure and method
US11114359B2 (en) * 2018-09-13 2021-09-07 Dialog Semiconductor (Uk) Limited Wafer level chip scale package structure
KR102620566B1 (ko) * 2018-09-27 2024-01-03 삼성전자주식회사 반도체 패키지, 이를 포함하는 스토리지 장치 및 반도체 패키지의 동작 방법
CN109580077B (zh) * 2018-12-06 2020-07-28 中国科学院苏州纳米技术与纳米仿生研究所南昌研究院 压力传感器结构及其制作方法
KR102730308B1 (ko) * 2019-01-30 2024-11-15 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 제조방법
KR20220144265A (ko) 2021-04-19 2022-10-26 삼성전자주식회사 집적회로 소자
CN113555326A (zh) * 2021-06-03 2021-10-26 珠海越亚半导体股份有限公司 可润湿侧面的封装结构与其制作方法及垂直封装模块
TWI798922B (zh) * 2021-11-08 2023-04-11 財團法人工業技術研究院 半導體結構及其製造方法
CN115133402B (zh) * 2022-06-29 2024-08-27 中国科学院半导体研究所 掩埋结构半导体激光器及其制作方法
WO2025159072A1 (ja) * 2024-01-22 2025-07-31 ソニーセミコンダクタソリューションズ株式会社 電子デバイスおよび電子デバイスの製造方法

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10261709A (ja) * 1996-09-27 1998-09-29 Nec Corp 半導体装置の製造方法
JP3184493B2 (ja) 1997-10-01 2001-07-09 松下電子工業株式会社 電子装置の製造方法
US6451624B1 (en) * 1998-06-05 2002-09-17 Micron Technology, Inc. Stackable semiconductor package having conductive layer and insulating layers and method of fabrication
JP3798620B2 (ja) 2000-12-04 2006-07-19 富士通株式会社 半導体装置の製造方法
JP4240899B2 (ja) * 2001-03-26 2009-03-18 Ｎｅｃエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
KR100638379B1 (ko) 2001-08-24 2006-10-26 쇼오트 아게 집적회로의 컨택 제조 및 하우징 공정
US6613606B1 (en) 2001-09-17 2003-09-02 Magic Corporation Structure of high performance combo chip and processing method
JP3853219B2 (ja) * 2002-01-18 2006-12-06 イビデン株式会社 半導体素子内蔵基板および多層回路基板
US6639309B2 (en) 2002-03-28 2003-10-28 Sandisk Corporation Memory package with a controller on one side of a printed circuit board and memory on another side of the circuit board
US6770971B2 (en) 2002-06-14 2004-08-03 Casio Computer Co., Ltd. Semiconductor device and method of fabricating the same
KR100497111B1 (ko) 2003-03-25 2005-06-28 삼성전자주식회사 웨이퍼 레벨 칩 스케일 패키지, 그를 적층한 적층 패키지및 그 제조 방법
CN100468719C (zh) 2003-06-03 2009-03-11 卡西欧计算机株式会社 可叠置的半导体器件及其制造方法
JP4073830B2 (ja) 2003-06-20 2008-04-09 松下電器産業株式会社 半導体チップ内蔵モジュールの製造方法
KR100621992B1 (ko) * 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
US7459781B2 (en) 2003-12-03 2008-12-02 Wen-Kun Yang Fan out type wafer level package structure and method of the same
JP4271590B2 (ja) * 2004-01-20 2009-06-03 新光電気工業株式会社 半導体装置及びその製造方法
US6943106B1 (en) 2004-02-20 2005-09-13 Micron Technology, Inc. Methods of fabricating interconnects for semiconductor components including plating solder-wetting material and solder filling
DE102004020497B8 (de) 2004-04-26 2006-06-14 Infineon Technologies Ag Verfahren zur Herstellung von Durchkontaktierungen und Halbleiterbauteil mit derartigen Durchkontaktierungen
JP4457779B2 (ja) * 2004-06-30 2010-04-28 Ｔｄｋ株式会社 半導体ｉｃ内蔵基板
JP2006222164A (ja) * 2005-02-08 2006-08-24 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP4526983B2 (ja) * 2005-03-15 2010-08-18 新光電気工業株式会社 配線基板の製造方法
JP2007012762A (ja) * 2005-06-29 2007-01-18 Tdk Corp 半導体ｉｃ内蔵基板及びその製造方法
CN100481420C (zh) 2005-09-08 2009-04-22 南茂科技股份有限公司 堆叠型芯片封装结构、芯片封装体及其制造方法
US7511371B2 (en) * 2005-11-01 2009-03-31 Sandisk Corporation Multiple die integrated circuit package
TWI284976B (en) 2005-11-14 2007-08-01 Via Tech Inc Package, package module and manufacturing method of the package
JP2007194436A (ja) 2006-01-19 2007-08-02 Elpida Memory Inc 半導体パッケージ、導電性ポスト付き基板、積層型半導体装置、半導体パッケージの製造方法及び積層型半導体装置の製造方法
US7435675B2 (en) * 2006-06-30 2008-10-14 Intel Corporation Method of providing a pre-patterned high-k dielectric film
KR100800473B1 (ko) * 2006-06-30 2008-02-04 삼성전자주식회사 재배선 칩 패드를 갖는 적층 칩 및 이를 이용한 적층 칩패키지
KR100826979B1 (ko) * 2006-09-30 2008-05-02 주식회사 하이닉스반도체 스택 패키지 및 그 제조방법
US20080197469A1 (en) * 2007-02-21 2008-08-21 Advanced Chip Engineering Technology Inc. Multi-chips package with reduced structure and method for forming the same
KR100914977B1 (ko) * 2007-06-18 2009-09-02 주식회사 하이닉스반도체 스택 패키지의 제조 방법
US7879652B2 (en) * 2007-07-26 2011-02-01 Infineon Technologies Ag Semiconductor module

Similar Documents

Publication Publication Date Title
JP2009044160A5 (enExample)
US8492181B2 (en) Embedded wafer level optical package structure and manufacturing method
JP2009105297A5 (enExample)
TWI763841B (zh) 形成具有豎立指向的電子構件的電子裝置結構的方法及相關結構
JP2010103129A5 (enExample)
JP2008539599A5 (enExample)
JP2014515187A5 (enExample)
JP2009545180A5 (enExample)
SG153722A1 (en) Semiconductor device and method of forming the device using sacrificial carrier
JP2011142264A5 (enExample)
JP2012028429A5 (ja) 半導体装置
CN101661929B (zh) 芯片封装结构及堆叠式芯片封装结构
JP2017135290A5 (enExample)
EP3346492A3 (en) Semiconductor chip package and fabrication method thereof
JP2013508974A5 (enExample)
JP2009152423A5 (enExample)
JP2009176978A5 (enExample)
CN103779290B (zh) 连接基板及层叠封装结构
TW200707676A (en) Thin IC package for improving heat dissipation from chip backside
CN103560090A (zh) 一种用于PoP封装的散热结构的制作方法
CN101286505B (zh) 具有天线的半导体封装结构
JP2009099905A5 (enExample)
JP2007235009A5 (enExample)
JP2011003764A5 (ja) 半導体装置
CN202996814U (zh) 散热型半导体封装构造