JP2009152423A5 - - Google Patents
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- Publication number
- JP2009152423A5 JP2009152423A5 JP2007329505A JP2007329505A JP2009152423A5 JP 2009152423 A5 JP2009152423 A5 JP 2009152423A5 JP 2007329505 A JP2007329505 A JP 2007329505A JP 2007329505 A JP2007329505 A JP 2007329505A JP 2009152423 A5 JP2009152423 A5 JP 2009152423A5
- Authority
- JP
- Japan
- Prior art keywords
- resin layer
- sealing resin
- metal post
- semiconductor device
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007329505A JP5075611B2 (ja) | 2007-12-21 | 2007-12-21 | 半導体装置 |
| US12/339,218 US7928583B2 (en) | 2007-12-21 | 2008-12-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007329505A JP5075611B2 (ja) | 2007-12-21 | 2007-12-21 | 半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2009152423A JP2009152423A (ja) | 2009-07-09 |
| JP2009152423A5 true JP2009152423A5 (enExample) | 2010-12-09 |
| JP5075611B2 JP5075611B2 (ja) | 2012-11-21 |
Family
ID=40787634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007329505A Expired - Fee Related JP5075611B2 (ja) | 2007-12-21 | 2007-12-21 | 半導体装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7928583B2 (enExample) |
| JP (1) | JP5075611B2 (enExample) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9524945B2 (en) | 2010-05-18 | 2016-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with L-shaped non-metal sidewall protection structure |
| US8198133B2 (en) * | 2009-07-13 | 2012-06-12 | International Business Machines Corporation | Structures and methods to improve lead-free C4 interconnect reliability |
| CN102484078B (zh) * | 2009-09-01 | 2015-06-24 | 先进封装技术私人有限公司 | 封装结构 |
| JP5226639B2 (ja) * | 2009-10-09 | 2013-07-03 | 株式会社テラミクロス | 半導体装置およびその製造方法 |
| JP2010268010A (ja) * | 2010-08-31 | 2010-11-25 | Sony Chemical & Information Device Corp | 電子部品、並びに、接合体及びその製造方法 |
| JP5966330B2 (ja) * | 2011-11-24 | 2016-08-10 | ローム株式会社 | 半導体チップおよび半導体パッケージ |
| US9627290B2 (en) * | 2011-12-07 | 2017-04-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structure design for stress reduction |
| US9159686B2 (en) | 2012-01-24 | 2015-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Crack stopper on under-bump metallization layer |
| JP6182309B2 (ja) * | 2012-11-28 | 2017-08-16 | 新光電気工業株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
| JP7157783B2 (ja) * | 2020-09-07 | 2022-10-20 | 富士電機株式会社 | 半導体モジュールの製造方法及び半導体モジュール |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3496569B2 (ja) * | 1999-04-23 | 2004-02-16 | カシオ計算機株式会社 | 半導体装置及びその製造方法並びにその実装構造 |
| JP3450238B2 (ja) * | 1999-11-04 | 2003-09-22 | Ｎｅｃエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
| JP2001339012A (ja) * | 2000-05-30 | 2001-12-07 | Nec Kyushu Ltd | 半導体装置およびその製造方法 |
| JP3998564B2 (ja) | 2002-11-13 | 2007-10-31 | 株式会社巴川製紙所 | 半導体封止用硬化性接着剤組成物および接着シート |
| JP4360873B2 (ja) * | 2003-09-18 | 2009-11-11 | ミナミ株式会社 | ウエハレベルｃｓｐの製造方法 |
| US7294929B2 (en) * | 2003-12-30 | 2007-11-13 | Texas Instruments Incorporated | Solder ball pad structure |
| TWI295498B (en) * | 2005-09-30 | 2008-04-01 | Siliconware Precision Industries Co Ltd | Semiconductor element with conductive bumps and fabrication method thereof |
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2007
- 2007-12-21 JP JP2007329505A patent/JP5075611B2/ja not_active Expired - Fee Related
-
2008
- 2008-12-19 US US12/339,218 patent/US7928583B2/en not_active Expired - Fee Related