KR100885924B1 - 묻혀진 도전성 포스트를 포함하는 반도체 패키지 및 그제조방법 - Google Patents

묻혀진 도전성 포스트를 포함하는 반도체 패키지 및 그제조방법 Download PDF

Info

Publication number
KR100885924B1
KR100885924B1 KR1020070080595A KR20070080595A KR100885924B1 KR 100885924 B1 KR100885924 B1 KR 100885924B1 KR 1020070080595 A KR1020070080595 A KR 1020070080595A KR 20070080595 A KR20070080595 A KR 20070080595A KR 100885924 B1 KR100885924 B1 KR 100885924B1
Authority
KR
South Korea
Prior art keywords
semiconductor chip
conductive
pattern
pad
encapsulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020070080595A
Other languages
English (en)
Korean (ko)
Other versions
KR20090016149A (ko
Inventor
김평완
이택훈
장철용
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020070080595A priority Critical patent/KR100885924B1/ko
Priority to US12/104,333 priority patent/US8093703B2/en
Priority to TW097123954A priority patent/TWI438883B/zh
Priority to CN2008101339737A priority patent/CN101364579B/zh
Priority to DE102008036561.0A priority patent/DE102008036561B4/de
Priority to JP2008206689A priority patent/JP5470510B2/ja
Publication of KR20090016149A publication Critical patent/KR20090016149A/ko
Application granted granted Critical
Publication of KR100885924B1 publication Critical patent/KR100885924B1/ko
Priority to US13/314,464 priority patent/US8846446B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02377—Fan-in arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
KR1020070080595A 2007-08-10 2007-08-10 묻혀진 도전성 포스트를 포함하는 반도체 패키지 및 그제조방법 Active KR100885924B1 (ko)

Priority Applications (7)

Application Number Priority Date Filing Date Title
KR1020070080595A KR100885924B1 (ko) 2007-08-10 2007-08-10 묻혀진 도전성 포스트를 포함하는 반도체 패키지 및 그제조방법
US12/104,333 US8093703B2 (en) 2007-08-10 2008-04-16 Semiconductor package having buried post in encapsulant and method of manufacturing the same
TW097123954A TWI438883B (zh) 2007-08-10 2008-06-26 封膠中有埋入式柱的半導體封裝及其製造方法
CN2008101339737A CN101364579B (zh) 2007-08-10 2008-07-18 半导体封装及其制造方法和包括该半导体封装的系统
DE102008036561.0A DE102008036561B4 (de) 2007-08-10 2008-07-30 Halbleiterbauelementpackung, Herstellungsverfahren und System
JP2008206689A JP5470510B2 (ja) 2007-08-10 2008-08-11 埋め込まれた導電性ポストを備える半導体パッケージ
US13/314,464 US8846446B2 (en) 2007-08-10 2011-12-08 Semiconductor package having buried post in encapsulant and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070080595A KR100885924B1 (ko) 2007-08-10 2007-08-10 묻혀진 도전성 포스트를 포함하는 반도체 패키지 및 그제조방법

Publications (2)

Publication Number Publication Date
KR20090016149A KR20090016149A (ko) 2009-02-13
KR100885924B1 true KR100885924B1 (ko) 2009-02-26

Family

ID=40345696

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070080595A Active KR100885924B1 (ko) 2007-08-10 2007-08-10 묻혀진 도전성 포스트를 포함하는 반도체 패키지 및 그제조방법

Country Status (5)

Country Link
US (2) US8093703B2 (enExample)
JP (1) JP5470510B2 (enExample)
KR (1) KR100885924B1 (enExample)
CN (1) CN101364579B (enExample)
TW (1) TWI438883B (enExample)

Families Citing this family (85)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US7791199B2 (en) 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
WO2008108970A2 (en) 2007-03-05 2008-09-12 Tessera, Inc. Chips having rear contacts connected by through vias to front contacts
WO2009017835A2 (en) 2007-07-31 2009-02-05 Tessera, Inc. Semiconductor packaging process using through silicon vias
US20090212381A1 (en) * 2008-02-26 2009-08-27 Tessera, Inc. Wafer level packages for rear-face illuminated solid state image sensors
US20100053407A1 (en) * 2008-02-26 2010-03-04 Tessera, Inc. Wafer level compliant packages for rear-face illuminated solid state image sensors
US7964450B2 (en) * 2008-05-23 2011-06-21 Stats Chippac, Ltd. Wirebondless wafer level package with plated bumps and interconnects
US20110073357A1 (en) * 2008-06-02 2011-03-31 Nxp B.V. Electronic device and method of manufacturing an electronic device
US7855439B2 (en) * 2008-08-28 2010-12-21 Fairchild Semiconductor Corporation Molded ultra thin semiconductor die packages, systems using the same, and methods of making the same
US8704350B2 (en) * 2008-11-13 2014-04-22 Samsung Electro-Mechanics Co., Ltd. Stacked wafer level package and method of manufacturing the same
US8183677B2 (en) * 2008-11-26 2012-05-22 Infineon Technologies Ag Device including a semiconductor chip
US8008125B2 (en) * 2009-03-06 2011-08-30 General Electric Company System and method for stacked die embedded chip build-up
EP2406821A2 (en) * 2009-03-13 2012-01-18 Tessera, Inc. Stacked microelectronic assemblies having vias extending through bond pads
US8258010B2 (en) * 2009-03-17 2012-09-04 Stats Chippac, Ltd. Making a semiconductor device having conductive through organic vias
US8026608B2 (en) * 2009-03-24 2011-09-27 General Electric Company Stackable electronic package
JP5330065B2 (ja) * 2009-04-13 2013-10-30 新光電気工業株式会社 電子装置及びその製造方法
TWI405306B (zh) * 2009-07-23 2013-08-11 日月光半導體製造股份有限公司 半導體封裝件、其製造方法及重佈晶片封膠體
US8367470B2 (en) * 2009-08-07 2013-02-05 Stats Chippac, Ltd. Semiconductor device and method of forming cavity in build-up interconnect structure for short signal path between die
EP2302403A1 (en) * 2009-09-28 2011-03-30 Imec Method and device for testing TSVs in a 3D chip stack
US20110084372A1 (en) * 2009-10-14 2011-04-14 Advanced Semiconductor Engineering, Inc. Package carrier, semiconductor package, and process for fabricating same
TWI497679B (zh) * 2009-11-27 2015-08-21 日月光半導體製造股份有限公司 半導體封裝件及其製造方法
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8372689B2 (en) * 2010-01-21 2013-02-12 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof
TWI411075B (zh) * 2010-03-22 2013-10-01 日月光半導體製造股份有限公司 半導體封裝件及其製造方法
US8759209B2 (en) 2010-03-25 2014-06-24 Stats Chippac, Ltd. Semiconductor device and method of forming a dual UBM structure for lead free bump connections
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
CN102244972A (zh) * 2010-04-08 2011-11-16 王忠诚 电路板及其应用
US8421210B2 (en) 2010-05-24 2013-04-16 Stats Chippac Ltd. Integrated circuit packaging system with dual side connection and method of manufacture thereof
US8987878B2 (en) * 2010-10-29 2015-03-24 Alpha And Omega Semiconductor Incorporated Substrateless power device packages
US9620455B2 (en) * 2010-06-24 2017-04-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming anisotropic conductive film between semiconductor die and build-up interconnect structure
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8193610B2 (en) * 2010-08-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming B-stage conductive polymer over contact pads of semiconductor die in Fo-WLCSP
KR101695352B1 (ko) * 2010-08-12 2017-01-12 삼성전자 주식회사 리드 프레임 및 이를 갖는 반도체 패키지
TWI426587B (zh) * 2010-08-12 2014-02-11 矽品精密工業股份有限公司 晶片尺寸封裝件及其製法
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
JP2012099648A (ja) * 2010-11-02 2012-05-24 Fujitsu Semiconductor Ltd 半導体装置とその製造方法
US8941222B2 (en) 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
KR101059490B1 (ko) 2010-11-15 2011-08-25 테세라 리써치 엘엘씨 임베드된 트레이스에 의해 구성된 전도성 패드
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US8736065B2 (en) 2010-12-22 2014-05-27 Intel Corporation Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same
KR20120091694A (ko) * 2011-02-09 2012-08-20 삼성전자주식회사 반도체 패키지
TWI462201B (zh) * 2011-03-04 2014-11-21 群成科技股份有限公司 半導體封裝結構及其製造方法
US8461691B2 (en) * 2011-04-29 2013-06-11 Infineon Technologies Ag Chip-packaging module for a chip and a method for forming a chip-packaging module
US8288209B1 (en) * 2011-06-03 2012-10-16 Stats Chippac, Ltd. Semiconductor device and method of using leadframe bodies to form openings through encapsulant for vertical interconnect of semiconductor die
US9123763B2 (en) * 2011-10-12 2015-09-01 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) structure having at least one package comprising one die being disposed in a core material between first and second surfaces of the core material
US8975741B2 (en) 2011-10-17 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Process for forming package-on-package structures
JP5870626B2 (ja) * 2011-11-01 2016-03-01 富士通株式会社 半導体装置及び半導体装置の製造方法
EP2613349B1 (en) 2012-01-05 2019-11-20 Nxp B.V. Semiconductor package with improved thermal properties
US8658473B2 (en) 2012-03-27 2014-02-25 General Electric Company Ultrathin buried die module and method of manufacturing thereof
KR101985236B1 (ko) 2012-07-10 2019-06-03 삼성전자주식회사 멀티-칩 패키지 및 그의 제조 방법
US8963336B2 (en) 2012-08-03 2015-02-24 Samsung Electronics Co., Ltd. Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same
KR101970291B1 (ko) * 2012-08-03 2019-04-18 삼성전자주식회사 반도체 패키지의 제조 방법
US9496211B2 (en) * 2012-11-21 2016-11-15 Intel Corporation Logic die and other components embedded in build-up layers
US9293404B2 (en) * 2013-01-23 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Pre-applying supporting materials between bonded package components
US9379041B2 (en) 2013-12-11 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fan out package structure
US9184128B2 (en) * 2013-12-13 2015-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC package and methods of forming the same
CN103681372B (zh) * 2013-12-26 2016-07-06 华进半导体封装先导技术研发中心有限公司 扇出型圆片级三维半导体芯片的封装方法
MY171261A (en) * 2014-02-19 2019-10-07 Carsem M Sdn Bhd Stacked electronic packages
US9527723B2 (en) 2014-03-13 2016-12-27 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming microelectromechanical systems (MEMS) package
JP6317629B2 (ja) * 2014-06-02 2018-04-25 株式会社東芝 半導体装置
JP6318016B2 (ja) * 2014-06-10 2018-04-25 株式会社ディスコ 積層デバイスの製造方法
US10257937B2 (en) * 2014-07-07 2019-04-09 Infineon Technologies Austria Ag Device for electrically coupling a plurality of semiconductor device layers by a common conductive layer
CN106158772B (zh) * 2015-03-27 2018-12-18 蔡亲佳 板级嵌入式封装结构及其制作方法
US9576918B2 (en) * 2015-05-20 2017-02-21 Intel IP Corporation Conductive paths through dielectric with a high aspect ratio for semiconductor devices
KR101651362B1 (ko) * 2015-05-22 2016-08-25 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지
US10090241B2 (en) * 2015-05-29 2018-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. Device, package structure and method of forming the same
KR102420125B1 (ko) 2015-12-10 2022-07-13 삼성전자주식회사 반도체 패키지 및 이의 제조방법
KR20170085833A (ko) * 2016-01-15 2017-07-25 삼성전기주식회사 전자 부품 패키지 및 그 제조방법
US9818729B1 (en) * 2016-06-16 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure and method
US11114359B2 (en) * 2018-09-13 2021-09-07 Dialog Semiconductor (Uk) Limited Wafer level chip scale package structure
KR102620566B1 (ko) * 2018-09-27 2024-01-03 삼성전자주식회사 반도체 패키지, 이를 포함하는 스토리지 장치 및 반도체 패키지의 동작 방법
CN109580077B (zh) * 2018-12-06 2020-07-28 中国科学院苏州纳米技术与纳米仿生研究所南昌研究院 压力传感器结构及其制作方法
KR102730308B1 (ko) * 2019-01-30 2024-11-15 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 제조방법
KR20220144265A (ko) 2021-04-19 2022-10-26 삼성전자주식회사 집적회로 소자
CN113555326A (zh) * 2021-06-03 2021-10-26 珠海越亚半导体股份有限公司 可润湿侧面的封装结构与其制作方法及垂直封装模块
TWI798922B (zh) * 2021-11-08 2023-04-11 財團法人工業技術研究院 半導體結構及其製造方法
CN115133402B (zh) * 2022-06-29 2024-08-27 中国科学院半导体研究所 掩埋结构半导体激光器及其制作方法
WO2025159072A1 (ja) * 2024-01-22 2025-07-31 ソニーセミコンダクタソリューションズ株式会社 電子デバイスおよび電子デバイスの製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980024991A (ko) * 1996-09-27 1998-07-06 가네꼬 히사시 다층 배선의 제조방법
JP2005167191A (ja) 2003-12-03 2005-06-23 Advanced Chip Engineering Technology Inc ファンアウト型ウェハレベルパッケージ構造及びその製造方法
JP2007194436A (ja) 2006-01-19 2007-08-02 Elpida Memory Inc 半導体パッケージ、導電性ポスト付き基板、積層型半導体装置、半導体パッケージの製造方法及び積層型半導体装置の製造方法

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3184493B2 (ja) 1997-10-01 2001-07-09 松下電子工業株式会社 電子装置の製造方法
US6451624B1 (en) * 1998-06-05 2002-09-17 Micron Technology, Inc. Stackable semiconductor package having conductive layer and insulating layers and method of fabrication
JP3798620B2 (ja) 2000-12-04 2006-07-19 富士通株式会社 半導体装置の製造方法
JP4240899B2 (ja) * 2001-03-26 2009-03-18 Ｎｅｃエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
EP1419534A2 (de) 2001-08-24 2004-05-19 Schott Glas Verfahren zum kontaktieren und gehäusen von integrierten schaltungen
US6613606B1 (en) 2001-09-17 2003-09-02 Magic Corporation Structure of high performance combo chip and processing method
JP3853219B2 (ja) * 2002-01-18 2006-12-06 イビデン株式会社 半導体素子内蔵基板および多層回路基板
US6639309B2 (en) 2002-03-28 2003-10-28 Sandisk Corporation Memory package with a controller on one side of a printed circuit board and memory on another side of the circuit board
US6770971B2 (en) 2002-06-14 2004-08-03 Casio Computer Co., Ltd. Semiconductor device and method of fabricating the same
KR100497111B1 (ko) 2003-03-25 2005-06-28 삼성전자주식회사 웨이퍼 레벨 칩 스케일 패키지, 그를 적층한 적층 패키지및 그 제조 방법
EP1636842B1 (en) 2003-06-03 2011-08-17 Casio Computer Co., Ltd. Stackable semiconductor device and method of manufacturing the same
JP4073830B2 (ja) 2003-06-20 2008-04-09 松下電器産業株式会社 半導体チップ内蔵モジュールの製造方法
KR100621992B1 (ko) * 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
JP4271590B2 (ja) * 2004-01-20 2009-06-03 新光電気工業株式会社 半導体装置及びその製造方法
US6943106B1 (en) 2004-02-20 2005-09-13 Micron Technology, Inc. Methods of fabricating interconnects for semiconductor components including plating solder-wetting material and solder filling
DE102004020497B8 (de) 2004-04-26 2006-06-14 Infineon Technologies Ag Verfahren zur Herstellung von Durchkontaktierungen und Halbleiterbauteil mit derartigen Durchkontaktierungen
JP4457779B2 (ja) * 2004-06-30 2010-04-28 Ｔｄｋ株式会社 半導体ｉｃ内蔵基板
JP2006222164A (ja) * 2005-02-08 2006-08-24 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP4526983B2 (ja) * 2005-03-15 2010-08-18 新光電気工業株式会社 配線基板の製造方法
JP2007012762A (ja) * 2005-06-29 2007-01-18 Tdk Corp 半導体ｉｃ内蔵基板及びその製造方法
CN100481420C (zh) 2005-09-08 2009-04-22 南茂科技股份有限公司 堆叠型芯片封装结构、芯片封装体及其制造方法
US7511371B2 (en) * 2005-11-01 2009-03-31 Sandisk Corporation Multiple die integrated circuit package
TWI284976B (en) 2005-11-14 2007-08-01 Via Tech Inc Package, package module and manufacturing method of the package
US7435675B2 (en) * 2006-06-30 2008-10-14 Intel Corporation Method of providing a pre-patterned high-k dielectric film
KR100800473B1 (ko) * 2006-06-30 2008-02-04 삼성전자주식회사 재배선 칩 패드를 갖는 적층 칩 및 이를 이용한 적층 칩패키지
KR100826979B1 (ko) * 2006-09-30 2008-05-02 주식회사 하이닉스반도체 스택 패키지 및 그 제조방법
US20080197469A1 (en) * 2007-02-21 2008-08-21 Advanced Chip Engineering Technology Inc. Multi-chips package with reduced structure and method for forming the same
KR100914977B1 (ko) 2007-06-18 2009-09-02 주식회사 하이닉스반도체 스택 패키지의 제조 방법
US7879652B2 (en) * 2007-07-26 2011-02-01 Infineon Technologies Ag Semiconductor module

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980024991A (ko) * 1996-09-27 1998-07-06 가네꼬 히사시 다층 배선의 제조방법
JP2005167191A (ja) 2003-12-03 2005-06-23 Advanced Chip Engineering Technology Inc ファンアウト型ウェハレベルパッケージ構造及びその製造方法
JP2007194436A (ja) 2006-01-19 2007-08-02 Elpida Memory Inc 半導体パッケージ、導電性ポスト付き基板、積層型半導体装置、半導体パッケージの製造方法及び積層型半導体装置の製造方法

Also Published As

Publication number Publication date
US20090039491A1 (en) 2009-02-12
TW200908273A (en) 2009-02-16
JP2009044160A (ja) 2009-02-26
CN101364579A (zh) 2009-02-11
US8093703B2 (en) 2012-01-10
KR20090016149A (ko) 2009-02-13
US8846446B2 (en) 2014-09-30
JP5470510B2 (ja) 2014-04-16
TWI438883B (zh) 2014-05-21
CN101364579B (zh) 2013-03-20
US20120077311A1 (en) 2012-03-29

Similar Documents

Publication Publication Date Title
KR100885924B1 (ko) 묻혀진 도전성 포스트를 포함하는 반도체 패키지 및 그제조방법
CN109979924B (zh) 插入基底和半导体封装件
US8729690B2 (en) Assembly having stacked die mounted on substrate
US7888785B2 (en) Semiconductor package embedded in substrate, system including the same and associated methods
KR101567943B1 (ko) 적층 인터포저를 구비한 실장식 집적 회로 패키지 시스템
KR20090039411A (ko) 솔더 볼과 칩 패드가 접합된 구조를 갖는 반도체 패키지,모듈, 시스템 및 그 제조방법
KR20140057982A (ko) 반도체 패키지 및 반도체 패키지의 제조 방법
KR20140057979A (ko) 반도체 패키지 및 반도체 패키지의 제조 방법
US20150115429A1 (en) Semiconductor package
JP2009141312A (ja) スタック型チップパッケージ構造
CN112071821B (zh) 半导体封装基板及其制法与电子封装件
US9202742B1 (en) Integrated circuit packaging system with pattern-through-mold and method of manufacture thereof
KR20210109258A (ko) 반도체 패키지 장치
US20080258288A1 (en) Semiconductor device stack package, electronic apparatus including the same, and method of manufacturing the same
KR101227078B1 (ko) 반도체 패키지 및 그 형성방법
KR100744146B1 (ko) 연성 접속판을 이용하여 배선 기판과 칩을 연결하는 반도체패키지
US11328997B2 (en) Through-core via
KR20130050077A (ko) 스택 패키지 및 이의 제조 방법
JP5078808B2 (ja) 半導体装置の製造方法
CN100539102C (zh) 电路板嵌埋有半导体芯片的电性连接结构
US20230111207A1 (en) Semiconductor package including sub-package
KR20010063236A (ko) 적층 패키지와 그 제조 방법
CN101465341B (zh) 堆叠式芯片封装结构
JP2008270597A (ja) 半導体装置
KR20120091694A (ko) 반도체 패키지

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 20070810

PA0201 Request for examination
E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 20081205

PG1501 Laying open of application
GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20090220

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20090223

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20120131

Start annual number: 4

End annual number: 4

FPAY Annual fee payment

Payment date: 20130131

Year of fee payment: 5

PR1001 Payment of annual fee

Payment date: 20130131

Start annual number: 5

End annual number: 5

FPAY Annual fee payment

Payment date: 20140129

Year of fee payment: 6

PR1001 Payment of annual fee

Payment date: 20140129

Start annual number: 6

End annual number: 6

FPAY Annual fee payment

Payment date: 20150202

Year of fee payment: 7

PR1001 Payment of annual fee

Payment date: 20150202

Start annual number: 7

End annual number: 7

PR1001 Payment of annual fee

Payment date: 20210128

Start annual number: 13

End annual number: 13

PR1001 Payment of annual fee

Payment date: 20220126

Start annual number: 14

End annual number: 14

PR1001 Payment of annual fee

Payment date: 20230125

Start annual number: 15

End annual number: 15

PR1001 Payment of annual fee

Payment date: 20250124

Start annual number: 17

End annual number: 17