JP5470510B2 - 埋め込まれた導電性ポストを備える半導体パッケージ - Google Patents
埋め込まれた導電性ポストを備える半導体パッケージ Download PDFInfo
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- JP5470510B2 JP5470510B2 JP2008206689A JP2008206689A JP5470510B2 JP 5470510 B2 JP5470510 B2 JP 5470510B2 JP 2008206689 A JP2008206689 A JP 2008206689A JP 2008206689 A JP2008206689 A JP 2008206689A JP 5470510 B2 JP5470510 B2 JP 5470510B2
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Description
前記複数の導電性ポストの厚さは、前記半導体チップの厚さより薄いことを特徴とする。
前記導電性ポストは、前記封止部に対し接着力の優れた物質である、銅、鉄、アルミニウム、及び導電性を有するポリマーからなる群より選択される一つを材質とすることが好ましい。
前記封止部を貫通して前記導電性ポストの下面と電気的に接続する貫通電極と、前記封止部の下面で前記貫通電極と電気的に接続された下部ソルダボールパッドとをさらに有することが好ましい。
前記下部ソルダボールパッドに付着されるソルダボールをさらに有することが好ましい。
前記複数の第1導電性ポストの厚さは、前記第1半導体チップの厚さより薄いことを特徴とする。
前記第1封止部を貫通して前記第1導電性ポストの下面と電気的に接続する貫通電極と、前記第1封止部の下面で前記貫通電極と電気的に接続する下部ソルダボールパッドとをさらに有することが好ましい。
前記下部ソルダボールパッドに付着するソルダボールをさらに有することが好ましい。
前記第2半導体チップ上で活性面が上方に向くように搭載される第3半導体チップと、前記第2封止部の上面を覆い、前記第3半導体チップの上面は露出させ、前記第1導電性パターンの一部を露出させる貫通ホールを備える第3封止部と、前記露出された第1導電性パターンと前記第3半導体チップのボンディングパッドとを電気的に接続する第2導電性パターンとをさらに有することが好ましい。
前記第3半導体チップ上で活性面が上方に向くように搭載される第4半導体チップと、前記第3封止部の上面を覆い、前記第4半導体チップの上面は露出させ、内部に設けられた貫通ホールによって前記第2導電性パターンの一部を露出させる第4封止部と、前記露出された第2導電性パターンと前記第4半導体チップのボンディングパッドとを電気的に接続する第3導電性パターンとをさらに有することが好ましい。
前記複数の第1導電性ポストの厚さは、前記第1半導体チップの厚さより薄いことを特徴とする。
前記第2半導体チップの上部接続パッドに付着するソルダボールをさらに有することが好ましい。
第二に、埋め込まれた構造の導電性ポストによって、上下半導体チップの上下接続のためのコンタクトホールを形成するとき、この部分で損傷が発生することを抑制すると同時に、半導体パッケージのノイズ発生を改善し、電源及び接地を安定化させて全体的な電気的信頼性を改善しうるという効果がある。
第四に、印刷回路基板やリードフレームを使用せずとも、純粋に半導体チップのみを封止部の内部で積層してファンアウト構造を有する積層型半導体パッケージを作れるという効果がある。
図1〜図5は、本発明の第1の実施形態による埋め込まれた導電性ポストを備える半導体パッケージの製造方法を説明するための断面図である。
キャリア基板は、金属やポリイミドのような材質を使用しうる。キャリア基板100は、内部に半導体チップ接着部が設けられており、半導体チップ接着部の縁部に沿って複数の導電性ポスト104を接着手段102を使用して付着する。
接着手段102は、熱や光によって接着力が変化する接着剤であることが望ましい。このとき、接着手段102が光によって接着力が変化する場合、硬質のキャリア基板100は、透光性のある透明材質であることが適している。
次いで、キャリア基板100を封止部108と分離させて除去した後、その結果物をひっくり返す。
これにより、複数の導電性ポスト104の上面及び半導体チップ106の活性面が上部に露出される。
そして、導電性ポスト104及び半導体チップ106の残りの部分は、封止部108内に埋め込まれた構造となる。
また、導電性ポスト104の厚さは、半導体チップ106より薄い範囲内で多様に適用しうる。一方、導電性ポスト104は、物理的な損傷を抑制する目的でのみ適用されれば、第1封止部108と適切な接着力を維持し、硬度のみあれば、絶縁物質に代替させて適用することもできる。
本実施形態では、パッド再配置パターン110は、銅を使用して作ることを一つの例として説明したが、パッド再配置パターン110は、導電性を有する他の材質に変えて適用可能である。
これにより、リードフレームや印刷回路基板のような骨格材を使用せずとも、半導体チップ106が封止部108に埋め込まれた構造で半導体パッケージ200を作りうる。半導体パッケージ200は、導電性ポスト104及びパッド再配置パターン110によって効率的なファンアウト構造を実現しうるため、半導体チップ106のボンディングパッド間隔が狭くなっても、これを効率的に再配置しうる。
本発明の第1の実施形態による埋め込まれた導電性ポストを備える半導体パッケージ200は、回路部が形成された活性面が上に向いた半導体チップ106と、半導体チップ106の活性面を外部に露出させ、残りの部分を密封する封止部108と、封止部内で上面のみが外部に露出され、残りの部分は埋め込まれた構造であり、半導体チップ106の外郭に沿って配置された複数の導電性ポスト104と、半導体チップ106及び封止部108上で半導体チップ106のボンディングパッドと導電性ポスト104の上部とを電気的に接続するパッド再配置パターン110及びパッド再配置パターン上に付着されるソルダボール112とを備える。
図6を参照すると、図5の埋め込まれた導電性ポストを備える半導体パッケージ200は、半導体パッケージの内部に一つの半導体チップが含まれることを中心に説明した。
しかし、図5の半導体パッケージ200の下部に印刷回路基板(PCB:Print Circuit Board)と電気的に接続される接続端子を作る場合、本発明による埋め込まれた導電性ポストを備える半導体パッケージ200は、POP(POP:Package On Package)構造でその使用範囲を拡大適用しうる。
すなわち、上部パッド再配置パターン110上に搭載されたソルダボール112に他の半導体パッケージをさらに搭載して、さらに多様な機能を行う半導体パッケージを具現しうる。
次いで、コンタクト電極114と接続された下部ソルダボールパッド116を形成し、下部ソルダボールパッド116にソルダボール112を付着する。下部ソルダボールパッド116に付着されたソルダボール112は、印刷回路基板と電気的に接続され、パッド再配置パターン112に接続されたソルダボール112は、他の半導体パッケージと接続される場合、本発明の第1の実施形態の変形例による半導体パッケージ202は、POP構造を有する。
図7〜図11は、本発明の第2の実施形態による埋め込まれた導電性ポストを備える半導体パッケージの製造方法を説明するための断面図である。
図7〜図11を参照すると、本実施形態による埋め込まれた導電性ポストを備える半導体パッケージは、2つの封止部の内部にそれぞれ半導体チップを有し、それらが積層された形態の半導体パッケージである。
パッド再配置パターン112を作る工程までは、前述した第1の実施形態と同じであるため、ここで説明を省略し、前述した第1の実施形態の図4についての説明に続けてその製造方法を説明する。
第2封止部122は、パッド再配置パターン110の一部を除外した第1封止部108の上面を覆い、高さが第2半導体チップ118と同じであることが適している。第2封止部122のコンタクトホール124は、第2封止部122を形成した後、レーザドリリング、ドリリング、ウェットエッチングのうちから選択される一つの方法でコンタクトホール124を形成しうる。
また、コンタクトホール124を形成する過程で、コンタクトホールの深さがパッド再配置パターン110の下方に形成されても、パッド再配置パターン110と下部にある導電性ポスト104とは、相互電気的に接続された状態であるため、これを補完しうる。
第2導電性パターン126を形成するために、第1の実施形態のように、絶縁膜パターン(図示せず)をまず形成し、スパッタリングによるシード層を形成し、シード層上に電気メッキ層を形成する方式で第1導電性パターン126を形成しうる。
最後に、ソルダボール112が付着した結果物にシンギュレーション工程を実施して半導体チップ106、118が二つ積層された構造の半導体パッケージ204に対する製造工程を完了する。
本発明の第2の実施形態による埋め込まれた導電性ポストを備える半導体パッケージ204は、回路部が形成された活性面が上方を向いた第1半導体チップ106と、第1半導体チップ106の活性面のみを外部に露出させ、残りの部分を密封する第1封止部108と、第1封止部108内で上面のみが外部に露出され、残りの部分は埋め込まれた構造であり、第1半導体チップ106の外郭に沿って配置される複数の第1導電性ポスト104と、第1半導体チップ106及び第1封止部108上で第1半導体チップ106のボンディングパッドと第1導電性ポスト104の上部とを電気的に接続するパッド再配置パターン110とを備える。
図12は、本発明の第2の実施形態による半導体パッケージをPOP形態に変形させた積層型半導体パッケージ206の断面図である。
その製造工程及び構造は、上述の図6での説明と同じであるため、ここでは重複を避けて説明を省略する。
図13は、本発明の第3の実施形態による埋め込まれた導電性ポストを備える半導体パッケージ208の断面図であり、図14は、第3の実施形態による半導体パッケージをPOPに適用できるように変形させた半導体パッケージ210の断面図である。
本実施形態では、4個の半導体チップが積層されたことを一例として説明したが、これは、6個、8個等、多様に変形適用が可能である。
図15〜図18を参照すると、上述した第3の実施形態では、第1導電性パターン126と第2導電性パターン134との接続を第2封止部122の上部で実施したが、第1導電性パターン126と第2導電性パターン134との接続は、図15に示すように、第2封止部122の下部(第1封止部108の上面)で、パッド再配置パターン110の導電性ポスト104との接触部分上と接するように実施できる。
符号144A、144B、144Cは、層間絶縁膜であって、パッド再配置パターン110、第1導電性パターン126及び第2導電性パターン143の下に形成しうる。
このとき、パッド再配置パターン110、第1導電性パターン126、及び第2導電性パターン134は、それぞれ層間絶縁膜144A、144B、144Cに形成されたコンタクトホールを通じて半導体チップに形成されたボンディングパッドと相互接続される。
このとき、コンタクトホールの内部には、充填物質148を内部に充填することが適しており、充填物質148は、導電物質あるいは絶縁物質を半導体素子の機能によって適切に選択して使用しうる。また、パッド再配置パターン110、第1〜第3導電性パターン126、134、142及び下部ソルダボールパッド116(図14)の表面は、必要に応じて適切な表面処理を行うことが好ましい。
図21を参照すると、本発明の第4の実施形態による埋め込まれた導電性ポストを備える半導体パッケージ208は、回路部が形成された活性面が上方に向く第1半導体チップ106と、第1半導体チップの活性面のみを外部に露出させ、残りの部分を密封する第1封止部108と、第1封止部108内で上面のみが外部に露出され、残りの部分は埋め込まれた構造であり、第1半導体チップ106の外郭に沿って配置される複数の第1導電性ポスト104と、第1半導体チップ106及び第1封止部108上で第1半導体チップ106のボンディングパッドと第1導電性ポスト104の上部とを電気的に接続するパッド再配置パターン110とを備える。
最後に、本実施形態による埋め込まれた導電性ポストを備える半導体パッケージ208は、上部接続パッド115bに付着されたソルダボール112をさらに備える。したがって、ソルダボール112を通じて本半導体パッケージが応用されるPCB等に付着されて作動する。
図22を参照すると、制御機410とメモリ420とは、電気的な信号を交換するように配される。例えば、制御機410で命令を出せば、メモリ420は、データを伝送しうる。ここで、メモリ420は、上述の埋め込まれた導電性ポストを備える半導体パッケージ210(図14)の形態を取り得る。
このようなカード400は、マルチメディアカード(Multi Media Card:MMC)または保安用デジタルカードのようなメモリ装置として利用される。
図23を参照すると、プロセッサ510、入/出力装置530、及びメモリ520は、バス540を利用して相互データ通信を行える。プロセッサ510は、プログラムを実行し、システム500を制御する役割を行う。入/出力装置530は、システム500のデータの入力または出力に利用される。システム500は、入/出力装置530を利用して外部装置、例えば、個人用コンピュータまたはネットワークに接続されて、外部装置と相互データを交換しうる。
102 接着手段
104 (第1)導電性ポスト
106 (第1)半導体チップ
108 (第1)封止部
110 パッド再配置パターン
112 ソルダボール
114 コンタクト電極
114a 貫通電極
115a 下部接続パッド
115b 上部接続パッド
116 下部ソルダボールパッド
118、118a 第2半導体チップ
120 接着手段
122 第2封止部
124 コンタクトホール
126 第1導電性パターン
128 第3半導体チップ
130、138 接着手段
132 第3封止部
134 第2導電性パターン
136 第4半導体チップ
140 第4封止部
142 第3導電性パターン
144(A、B、C) 層間絶縁膜
146 導電物質
148 充填物質
200、202、204、206、208、210 半導体パッケージ
Claims (14)
- 回路部が形成された活性面が上方に向いた半導体チップと、
前記半導体チップの活性面を外部に露出させ、残りの部分を密封する封止部と、
前記封止部内で、上面のみが外部に露出され、残りの部分は埋め込まれた構造であって、前記半導体チップの外郭に沿って配置される複数の導電性ポストと、
前記半導体チップ及び封止部上で半導体チップのボンディングパッドと前記導電性ポストの上部とを電気的に接続するパッド再配置パターンとを有し、
前記複数の導電性ポストの厚さは、前記半導体チップの厚さより薄いことを特徴とする埋め込まれた導電性ポストを備える半導体パッケージ。 - 前記導電性ポスト上に位置した前記パッド再配置パターンに付着されるソルダボールをさらに有することを特徴とする請求項1に記載の埋め込まれた導電性ポストを備える半導体パッケージ。
- 前記導電性ポストは、前記封止部に対し接着力の優れた物質である、銅、鉄、アルミニウム、及び導電性を有するポリマーからなる群より選択される一つを材質とすることを特徴とする請求項1に記載の埋め込まれた導電性ポストを備える半導体パッケージ。
- 前記封止部を貫通して前記導電性ポストの下面と電気的に接続する貫通電極と、
前記封止部の下面で前記貫通電極と電気的に接続された下部ソルダボールパッドとをさらに有することを特徴とする請求項1に記載の埋め込まれた導電性ポストを備える半導体パッケージ。 - 前記下部ソルダボールパッドに付着されるソルダボールをさらに有することを特徴とする請求項4に記載の埋め込まれた導電性ポストを備える半導体パッケージ。
- 回路部が形成された活性面が上方に向いた第1半導体チップと、
前記第1半導体チップの活性面のみを外部に露出させ、残りの部分を密封する第1封止部と、
前記第1封止部内に、上面のみが外部に露出され、残りの部分は埋め込まれた構造であり、前記第1半導体チップの外郭に沿って配置される複数の第1導電性ポストと、
前記第1半導体チップ及び第1封止部上で前記第1半導体チップのボンディングパッドと第1導電性ポストの上部とを電気的に接続するパッド再配置パターンと、
前記第1半導体チップ上に活性面が上方に向くように接着手段を通じて搭載される第2半導体チップと、
前記第1封止部の上面を覆い、前記第2半導体チップの上面は露出させ、前記導電性ポスト上にあるパッド再配置パターンの一部を露出させる貫通ホールを備える第2封止部と、
前記パッド再配置パターンと前記第2半導体チップのボンディングパッドとを電気的に接続する第1導電性パターンとを有し、
前記複数の第1導電性ポストの厚さは、前記第1半導体チップの厚さより薄いことを特徴とする埋め込まれた導電性ポストを備える半導体パッケージ。 - 前記第1導電性パターンに付着するソルダボールをさらに有することを特徴とする請求項6に記載の埋め込まれた導電性ポストを備える半導体パッケージ。
- 前記第1封止部を貫通して前記第1導電性ポストの下面と電気的に接続する貫通電極と、
前記第1封止部の下面で前記貫通電極と電気的に接続する下部ソルダボールパッドとをさらに有することを特徴とする請求項6に記載の埋め込まれた導電性ポストを備える半導体パッケージ。 - 前記下部ソルダボールパッドに付着するソルダボールをさらに有することを特徴とする請求項8に記載の埋め込まれた導電性ポストを備える半導体パッケージ。
- 前記第2半導体チップ上で活性面が上方に向くように搭載される第3半導体チップと、
前記第2封止部の上面を覆い、前記第3半導体チップの上面は露出させ、前記第1導電性パターンの一部を露出させる貫通ホールを備える第3封止部と、
前記露出された第1導電性パターンと前記第3半導体チップのボンディングパッドとを電気的に接続する第2導電性パターンとをさらに有することを特徴とする請求項6に記載の埋め込まれた導電性ポストを備える半導体パッケージ。 - 前記第3半導体チップ上で活性面が上方に向くように搭載される第4半導体チップと、
前記第3封止部の上面を覆い、前記第4半導体チップの上面は露出させ、内部に設けられた貫通ホールによって前記第2導電性パターンの一部を露出させる第4封止部と、
前記露出された第2導電性パターンと前記第4半導体チップのボンディングパッドとを電気的に接続する第3導電性パターンとをさらに有することを特徴とする請求項10に記載の埋め込まれた導電性ポストを備える半導体パッケージ。 - 回路部が形成された活性面が上方に向いた第1半導体チップと、
前記第1半導体チップの活性面のみを外部に露出させ、残りの部分を密封する第1封止部と、
前記第1封止部内に、上面のみが外部に露出され、残りの部分は埋め込まれた構造であり、前記第1半導体チップの外郭に沿って配置される複数の第1導電性ポストと、
前記第1半導体チップ及び第1封止部上で前記第1半導体チップのボンディングパッドと第1導電性ポストの上部とを電気的に接続するパッド再配置パターンと、
前記第1半導体チップ上に活性面が下方に向くように接着手段を通じて搭載され、半導体チップのボンディングパッドに貫通電極が形成され、前記貫通電極にそれぞれ上部及び下部接続パッドを有し、前記下部接続パッドは、前記パッド再配置パターンと電気的に接続される第2半導体チップと、
前記第1封止部上で前記第2半導体チップの側面を覆い包み、前記上部接続パッド及び前記第2半導体チップの上面を外部に露出させる第2封止部とを有し、
前記複数の第1導電性ポストの厚さは、前記第1半導体チップの厚さより薄いことを特徴とする埋め込まれた導電性ポストを備える半導体パッケージ。
- 前記第2半導体チップは、前記第1半導体チップよりサイズが大きいことを特徴とする請求項12に記載の埋め込まれた導電性ポストを備える半導体パッケージ。
- 前記第2半導体チップの上部接続パッドに付着するソルダボールをさらに有することを特徴とする請求項12に記載の埋め込まれた導電性ポストを備える半導体パッケージ。
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