CN101661929B - 芯片封装结构及堆叠式芯片封装结构 - Google Patents

芯片封装结构及堆叠式芯片封装结构 Download PDF

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CN101661929B
CN101661929B CN2009101652181A CN200910165218A CN101661929B CN 101661929 B CN101661929 B CN 101661929B CN 2009101652181 A CN2009101652181 A CN 2009101652181A CN 200910165218 A CN200910165218 A CN 200910165218A CN 101661929 B CN101661929 B CN 101661929B
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substrate
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伯恩·卡尔·厄佩尔特
布莱福特·丁·法克特
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Abstract

本发明提供了一种芯片封装结构及堆叠式芯片封装结构，其中，堆叠式封装结构具有一基板，且此基板的一侧或双侧具有一拟凹槽或一排除区。通过线路层与焊罩层的图案排列以及将芯片配置于凹陷的排除区中，可使导线高度降低以及模盖薄化，进而有效降低堆叠式芯片封装结构的厚度。此外，双面芯片封装结构适于作为行动装置中的层叠封装结构。

Description

芯片封装结构及堆叠式芯片封装结构
技术领域
本发明是涉及一种多芯片封装结构，且特别是有关于一种芯片封装结构及堆叠式芯片封装结构。
背景技术
多芯片封装结构(Multiple-chip package，MCP)一般用在需要高功率、低能量损耗及小尺寸的多种应用上。事实上，可移动或可携式产品需要使用具有多种功能且相当薄的封装结构。
现有技术采用一种具有凹陷的封装基板(凹陷基板)，以通过前述凹陷容置芯片。如图1所示，现有技术具有一凹陷102的一芯片封装结构10主要包括一载板100、一芯片110、多个导线120与一封装胶体130。载板100的凹陷102可容纳芯片110，且芯片110通过多个导线120电性连接至载板100的接垫106。封装胶体130覆盖芯片110并包覆导线120。然而，凹陷基板的成本高，且前述凹陷的设计是挖入导线的布线区中的。
为节省较大的空间，可采用层叠封装(Package on package，PoP)结构，其堆叠一顶封装于一底封装上。然而，随着堆叠的芯片数目持续增加且电子元件的功能逐渐复杂化，降低芯片封装结构的总厚度相当重要。
发明内容
本发明提出一种堆叠式芯片封装结构，其芯片直接配置在未配置有芯片垫与焊罩层的基板上，以有效降低堆叠式芯片封装结构的整体厚度。
本发明另提出一种芯片封装结构，具体为双面芯片封装结构，其芯片分别配置于电路基板的双面的排除区内。双面芯片封装结构对于层叠封装相当有用。
为具体描述本发明的内容，在此提出一种堆叠式芯片封装结构包括一第一封装结构、一第二封装结构以及多个连接结构。第一封装结构可为一双面封装结构，双面封装结构包括一多层基板，多层基板具有配置于基板的二相对表面上的至少二电路层，且第一芯片与第二芯片分别配置在基板的二相对表面上。此外，一焊罩层分别形成在基板的二相对表面，以覆盖第一电路层与第二电路层。通过基板的表面上的电路层与焊罩层的设计，定义出容纳第一芯片的一第一排除区以及容纳一第二芯片的一第二排除区。双面封装结构还包括配置在基板两侧上的一封装胶体，且封装胶体暴露出围绕电路层的焊球垫的焊罩层。
在本发明的一实施例中，连接结构可以为一焊球、一金凸块或一铜柱。
在本发明的一实施例中，第二封装结构可为一单芯片封装结构或一堆叠式芯片封装结构。
为具体描述本发明的内容，在此还提出一种芯片封装结构，包括：
一基板，具有一基底与一第一电路层，该第一电路层配置于该基底的一第一表面上，其中该第一电路层包括多个第一焊球垫与多个第一接触垫，该第一电路层定义出一第一排除区；
一第一焊罩层，部分覆盖该第一电路层，并暴露出该第一排除区、所述多个第一接触垫与所述多个第一焊球垫；
一第一芯片，配置于该基底的该第一表面上，并位于该第一排除区内，并通过多条第一导线电性连接至该基板的所述多个第一接触垫；以及
一第一封装胶体，包覆该第一芯片与所述多个第一导线，并部分覆盖该第一电路层与该第一焊罩层，且暴露出所述多个第一焊球垫与围绕所述多个第一焊球垫的该第一焊罩层。
为具体描述本发明的内容，在此提出一种芯片封装结构包括一基板、一第一焊罩层、一第一芯片以及一第一封装胶体。基板具有一基底与一第一电路层，第一电路层配置于基底的一第一表面上，其中第一电路层包括多个第一焊球垫与多个第一接触垫，第一电路层定义出一第一排除区。第一焊罩层部分覆盖第一电路层，并暴露出第一排除区、第一接触垫与第一焊球垫。第一芯片配置于基底的第一表面上，并位于第一排除区内，并透过多条第一导线电性连接至基板的第一接触垫。第一封装胶体包覆第一芯片与第一导线，并部分覆盖第一电路层与第一焊罩层，且暴露出第一焊球垫与围绕第一焊球垫的第一焊罩层。
就本实施例的堆叠式芯片封装结构而言，由于芯片是配置在在基板的一侧或两侧的凹陷的排除区内的，因此导线高度降低且模盖(mold-cap)较薄，以大幅减少封装结构的厚度。当个别的封装结构的模具高度(mold height)降低，可缩小连接球的尺寸或球距，而这将有利于高密度的立体堆叠式芯片封装结构，并可避免翘曲问题(warpage issues)。
为让本发明的上述和其他特征和优点能更明显易懂，下文特举实施例，并配合附图，作详细说明如下。
附图说明
图1为现有的一种具有一凹槽的芯片封装结构的剖面图；
图2为本发明一实施例的芯片封装结构的剖面图；
图3为本发明另一实施例的双面封装结构的剖面图；
图4为本发明又一实施例的堆叠式芯片封装结构的剖面图。
附图中主要元件符号说明：
10、20-芯片封装结构；            30-双面芯片封装结构；
32、22-封装结构；                40-层叠封装结构；
100-载板；                       102-凹陷；
106、204a、304a、306a-接垫；     110、210-芯片；
120、230-导线；                  130、250、350a、350b-封装胶体；
200、300-基板；                202、302-基底；
204-电路层；                   204b、206b-迹线；
206a、304b、306b-焊球垫；      212、312、322-接点；
215、315、325-粘着剂；         240、242-焊罩层；
304-第一图案化金属层；         306-第二图案化金属层；
310-第一芯片；                 320-第二芯片；
330a-第一导线；                330b-第二导线；
340a-第一图案化焊罩层；        340b-第二图案化焊罩层；
360a-第一焊球；                360b-第二焊球；
460-连接结构；                 A、A1、A2-排除区；
S1-第一表面；                  S2-第二表面；
t-模盖厚度；                   T-支撑高度。
具体实施方式
图2为本发明一实施例的芯片封装结构的剖面图。芯片封装结构20包括一基板200、至少一芯片210、多个导线230与一封装胶体250。基板200可以为一多层基板，其具有至少一基底202与配置于基底202的第一表面S1上的一图案化的金属层。图案化的金属层构成一电路层(或线路层)204，其具有多个接垫204a与迹线(trace)204b。基板200可为一多层电路基板，例如一双层电路基板、一四层电路基板或一六层电路基板。电路层204可通过电镀或是压合铜或铜箔于基底202上的方式形成。基底202可以是一绝缘的核心基底，也可以具有增层电路或叠层电路，其中绝缘材料压合于叠层电路中。
芯片210的接点212通过多个导线230分别电性连接至接垫204a及/或迹线204b。芯片210通过一粘着剂215粘着至基底202的第一表面S1。较佳地，粘着剂215可以为一芯片连接膜(die attach film)，其可选择性地具有填充物以增加导热效果。一图案化的焊罩层240部分覆盖电路层204并暴露出接垫204a与迹线204b，以用于电性连接。焊罩层240可以以模板印刷、滚筒涂布、干膜叠层或旋转涂布的方法形成，用于部分覆盖电路层204。电路层204的被焊罩层240覆盖的部分可避免被后续的焊接与打线接合的制程所污染。封装胶体250覆盖芯片210并包覆导线230。芯片封装结构20的封装胶体250的模盖(mold-cap)厚度t取决于芯片210的厚度与打线接合的高度。
芯片封装结构20的设计使电路层204与焊罩层240位于芯片210的配置区之外。换言之，通过电路层204与焊罩层240的排列，可形成一凹陷区或是一排除区A以容纳芯片210，且芯片210粘着至基底202的排除区A。因此，基板200的位于芯片210正下方的部分未配置有电路层204(包括所谓的芯片垫)与焊罩层240。排除区A的尺寸实质上与芯片的尺寸相等或略大于芯片的尺寸。
基本上，封装胶体250的模盖厚度t可略大于导线230的打线接合高度。由于基底202的排除区A与焊罩层240及/或电路层204的顶面之间存在有一高度差，故排除区A的位置相对较低。相较于现有的封装结构的芯片配置于覆盖有焊罩层的芯片垫上，芯片封装结构20的排除区A可使芯片210的位置降低80微米(可以是现有的封装结构的芯片垫的厚度加焊罩层的厚度的总和)。通过使焊罩层的层数加倍或增加迹线高度，可增加凹陷区(即排除区A)的深度，以使其超过100微米。在本实施例中，凹陷的排除区A可降低芯片210的位置与导线230的位置。由于导线230的高度降低，因此封装胶体250的厚度减少，进而使芯片封装结构20的总厚度大幅减少。
图3为本发明另一实施例的双面封装结构的剖面图。双面芯片封装结构30包括一双面的基板300、一第一芯片310、一第二芯片320、多个第一导线330a、多个第二导线330b以及一封装胶体350a、350b。第一芯片310配置于基板300的一第一表面S1，第二芯片320配置于基板300的一第二表面S2。封装胶体350a、350b分别覆盖第一芯片310与第二芯片320。
在图3中，基板300可以为一多层基板，其具有至少一基底302以及分别配置于基底302的第一表面S1与第二表面S2上的一第一图案化金属层304与一第二图案化金属层306。第一图案化金属层304构成一电路层(线路层)，其具有多个接垫304a与多个焊球垫304b，且第二图案化金属层306构成一电路层(线路层)，其具有多个接垫306a与多个焊球垫306b。多层的电路基板较佳为一四层电路基板(例如四层或1+2+1层基板)或六层电路基板(例如六层、2+2+2或1+4+1层基板)或一多层的电路基板。第一芯片310的接点312通过第一导线330a分别电性连接至接垫304a。第二芯片320的接点322通过第二导线330b分别电性连接至接垫306a。第一芯片310通过一粘着剂315粘着至基底302的第一表面S1，且第二芯片320通过一粘着剂325粘着至基底302的第二表面S2。同样地，粘着剂315、325较佳可以为一芯片连接膜(die attach film)，其可选择性地具有填充物以增加导热效果。
一第一图案化焊罩层340a暴露出接垫304a与焊球接垫304b，以用于电性连接。至少一第一焊球360a配置在焊球垫304b上。一第二图案化焊罩层340b暴露出接垫306a与焊球垫306b，以用于电性连接。至少一第二焊球360b配置在焊球垫306b上。第一图案化焊罩层340a/第二图案化焊罩层340b部分覆盖第一图案化金属层304/第二图案化金属层306以保护迹线(未示出)免于受到后续的焊接或打线接合的影响。封装胶体350a覆盖第一芯片310并包覆第一导线330a，且封装胶体350b覆盖第二芯片320并包覆第二导线330b。封装胶体350a/350b可延伸至第一图案化焊罩层340a/第二图案化焊罩层340b上。
双面芯片封装结构30的设计是使第一图案化金属层304、第二图案化金属层306与第一图案化焊罩层340a/第二图案化焊罩层340b位于第一芯片310的配置区之外，并形成一排除区A1以容纳第一芯片310，第一芯片310粘着至基底302的排除区A1内的第一表面S1。此外，还形成一排除区A2以容纳第二芯片320，第二芯片320粘着至基底302的排除区A2内的第二表面S2。如图3所示，排除区A1实质上与排除区A2切齐。然而，排除区A1与排除区A2的尺寸可以是相等或不相等，且排除区A1与排除区A2可以是排成一列或不排成一列。
在本实施例中，第一图案化焊罩层340a/第二图案化焊罩层340b的厚度定义出第一焊球360a/第二焊球360b的高度以及凹陷区或排除区A1/A2的深度以容纳第一芯片310/第二芯片320。由于凹陷的排除区A1/A2，双面芯片封装结构30具有较低的导线与较薄的封装胶体。
为进一步降低封装结构的尺寸与厚度，上述芯片封装结构20与双面芯片封装结构30可应用在层叠封装结构中。原则上，对于层叠封装结构，上封装结构可通过多个配置于下封装结构的周边区域的焊球连接至下封装结构。举例来说，上封装结构为一单芯片的球栅阵列(ball grid array，BGA)封装或一堆叠式芯片的球栅阵列封装，下封装结构包括一逻辑器件(logic device)或堆叠的芯片。
图4为本发明又一实施例的堆叠式芯片封装结构的剖面图。一双面封装结构可依据层叠封装结构的设计需求(如堆叠的封装结构的数量)而作为底封装结构或顶封装结构。如图4所示，就层叠封装结构40而言，其提供两个独立的封装结构32、22，且封装结构32通过多个连接结构460粘着并电性连接至封装结构22，以形成层叠封装结构40。封装结构22与图2的芯片封装结构20相似，两者的差异之处在于基板200的背面覆盖有一焊罩层242。焊罩层242覆盖迹线206b，但暴露出焊球垫206a以容置连接结构460。封装结构32与图3的双面芯片封装结构30相似，且第一图案化焊罩层340a暴露出焊球垫304b以容置连接结构460。连接至焊球垫206a、304b的连接结构460可以是以回焊(reflowing)的方式所形成的焊球。铜柱或金凸块也可作为连接结构460，其以回焊焊料的方式形成。连接结构460与焊球垫206a、304b的总厚度大于焊罩层242与封装胶体350a的总厚度。
金凸块或铜柱可预先配置于底封装结构的接垫上，然后回焊位于顶封装结构的焊球垫上的焊料胶(solder paste)，如此可使金凸块在移除顶封装结构之后仍然保持完整，进而有利重工(reworking)。或者，金凸块可先配置在顶封装结构的接垫上，然后回焊位于底封装结构的焊球垫上的焊料胶。对于堆叠式封装结构而言，连接结构可配置于底层叠封装结构的顶面的周边。
如上所述，焊罩层242、第一图案化焊罩层340a的厚度定义出凹陷区或排除区的容纳芯片的深度，以及连接结构460的支撑高度T。如果必要的话，焊罩层的厚度可依据芯片厚度或是芯片堆叠的总厚度而做调整，调整的方法可以是增加涂布厚度或使层数加倍。为使封装结构成为层叠封装结构，底封装结构的模盖厚度t必需小于位于堆叠封装结构之间的连接结构的支撑高度T。如此一来，由于底封装结构是扁平(low-profile)的，故可采用尺寸较小的焊球或凸块。再者，由于焊球或凸块的尺寸较小，因此堆叠式芯片封装结构可具有较小的球距(ball pitch)。在另一方面，若使用一般尺寸的焊球或凸块，对于层叠封装结构而言，将多芯片及/或较大的芯片整合至底封装结构中是可行的。此外，易于重工，金凸块与铜柱的主要优点是直径小(相较于焊球)，故使连接结构之间的间距较小，因此可增加单位面积中的连接结构数。
综上所述，在本发明中，可通过将芯片配置在排除区(例如周边线路与焊罩层所定义出的孔洞或开口)中来降低导线高度与薄化模盖，进而有效减少堆叠式芯片封装结构的总厚度。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (11)

1.一种堆叠式芯片封装结构，包括：
一第一封装结构，包括：
一第一基板，具有一基底、一第一电路层与一第二电路层，该第一电路层配置于该基板的一第一表面上，该第二电路层配置于该基板的相对该第一表面的一第二表面上，其中该第一电路层包括多个第一焊球垫，该第一电路层设置有一第一排除区，且该第二电路层设置有一第二排除区；
一第一焊罩层，覆盖该第一电路层，并暴露出该第一排除区与所述多个第一焊球垫；
一第一芯片，配置于该基底的该第一表面上并位于该第一排除区内，且电性连接至该第一基板；
一第一封装胶体，包覆该第一芯片，并部分覆盖该第一电路层与该第一焊罩层，且暴露出所述多个第一焊球垫与围绕所述多个第一焊球垫的该第一焊罩层；
一第二焊罩层，覆盖该第二电路层，并暴露出该第二排除区；
一第二芯片，配置于该基底的该第二表面上并位于该第二排除区内，且电性连接至该第一基板；
一第二封装胶体，包覆该第二芯片；
一第二封装结构，包括：
一第二基板，具有多个第二焊球垫，所述多个第二焊球垫配置于该第二基板的一背面上；
一第三芯片，配置于该第二基板的一承载面上，并电性连接至该第二基板；
一第三焊罩层，覆盖该第二基板的该背面，并暴露出所述多个第二焊球垫；
一第三封装胶体，包覆该第三芯片；以及 
多个连接结构，各连接结构配置于该第一焊球垫与该第二焊球垫之间，以电性连接该第一封装结构与该第二封装结构。
2.根据权利要求1所述的堆叠式芯片封装结构，其中该连接结构为一焊球、一金凸块或一铜柱。
3.根据权利要求1所述的堆叠式芯片封装结构，其中该第一电路层还包括至少一第一接垫，且该第一芯片以打线接合的方式电性连接至该第一接垫。
4.根据权利要求1所述的堆叠式芯片封装结构，其中该第二电路层还包括至少一第二接垫，且该第二芯片以打线接合的方式电性连接至该第二接垫。
5.根据权利要求1所述的堆叠式芯片封装结构，其中该连接结构、该第一焊球垫与该第二焊球垫的总厚度大于该第三焊罩层与该第一封装胶体的总厚度。
6.根据权利要求1所述的堆叠式芯片封装结构，其中该第一电路层与该第一焊罩层仅位于该第一排除区之外，该第二电路层与该第二焊罩层仅位于该第二排除区之外。
7.一种芯片封装结构，包括：
一基板，具有一基底与一第一电路层，该第一电路层配置于该基底的一第一表面上，其中该第一电路层包括多个第一焊球垫与多个第一接触垫，该第一电路层定义出一第一排除区；
一第一焊罩层，部分覆盖该第一电路层，并暴露出该第一排除区、所述多个第一接触垫与所述多个第一焊球垫；
一第一芯片，配置于该基底的该第一表面上，并位于该第一排除区内，并通过多条第一导线电性连接至该基板的所述多个第一接触垫；以及
一第一封装胶体，包覆该第一芯片与所述多个第一导线，并部分覆盖该第一电路层与该第一焊罩层，且暴露出所述多个第一焊球垫与围绕所述多个第一焊球垫的该第一焊罩层。
8.根据权利要求7所述的芯片封装结构，还包括： 
多个连接结构，配置于所述多各第一焊球垫上，其中该连接结构为一焊球、一金凸块或一铜柱。
9.根据权利要求7所述的芯片封装结构，还包括：
一第二电路层，配置于该基底的相对于该第一表面的一第二表面上，其中该第二电路层包括多个第二焊球垫与多个第二接触垫，该第二电路层设置有一第二排除区；
一第二焊罩层，部分覆盖该第二电路层，并暴露出所述多个第二排除区、所述多个第二接触垫与所述多个第二焊球垫；
一第二芯片，配置于该基底的该第二表面上，并位于该第二排除区中，且通过多条第二导线电性连接至该基板的所述多个第二接触垫；以及
一第二封装胶体，包覆该第二芯片与所述多个第二导线，并部分覆盖该第二电路层与该第二焊罩层，且暴露出所述多个第二焊球垫与围绕该些第二焊球垫的该第二焊罩层。
10.根据权利要求9所述的芯片封装结构，还包括：
多个连接结构，配置于所述多个第二焊球垫上，其中该连接结构为一焊球、一金凸块或一铜柱。
11.根据权利要求9所述的芯片封装结构，其中该第一电路层与该第一焊罩层仅位于该第一排除区之外，且该第二电路层与该第二焊罩层仅位于该第二排除区之外。 
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