JP2007531981A - 信頼性向上のための半導体デバイスのパッケージング - Google Patents
信頼性向上のための半導体デバイスのパッケージング Download PDFInfo
- Publication number
- JP2007531981A JP2007531981A JP2006520255A JP2006520255A JP2007531981A JP 2007531981 A JP2007531981 A JP 2007531981A JP 2006520255 A JP2006520255 A JP 2006520255A JP 2006520255 A JP2006520255 A JP 2006520255A JP 2007531981 A JP2007531981 A JP 2007531981A
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- Prior art keywords
- package
- radiation
- shielding
- integrated circuit
- circuit
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49139—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture
- Y10T29/4914—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture with deforming of lead or terminal
- Y10T29/49142—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture with deforming of lead or terminal including metal fusion
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
- Y10T29/49149—Assembling terminal to base by metal fusion bonding
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Abstract
Description
Claims (50)
- 回路パッケージ、該回路パッケージに結合された放射線遮へいベース、および該放射線遮へいベースに結合された回路ダイを含む複数のパッケージ層と、
該複数のパッケージ層に結合された放射線遮へい蓋と、
を具備する放射線遮へい集積回路デバイスであって、
前記回路ダイが、回路ダイの全許容線量よりも多い放射線量から遮へいされ、
前記複数のパッケージ層は相互に積み重ねられて、第1のパッケージ層の下部が第2のパッケージ層の上部として作用する、放射線遮へい集積回路デバイス。 - 前記放射線遮へいベースに結合された基板と、
前記基板に結合された複数の回路ダイと、
を更に具備する、請求項1に記載の放射線遮へい集積回路デバイス。 - 前記複数の回路ダイを前記放射線遮へいベースに結合する複数の熱バイアを更に前記基板内に具備する、請求項2に記載の放射線遮へい集積回路デバイス。
- 更に、前記複数の放射線遮へいベースの第1のものを、前記複数の放射線遮へいベースの第2のものに結合する熱接続を前記複数のパッケージ層間に具備する、請求項2に記載の放射線遮へい集積回路デバイス。
- 複数の放射線遮へいベースの第1のものが、放射線遮へい集積回路デバイスのヒートシンクとして作用する、請求項2に記載の放射線遮へい集積回路デバイス。
- 前記複数のパッケージ層には、はんだボールの1つが取り付けられ、はんだペースト上で覆う、請求項1に記載の放射線遮へい集積回路デバイス。
- 前記放射線遮へい蓋が高Z材料である、請求項1に記載の放射線遮へい集積回路デバイス。
- 前記放射線遮へいベースが高Z材料である、請求項1に記載の放射線遮へい集積回路デバイス。
- 前記放射線遮へいベースがヒートシンクとして作用する、請求項1に記載の放射線遮へい集積回路デバイス。
- 前記放射線遮へい蓋が高Z材料および低Z材料を具備する、請求項1に記載の放射線遮へい集積回路デバイス。
- 前記放射線遮へいベースが高Z材料および低Z材料を具備する、請求項1に記載の放射線遮へい集積回路デバイス。
- 回路パッケージ、および該回路パッケージに結合された放射線遮へい蓋を含む複数のパッケージ層と、
前記回路パッケージに結合された回路ダイと、
前記複数のパッケージ層に結合された放射線遮へいベースと、
を具備する放射線遮へい集積回路デバイスであって、
前記回路ダイが、回路ダイの全許容線量よりも多い放射線量から遮へいされ、
前記複数のパッケージ層が相互に積み重ねられる、放射線遮へい集積回路デバイス。 - 前記回路パッケージに結合された基板と、
前記基板に結合された複数の回路ダイと、
を更に具備する、請求項12に記載の放射線遮へい集積回路デバイス。 - 前記基板を前記回路パッケージに接続する複数のはんだボールを更に具備する、請求項13に記載の放射線遮へい集積回路デバイス。
- 前記複数のパッケージ層がはんだボールによって取り付けられる、請求項12に記載の放射線遮へい集積回路デバイス。
- 前記放射線遮へい蓋が高Z材料である、請求項12に記載の放射線遮へい集積回路デバイス。
- 前記放射線遮へいベースが高Z材料である、請求項12に記載の放射線遮へい集積回路デバイス。
- 前記放射線遮へいベースがヒートシンクとして作用する、請求項12に記載の放射線遮へい集積回路デバイス。
- 前記複数のパッケージ層が気密封止される、請求項12に記載の放射線遮へい集積回路デバイス。
- 前記放射線遮へい蓋が高Z材料および低Z材料を具備する、請求項12に記載の放射線遮へい集積回路デバイス。
- 前記放射線遮へいベースが高Z材料および低Z材料を具備する、請求項12に記載の放射線遮へい集積回路デバイス。
- 集積回路デバイスを遮へいする方法であって、
第1の放射線遮へいベース、第1のパッケージ、および第1の回路ダイを含む第1のパッケージ層を形成し、
第2の放射線遮へいベース、第2のパッケージ、および第2の回路ダイを含む第2のパッケージ層を形成し、
前記第1のパッケージ層の下部を前記第2のパッケージ層の上部に結合し、
前記第1のパッケージ層に蓋を結合する、
ことを含む、方法。 - 高Z材料から前記蓋を形成することを更に含む、請求項22に記載の集積回路デバイスを遮へいする方法。
- 高Z材料から前記第1の放射線遮へいベースおよび前記第2の放射線遮へいベースを形成することを更に含む、請求項22に記載の集積回路デバイスを遮へいする方法。
- 前記第1の回路ダイが、前記第1の回路ダイの全許容線量よりも少ない放射線量を受け取る、請求項22に記載の集積回路デバイスを遮へいする方法。
- 前記第2の回路ダイが、前記第2の回路ダイの全許容線量よりも少ない放射線量を受け取る、請求項22に記載の集積回路デバイスを遮へいする方法。
- 回路パッケージ、該回路パッケージに結合された熱伝導ベース、および該熱伝導ベースに結合された回路ダイを含む複数のパッケージ層を具備する高密度回路パッケージであって、
前記回路ダイが、熱バイアを介して前記熱伝導ベースへ結合される、回路パッケージ。 - 前記熱伝導ベースに結合された熱層コネクタを更に具備する、請求項27に記載の回路パッケージ。
- 前記回路ダイがメモリを含む、請求項28に記載の回路パッケージ。
- 前記熱伝導ベースが放射線遮へい材料を含む、請求項27に記載の回路パッケージ。
- 前記回路ダイが、回路ダイの全許容線量よりも多い放射線量から遮へいされる、請求項30に記載の回路パッケージ。
- 複数の層の上部に結合された熱伝導蓋を更に具備する、請求項27に記載の回路パッケージ。
- 前記回路パッケージがセラミックを含む、請求項27に記載の回路パッケージ。
- 集積回路デバイスを遮へいする方法であって、
第1の放射線遮へい蓋、第1のパッケージ、および第1の回路ダイを含む第1のパッケージ層を形成し、
第2の放射線遮へい蓋、第2のパッケージ、および第2の回路ダイを含む第2のパッケージ層を形成し、
前記第1のパッケージ層の上部を前記第2のパッケージ層の下部に結合し、
前記第1のパッケージ層にベースを結合する、
ことを含む、方法。 - 高Z材料から前記ベースを形成することを更に含む、請求項34に記載の集積回路デバイスを遮へいする方法。
- 高Z材料から前記第1の放射線遮へい蓋および前記第2の放射線遮へい蓋を形成することを更に含む、請求項34に記載の集積回路デバイスを遮へいする方法。
- 前記第1の回路ダイが、第1の回路ダイの全許容線量よりも少ない放射線量を受け取る、請求項34に記載の集積回路デバイスを遮へいする方法。
- 前記第2の回路ダイが、第2の回路ダイの全許容線量よりも少ない放射線量を受け取る、請求項34に記載の集積回路デバイスを遮へいする方法。
- パッケージの異なった層の中にある複数の集積回路ダイを放射線から保護する高信頼性パッケージを作る方法であって、
パッケージの第1の層の中に第1の回路ダイを配置するステップと、
前記第1の回路ダイの全許容線量よりも多い放射線量から蓋を介して第1の回路ダイを十分に遮へいするため、該パッケージの第1の層のために蓋を提供するステップと、
該パッケージの内部層の中に第2の回路ダイを配置するステップと、
該第2の回路ダイの全許容線量よりも多い放射線量から蓋および内部遮へい層を介して第2の回路ダイを遮へいするため、蓋および内部遮へい層の遮へいが十分となるように内部パッケージのために内部遮へい層を提供するステップと、を含む方法。 - 前記第1の回路ダイが、前記第2の回路ダイの全許容線量よりも大きい全許容線量を有する、請求項39に記載の方法。
- 前記パッケージの上にベースを置くことを更に含む、請求項39に記載の方法。
- 高密度回路パッケージを作る方法であって、
回路パッケージ、該回路パッケージに結合された熱伝導ベース、および該熱伝導ベースに結合された回路ダイを含む複数のパッケージ層を形成し、
熱バイアを介して前記熱伝導ベースに前記回路ダイを結合する、
ことを含む方法。 - 前記複数のパッケージ層の1つに熱伝導蓋を結合することを更に含む、請求項42に記載の方法。
- 前記回路ダイがメモリである、請求項42に記載の方法。
- 銅−タングステンから前記熱伝導ベースを形成することを更に含む、請求項42に記載の方法。
- 高密度回路パッケージを作る方法であって、
熱伝導ベースを第1のパッケージ層に結合し、
第1の回路ダイを前記熱伝導ベースに結合し、
第2のパッケージ層を前記第1のパッケージ層に結合し、
第2の回路ダイを前記熱伝導ベースに結合する、
ことを含む方法。 - 前記第1のパッケージ層と前記第2のパッケージ層との間に熱伝導層を結合することを更に含む、請求項46に記載の方法。
- 熱バイアを使用して前記熱伝導層を前記熱伝導ベースに結合することを更に含む、請求項47に記載の方法。
- 熱伝導蓋を前記第2のパッケージ層に結合することを更に含む、請求項47に記載の方法。
- 熱バイアを使用して前記熱伝導蓋を前記熱伝導層に結合することを更に含む、請求項49に記載の方法。
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PCT/US2004/022344 WO2005010937A2 (en) | 2003-07-16 | 2004-07-12 | Packaging of semiconductor devices for incrased reliability |
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- 2004-07-12 CN CN200480020214XA patent/CN1823561B/zh not_active Expired - Fee Related
- 2004-07-12 JP JP2006520255A patent/JP4795948B2/ja not_active Expired - Fee Related
- 2004-07-12 EP EP04778051.5A patent/EP1647173A4/en not_active Withdrawn
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- 2006-11-13 US US11/559,140 patent/US7696610B2/en not_active Expired - Lifetime
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Also Published As
Publication number | Publication date |
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US7696610B2 (en) | 2010-04-13 |
WO2005010937A2 (en) | 2005-02-03 |
EP1647173A2 (en) | 2006-04-19 |
US7191516B2 (en) | 2007-03-20 |
CN1823561B (zh) | 2011-09-07 |
EP1647173A4 (en) | 2017-12-27 |
CN101345238A (zh) | 2009-01-14 |
WO2005010937A3 (en) | 2005-05-26 |
KR20060113632A (ko) | 2006-11-02 |
US20050011656A1 (en) | 2005-01-20 |
US20080251895A1 (en) | 2008-10-16 |
HK1127162A1 (en) | 2009-09-18 |
US20100155912A1 (en) | 2010-06-24 |
CN1823561A (zh) | 2006-08-23 |
KR101059918B1 (ko) | 2011-08-29 |
US8018739B2 (en) | 2011-09-13 |
JP4795948B2 (ja) | 2011-10-19 |
CN101345238B (zh) | 2010-12-15 |
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