DE68923732T2 - Verfahren zur Herstellung einer elektrischen Vorrichtung. - Google Patents
Verfahren zur Herstellung einer elektrischen Vorrichtung.Info
- Publication number
- DE68923732T2 DE68923732T2 DE68923732T DE68923732T DE68923732T2 DE 68923732 T2 DE68923732 T2 DE 68923732T2 DE 68923732 T DE68923732 T DE 68923732T DE 68923732 T DE68923732 T DE 68923732T DE 68923732 T2 DE68923732 T2 DE 68923732T2
- Authority
- DE
- Germany
- Prior art keywords
- manufacturing
- electrical device
- electrical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Formation Of Insulating Films (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63124360A JPH01292846A (ja) | 1988-05-19 | 1988-05-19 | 電子装置作製方法 |
JP63124361A JPH01292833A (ja) | 1988-05-19 | 1988-05-19 | 電子装置作製方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE68923732D1 DE68923732D1 (de) | 1995-09-14 |
DE68923732T2 true DE68923732T2 (de) | 1996-01-18 |
Family
ID=26461041
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE68923732T Expired - Fee Related DE68923732T2 (de) | 1988-05-19 | 1989-05-18 | Verfahren zur Herstellung einer elektrischen Vorrichtung. |
Country Status (5)
Country | Link |
---|---|
US (1) | US5096851A (de) |
EP (1) | EP0342681B1 (de) |
KR (1) | KR900019177A (de) |
CN (1) | CN1020317C (de) |
DE (1) | DE68923732T2 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102016109349A1 (de) * | 2016-05-20 | 2017-11-23 | Infineon Technologies Ag | Chipgehäuse, verfahren zum bilden eines chipgehäuses und verfahren zum bilden eines elektrischen kontakts |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5451550A (en) * | 1991-02-20 | 1995-09-19 | Texas Instruments Incorporated | Method of laser CVD seal a die edge |
US6613978B2 (en) * | 1993-06-18 | 2003-09-02 | Maxwell Technologies, Inc. | Radiation shielding of three dimensional multi-chip modules |
US5880403A (en) | 1994-04-01 | 1999-03-09 | Space Electronics, Inc. | Radiation shielding of three dimensional multi-chip modules |
US6720493B1 (en) | 1994-04-01 | 2004-04-13 | Space Electronics, Inc. | Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages |
US6455864B1 (en) | 1994-04-01 | 2002-09-24 | Maxwell Electronic Components Group, Inc. | Methods and compositions for ionizing radiation shielding |
US6261508B1 (en) | 1994-04-01 | 2001-07-17 | Maxwell Electronic Components Group, Inc. | Method for making a shielding composition |
KR100202668B1 (ko) * | 1996-07-30 | 1999-07-01 | 구본준 | 크랙 방지를 위한 반도체 패키지와 그 제조방법 및 제조장치 |
US6368899B1 (en) * | 2000-03-08 | 2002-04-09 | Maxwell Electronic Components Group, Inc. | Electronic device packaging |
US6441503B1 (en) | 2001-01-03 | 2002-08-27 | Amkor Technology, Inc. | Bond wire pressure sensor die package |
US6432737B1 (en) | 2001-01-03 | 2002-08-13 | Amkor Technology, Inc. | Method for forming a flip chip pressure sensor die package |
US6661080B1 (en) | 2001-06-28 | 2003-12-09 | Amkor Technology, Inc. | Structure for backside saw cavity protection |
US6586824B1 (en) | 2001-07-26 | 2003-07-01 | Amkor Technology, Inc. | Reduced thickness packaged electronic device |
US6399418B1 (en) * | 2001-07-26 | 2002-06-04 | Amkor Technology, Inc. | Method for forming a reduced thickness packaged electronic device |
US7382043B2 (en) * | 2002-09-25 | 2008-06-03 | Maxwell Technologies, Inc. | Method and apparatus for shielding an integrated circuit from radiation |
US20040119172A1 (en) | 2002-12-18 | 2004-06-24 | Downey Susan H. | Packaged IC using insulated wire |
US7191516B2 (en) * | 2003-07-16 | 2007-03-20 | Maxwell Technologies, Inc. | Method for shielding integrated circuit devices |
US9953952B2 (en) * | 2008-08-20 | 2018-04-24 | Infineon Technologies Ag | Semiconductor device having a sealant layer including carbon directly contact the chip and the carrier |
DE102016106137B4 (de) * | 2016-04-04 | 2023-12-28 | Infineon Technologies Ag | Elektronikvorrichtungsgehäuse umfassend eine dielektrische Schicht und ein Kapselungsmaterial |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4056681A (en) * | 1975-08-04 | 1977-11-01 | International Telephone And Telegraph Corporation | Self-aligning package for integrated circuits |
US4091407A (en) * | 1976-11-01 | 1978-05-23 | Rca Corporation | Combination glass/low temperature deposited Siw Nx Hy O.sub.z |
JPS55163850A (en) * | 1979-06-08 | 1980-12-20 | Fujitsu Ltd | Semiconductor device |
JPS5627941A (en) * | 1979-08-17 | 1981-03-18 | Hitachi Ltd | Manufacture of semiconductor device |
JPS56108247A (en) * | 1980-01-31 | 1981-08-27 | Sanyo Electric Co Ltd | Semiconductor device |
JPS5745259A (en) * | 1980-09-01 | 1982-03-15 | Hitachi Ltd | Resin sealing type semiconductor device |
JPS57210646A (en) * | 1981-06-19 | 1982-12-24 | Seiko Epson Corp | Resin-sealed semiconductor device |
JPS59231810A (ja) * | 1983-06-14 | 1984-12-26 | Toshiba Corp | 電子ビ−ム露光装置 |
JPS59231840A (ja) * | 1983-06-14 | 1984-12-26 | Semiconductor Energy Lab Co Ltd | 半導体装置作成方法 |
JPS601846A (ja) * | 1983-06-18 | 1985-01-08 | Toshiba Corp | 多層配線構造の半導体装置とその製造方法 |
JPS60107841A (ja) * | 1983-11-16 | 1985-06-13 | Hitachi Ltd | 窒化シリコン膜の形成方法 |
JPS61148824A (ja) * | 1984-12-21 | 1986-07-07 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JPS61258436A (ja) * | 1985-05-13 | 1986-11-15 | Nec Corp | 半導体装置の製造方法 |
US4729010A (en) * | 1985-08-05 | 1988-03-01 | Hitachi, Ltd. | Integrated circuit package with low-thermal expansion lead pieces |
KR920003431B1 (ko) * | 1988-02-05 | 1992-05-01 | 가부시끼가이샤 한도다이 에네르기 겐뀨쇼 | 플라즈마 처리 방법 및 장치 |
-
1989
- 1989-05-18 KR KR1019890006744A patent/KR900019177A/ko not_active Application Discontinuation
- 1989-05-18 EP EP89108973A patent/EP0342681B1/de not_active Expired - Lifetime
- 1989-05-18 DE DE68923732T patent/DE68923732T2/de not_active Expired - Fee Related
- 1989-05-19 CN CN89103436A patent/CN1020317C/zh not_active Expired - Fee Related
-
1990
- 1990-08-24 US US07/572,331 patent/US5096851A/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102016109349A1 (de) * | 2016-05-20 | 2017-11-23 | Infineon Technologies Ag | Chipgehäuse, verfahren zum bilden eines chipgehäuses und verfahren zum bilden eines elektrischen kontakts |
US10461056B2 (en) | 2016-05-20 | 2019-10-29 | Infineon Technologies Ag | Chip package and method of forming a chip package with a metal contact structure and protective layer, and method of forming an electrical contact |
Also Published As
Publication number | Publication date |
---|---|
KR900019177A (ko) | 1990-12-24 |
DE68923732D1 (de) | 1995-09-14 |
EP0342681B1 (de) | 1995-08-09 |
EP0342681A2 (de) | 1989-11-23 |
CN1039504A (zh) | 1990-02-07 |
EP0342681A3 (en) | 1990-07-04 |
US5096851A (en) | 1992-03-17 |
CN1020317C (zh) | 1993-04-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |