DE69004201D1 - Verfahren zur Herstellung einer SOI-Halbleiteranordnung. - Google Patents

Verfahren zur Herstellung einer SOI-Halbleiteranordnung.

Info

Publication number
DE69004201D1
DE69004201D1 DE90402260T DE69004201T DE69004201D1 DE 69004201 D1 DE69004201 D1 DE 69004201D1 DE 90402260 T DE90402260 T DE 90402260T DE 69004201 T DE69004201 T DE 69004201T DE 69004201 D1 DE69004201 D1 DE 69004201D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
soi semiconductor
soi
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE90402260T
Other languages
English (en)
Other versions
DE69004201T2 (de
Inventor
Hiroshi Fujioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69004201D1 publication Critical patent/DE69004201D1/de
Application granted granted Critical
Publication of DE69004201T2 publication Critical patent/DE69004201T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76267—Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
DE90402260T 1989-08-19 1990-08-07 Verfahren zur Herstellung einer SOI-Halbleiteranordnung. Expired - Fee Related DE69004201T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1213428A JPH0377329A (ja) 1989-08-19 1989-08-19 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69004201D1 true DE69004201D1 (de) 1993-12-02
DE69004201T2 DE69004201T2 (de) 1994-03-03

Family

ID=16639066

Family Applications (1)

Application Number Title Priority Date Filing Date
DE90402260T Expired - Fee Related DE69004201T2 (de) 1989-08-19 1990-08-07 Verfahren zur Herstellung einer SOI-Halbleiteranordnung.

Country Status (4)

Country Link
US (1) US5061642A (de)
EP (1) EP0419302B1 (de)
JP (1) JPH0377329A (de)
DE (1) DE69004201T2 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69125886T2 (de) 1990-05-29 1997-11-20 Semiconductor Energy Lab Dünnfilmtransistoren
JPH04198095A (ja) * 1990-11-28 1992-07-17 Fujitsu Ltd 化合物半導体薄膜成長方法
JP2546745B2 (ja) * 1991-03-15 1996-10-23 信越半導体株式会社 半導体デバイスの製造方法
GB2258356B (en) * 1991-07-31 1995-02-22 Metron Designs Ltd Method and apparatus for conditioning an electronic component having a characteristic subject to variation with temperature
JP3173854B2 (ja) 1992-03-25 2001-06-04 株式会社半導体エネルギー研究所 薄膜状絶縁ゲイト型半導体装置の作製方法及び作成された半導体装置
JPH0684925A (ja) * 1992-07-17 1994-03-25 Toshiba Corp 半導体基板およびその処理方法
JPH0799295A (ja) * 1993-06-07 1995-04-11 Canon Inc 半導体基体の作成方法及び半導体基体
JP3173926B2 (ja) 1993-08-12 2001-06-04 株式会社半導体エネルギー研究所 薄膜状絶縁ゲイト型半導体装置の作製方法及びその半導体装置
US6331717B1 (en) 1993-08-12 2001-12-18 Semiconductor Energy Laboratory Co. Ltd. Insulated gate semiconductor device and process for fabricating the same
JP2666757B2 (ja) * 1995-01-09 1997-10-22 日本電気株式会社 Ｓｏｉ基板の製造方法
JP3451908B2 (ja) * 1997-11-05 2003-09-29 信越半導体株式会社 Ｓｏｉウエーハの熱処理方法およびｓｏｉウエーハ
JP2003289051A (ja) * 1998-09-10 2003-10-10 Nippon Steel Corp Ｓｉｍｏｘ基板およびその製造方法
DE19952015A1 (de) * 1999-10-28 2001-05-17 Steag Rtp Systems Gmbh Verfahren zum thermischen Behandeln von Objekten
WO2001082342A1 (en) * 2000-04-26 2001-11-01 Wafermasters Incorporated Gas assisted rapid thermal annealing
US20100085713A1 (en) * 2008-10-03 2010-04-08 Balandin Alexander A Lateral graphene heat spreaders for electronic and optoelectronic devices and circuits
US8846505B2 (en) * 2009-03-09 2014-09-30 Skokie Swift Corporation Method of growing semiconductor micro-crystalline islands on an amorphous substrate
WO2014018776A1 (en) 2012-07-26 2014-01-30 Massachusetts Institute Of Technology Photonic integrated circuits based on quantum cascade structures
US10170315B2 (en) 2013-07-17 2019-01-01 Globalfoundries Inc. Semiconductor device having local buried oxide
US9252272B2 (en) 2013-11-18 2016-02-02 Globalfoundries Inc. FinFET semiconductor device having local buried oxide
US20150263040A1 (en) 2014-03-17 2015-09-17 Silicon Storage Technology, Inc. Embedded Memory Device With Silicon-On-Insulator Substrate, And Method Of Making Same
US10752492B2 (en) 2014-04-01 2020-08-25 Agiltron, Inc. Microelectromechanical displacement structure and method for controlling displacement
US9431407B2 (en) 2014-09-19 2016-08-30 Silicon Storage Technology, Inc. Method of making embedded memory device with silicon-on-insulator substrate
US9466729B1 (en) 2015-05-08 2016-10-11 Qualcomm Incorporated Etch stop region based fabrication of bonded semiconductor structures
US9634020B1 (en) 2015-10-07 2017-04-25 Silicon Storage Technology, Inc. Method of making embedded memory device with silicon-on-insulator substrate
US10790292B2 (en) 2018-05-14 2020-09-29 Silicon Storage Technology, Inc. Method of making embedded memory device with silicon-on-insulator substrate
US10797163B1 (en) * 2019-04-29 2020-10-06 International Business Machines Corporation Leakage control for gate-all-around field-effect transistor devices

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0060676B1 (de) * 1981-03-11 1990-07-25 Fujitsu Limited Verfahren zur Herstellung einer Halbleiteranordnung mit Ausglühen eines Halbleiterkörpers
JPS6031231A (ja) * 1983-07-29 1985-02-18 Toshiba Corp 半導体基体の製造方法
EP0165364B1 (de) * 1984-06-20 1988-09-07 International Business Machines Corporation Verfahren zum Standardisieren und Stabilisieren von Halbleiterscheiben
US4622082A (en) * 1984-06-25 1986-11-11 Monsanto Company Conditioned semiconductor substrates
US4676841A (en) * 1985-09-27 1987-06-30 American Telephone And Telegraph Company, At&T Bell Laboratories Fabrication of dielectrically isolated devices utilizing buried oxygen implant and subsequent heat treatment at temperatures above 1300° C.
US4837172A (en) * 1986-07-18 1989-06-06 Matsushita Electric Industrial Co., Ltd. Method for removing impurities existing in semiconductor substrate
US4749660A (en) * 1986-11-26 1988-06-07 American Telephone And Telegraph Company, At&T Bell Laboratories Method of making an article comprising a buried SiO2 layer
US4786608A (en) * 1986-12-30 1988-11-22 Harris Corp. Technique for forming electric field shielding layer in oxygen-implanted silicon substrate
US4784964A (en) * 1987-10-19 1988-11-15 Motorola Inc. EPI defect reduction using rapid thermal annealing
US4868133A (en) * 1988-02-11 1989-09-19 Dns Electronic Materials, Inc. Semiconductor wafer fabrication with improved control of internal gettering sites using RTA
US4804633A (en) * 1988-02-18 1989-02-14 Northern Telecom Limited Silicon-on-insulator substrates annealed in polysilicon tube

Also Published As

Publication number Publication date
EP0419302B1 (de) 1993-10-27
US5061642A (en) 1991-10-29
DE69004201T2 (de) 1994-03-03
EP0419302A1 (de) 1991-03-27
JPH0377329A (ja) 1991-04-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee