US20040119172A1 - Packaged IC using insulated wire - Google Patents

Packaged IC using insulated wire Download PDF

Info

Publication number
US20040119172A1
US20040119172A1 US10/323,293 US32329302A US2004119172A1 US 20040119172 A1 US20040119172 A1 US 20040119172A1 US 32329302 A US32329302 A US 32329302A US 2004119172 A1 US2004119172 A1 US 2004119172A1
Authority
US
United States
Prior art keywords
oxide
packaged
insulator coating
conductive core
wires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/323,293
Inventor
Susan Downey
Peter Harper
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Priority to US10/323,293 priority Critical patent/US20040119172A1/en
Assigned to MOTOROLA, INC. reassignment MOTOROLA, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DOWNEY, SUSAN H., HARPER, PETER R.
Priority to AU2003270913A priority patent/AU2003270913A1/en
Priority to PCT/US2003/030593 priority patent/WO2004061959A1/en
Priority to TW092128310A priority patent/TWI317541B/en
Assigned to FREESCALE SEMICONDUCTOR, INC. reassignment FREESCALE SEMICONDUCTOR, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MOTOROLA, INC
Priority to US10/847,775 priority patent/US7138328B2/en
Publication of US20040119172A1 publication Critical patent/US20040119172A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/43Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/745Apparatus for manufacturing wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/43Manufacturing methods
    • H01L2224/438Post-treatment of the connector
    • H01L2224/4382Applying permanent coating, e.g. in-situ coating
    • H01L2224/43827Chemical vapour deposition [CVD], e.g. laser CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/45565Single coating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/45599Material
    • H01L2224/45686Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/45599Material
    • H01L2224/45693Material with a principal constituent of the material being a solid not provided for in groups H01L2224/456 - H01L2224/45691, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/4813Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L2224/745Apparatus for manufacturing wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7865Means for transporting the components to be connected
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
    • H01L2224/85205Ultrasonic bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01012Magnesium [Mg]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01023Vanadium [V]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01024Chromium [Cr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0104Zirconium [Zr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01073Tantalum [Ta]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S228/00Metal fusion bonding
    • Y10S228/904Wire bonding

Definitions

  • This invention relates in general to packaged integrated circuits (ICs) in general and specifically to insulated wires for packaged ICs.
  • Packaged ICs utilize wires for electrically coupling conductive structures encapsulated in an IC package.
  • wires may be used to electrically connect bond pads of an integrated circuit (IC) die with devices of a package substrate.
  • Wires may also be used to cross connect bond pads of a die in the package or to cross connect bond fingers of a substrate.
  • a problem with using wires in a packaged IC is that a wire may unintentionally short to other conductive structures of the packaged IC such as, e.g., other wires, pads, fingers, or the die. This shorting may occur during IC die encapsulation as, for example, from “sweeping,” where the injection or transfer of the liquid molding encapsulant moves the wires against another conductive structure.
  • An insulator coating may be applied to wires utilized in an IC package.
  • Such insulator coatings need to be compatible with wire bonding processes and provide the insulative electrical properties as desired. What is needed is an improved wire insulator coating for packaged ICs.
  • FIG. 1 is a top view of one embodiment of an IC die attached to a package substrate and including wires for electrically connecting electrically conductive structures of the IC die and substrate according to the present invention.
  • FIG. 2 is partial cut away side view of one embodiment of a packaged IC according to the present invention.
  • FIG. 3 is a cross sectional view of one embodiment of a wire with an insulator coating according to the present invention.
  • FIG. 4 is a view of one embodiment of a chemical vapor deposition system for coating a conductive core with an insulator coating according to the present invention.
  • FIG. 5 is a flow chart setting forth one embodiment of a method of manufacturing a packaged IC according to the present invention.
  • FIG. 1 is a top view of one embodiment of an IC die 114 attached to package substrate 112 prior to an encapsulation of IC die 114 .
  • Wires e.g. 120
  • Wires are utilized to electrically connect bond pads (e.g. 118 ) on IC die 114 with bond fingers (e.g. 116 ) of package substrate 112 .
  • Wires are also utilized for electrically connecting bond fingers of substrate 112 to each other.
  • wire 132 electrically connects substrate bond finger 142 with bond finger 144 .
  • wires can be utilized to electrically connect IC bond pads with each other.
  • wire 134 electrically connects bond pad 150 with bond pad 152 .
  • the wires shown in FIG. 1 have an insulator coating surrounding a conductive core for preventing the wires from shorting to other wires or other conductive structures of the packaged IC ( 201 of FIG. 2).
  • the insulative coating on wires 132 and 136 would prevent the conductive cores of those wires from shorting to each other in the event that the wires contact each other.
  • insulator coating 304 surrounds conductive core 306 .
  • the conductive core is made from a metal such as copper, gold, or aluminum.
  • insulator coating 304 includes an inorganic covalently-bonded substance having insulative properties such that the thickness of the coating is sufficient to meet the insulative requirements of the IC package.
  • An inorganic covalently-bonded substance is a covalently-bonded substance that does not include a compound with carbon and another element.
  • Examples of an inorganic covalently-bonded substance that have insulative properties such that it can be used in the insulative coating include nitrides such as, e.g. silicon nitride, aluminum nitride, and boron nitride; oxides such as e.g.
  • the oxides that may be used are not oxides of the material of the conductive core.
  • the insulative coating is applied by a chemical vapor deposition (CVD) process such as, e.g., a plasma enhanced CVD (PECVD) process prior to the attachment of the wire to the electrically conductive structure of the die and substrate.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced CVD
  • the inorganic covalently-bonded substance of the insulator coating has a high breakdown voltage such that it that can provide the desired insulative properties with a relatively thin coating.
  • the insulative coating include stoichiometric silicon oxide (SiO2).
  • SiO2 stoichiometric silicon oxide
  • a wire having a conductive core of gold would have a insulator coating of SiO2 having a thickness of 15-10,000 angstroms.
  • the thickness of the insulator coating should be minimized to allow the wire to be bent without cracking the insulator coating.
  • FIG. 2 is a partial cutaway view of a packaged IC 201 that includes substrate 112 and IC die 114 encapsulated in an encapsulant 224 .
  • Wire 120 electrically connects bond pad 118 to substrate bond finger 116 .
  • Bond finger 116 is connected to plated via 214 , which is connected to ball grid array (BGA) pad 212 .
  • Ball 210 is electrically connected to pad 212 and as is utilized for the electrically coupling IC die 114 to external devices.
  • BGA ball grid array
  • Wire 120 is attached to pad 118 by thermosonically bonding a formed ball 202 to pad 118 and wire 120 . Wire is then routed to bond finger 116 where it is attached to bond finger 116 by wedge bonding wire 120 to bond finger 116 and then cutting the excess wire from bond finger 116 . In other embodiments, both ends of the wire are attached by wedge bonding or by other conventional wire attachment techniques.
  • the insulator coating including an inorganic covalently-bonded substance has a material hardness greater than and is more brittle than the conductive core. Accordingly the insulator coating provides an “egg shell” effect with respect to the conductive core. The brittle nature of the insulator coating may aid in the wedge bonding of the wire to a conductive structure. With these embodiments, the insulator coating material easily cracks at the point of attachment wherein small particles of the insulator become embedded in the softer conductive core material. Also, in some embodiments, the material hardness of the insulator coating aids in ability of the coating to withstand wear from friction such as e.g. from two wires rubbing together during e.g. the bonding or encapsulation process.
  • the melting point of the inorganic covalently-bonded substance of the insulator coating is higher than that of the conductive core material.
  • the conductive core material melts wherein insulator coating material covering the melted portion of the core becomes embedded as particulate matter in the ball.
  • the insulator coating material has a higher melting point than the conductive core material, the insulator coating remains on the portions of the wire whose conductive core was not melted.
  • wires having an insulator coatings may be utilized in other types of packaged ICs.
  • wires with insulator coatings may be utilized to connect die pads of multiple IC dies located in a multi die IC package (such as, e.g., in a stacked die or side by side die packaged IC).
  • Wires having insulator coatings may also be used in leaded packaged IC to connect the bond pads of the IC die to the lead frame of the leaded packaged IC.
  • Wires having insulator coatings may also be used in other types of packages such as e.g.
  • quad flat package QFP
  • small outline integrated circuit SOIC
  • quad flat package no leads QFN
  • plastic ball grid array PBGA
  • tape ball grid array TBGA
  • chip scale package CSP
  • wires having insulator coatings may also be used to connect other types of conductive structures in a packaged IC.
  • FIG. 4 shows one embodiment of a chemical vapor deposition (CVD) system 410 for coating a conductive core (e.g. 306 ) with an insulator coating (e.g. 304 ) according to the present invention.
  • CVD system 410 is configured to perform plasma enhanced chemical vapor deposition (PECVD) on a conductive core 418 , which is initially stored, uncoated, on reel 414 .
  • PECVD plasma enhanced chemical vapor deposition
  • CVD system 410 includes a deposition chamber 412 with wire reels 414 and 416 located therein. Also located in chamber 412 are a gas manifold 420 and a bottom plate 422 . Reactive species gas is introduced into chamber 412 through gas inlets 426 and 428 and gas manifold 420 . Exhaust gas is removed from chamber 412 via exhaust tube 430 .
  • a radio frequency (RF) plasma discharge is generated between gas manifold 420 and bottom plate 422 which causes a chemical reaction between the reactive species.
  • the bottom plate 422 may be heated to 200-400 C to aid in the chemical reaction.
  • This chemical reaction causes a vapor deposition in the deposition zone (located between manifold 420 and bottom plate 422 ) of the insulator coating material on the portion of conductive core 418 located between reel 414 and 416 .
  • an insulator coating e.g. 304
  • System 410 may include other conventional CVD equipment not shown.
  • ammonia is introduced in inlet 426 and silane (SiH 4 ) diluted in helium is introduced in inlet 428 to cause a chemical reaction for the deposition of silicon nitride on the conductive core 418 .
  • the thickness of the coating deposited on the conductive core 418 is controlled by the amount and/or rate of reactive species gas introduced in chamber 412 , the RF power applied to manifold 420 and plate 422 , the vacuum pumping rate in which gas is removed from tube 430 , and the spool rate that conductive core 418 is transferred from reel 414 to reel 416 .
  • the PECVD occurs at a sufficiently low temperature to avoid melting the conductive core.
  • CVD processes may be utilized to apply an insulator coating on a conductive core.
  • other methods for applying an insulator coating may be used such as, e.g., sputtering and evaporation.
  • CVD processes provide for a faster and more uniform application of the insulator coating material.
  • FIG. 5 is a flow chart setting forth one embodiment of a method of manufacturing a packaged IC according to the present invention.
  • IC die 114 is attached to substrate 112 .
  • the wires having an insulator coating formed by a CVD process in 514 are attached to bond fingers of the substrate and bond pads of the IC die.
  • wire having an insulator coating is initially located on a spool (not shown).
  • the end of the wire (not shown) extending from the spool is attached to a bond pad (e.g. pad 118 ) of a die by thermosonically a formed ball (e.g. 202 ) to the pad and the wire end.
  • the wire is then positioned over a bond finger (e.g. 116 ) where it is wedge bonded to the bond finger and cut from the remaining portion of the wire on the spool.
  • a bond finger e.g. 116
  • the new end of the wire from the spool is attached to another bond pad by thermosonically bonding a formed ball to the pad and the new end of the wire, and in 508 , the wire is wedged bonded to the second bond finger and cut from the remaining portion of the wire on the spool.
  • a packaged integrated circuit includes an IC die having a plurality of sides, a first plurality of conductive structures, a second plurality of conductive structures, and a plurality of wires.
  • Each wire of the plurality electrically connects a conductive structure of the first plurality of conductive structures to a conductive structure of the second plurality of conductive structures.
  • Each wire of the plurality of wires includes an electrically conductive core with an insulator coating around the electrically conductive core.
  • the insulator coating includes an inorganic covalently-bonded substance that is not an oxide of the electrically conductive core.
  • the packaged IC also includes an encapsulant covering the plurality of wires and at least one side of the IC die.
  • the invention includes a method of making a packaged integrated circuit (IC).
  • the method includes providing an IC die, providing a conductive core, and applying an insulator coating around the conductive core by a chemical vapor deposition process to form an insulated wire.
  • the method also includes electrically connecting a first conductive structure with a second conductive structure with the insulated wire and encapsulating at least a portion of each of the IC die, the first conductive structure, the second conductive structure, and the insulated wire.
  • a wire in another aspect of the invention, includes a metal core and an insulator coating around the core.
  • the insulator coating includes at least one of silicon nitride and silicon oxide.
  • a packaged integrated circuit includes a package substrate having a plurality of package bond fingers, an IC die mounted on the package substrate and having a plurality of IC bond pads, and a plurality of wires.
  • Each of the plurality of wires connects a package bond finger of the plurality of package bond fingers to a IC bond pad of the plurality of IC bond pads.
  • Each of the plurality of wires includes a metal core with an insulator coating including at least one of silicon nitride, silicon oxynitride, and silicon oxide.
  • the packaged IC also includes an encapsulant covering the plurality of wires and at least one side of the IC die.

Abstract

A packaged IC including insulated wire for electrically connecting conductive structures of the packaged IC. In some embodiments, the packaged IC includes an IC die attached to a package substrate, where bond pads of the IC die are electrically connected to bond fingers of the substrate with insulated wire. The insulated wire has a conductive core and an insulator coating. In some examples, the insulator coating includes an inorganic covalently-bonded substance that is not an oxide of the electrically conductive core such as, e.g., silicon nitride or silicon oxide. In one example, the insulator coating is applied to a conductive core by a chemical vapor deposition (CVD) process such as a plasma enhanced chemical vapor deposition (PECVD).

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • This invention relates in general to packaged integrated circuits (ICs) in general and specifically to insulated wires for packaged ICs. [0002]
  • 2. Description of the Related Art [0003]
  • Packaged ICs utilize wires for electrically coupling conductive structures encapsulated in an IC package. For example, wires may be used to electrically connect bond pads of an integrated circuit (IC) die with devices of a package substrate. Wires may also be used to cross connect bond pads of a die in the package or to cross connect bond fingers of a substrate. [0004]
  • A problem with using wires in a packaged IC is that a wire may unintentionally short to other conductive structures of the packaged IC such as, e.g., other wires, pads, fingers, or the die. This shorting may occur during IC die encapsulation as, for example, from “sweeping,” where the injection or transfer of the liquid molding encapsulant moves the wires against another conductive structure. [0005]
  • An insulator coating may be applied to wires utilized in an IC package. However such insulator coatings need to be compatible with wire bonding processes and provide the insulative electrical properties as desired. What is needed is an improved wire insulator coating for packaged ICs. [0006]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings. [0007]
  • FIG. 1 is a top view of one embodiment of an IC die attached to a package substrate and including wires for electrically connecting electrically conductive structures of the IC die and substrate according to the present invention. [0008]
  • FIG. 2 is partial cut away side view of one embodiment of a packaged IC according to the present invention. [0009]
  • FIG. 3 is a cross sectional view of one embodiment of a wire with an insulator coating according to the present invention. [0010]
  • FIG. 4 is a view of one embodiment of a chemical vapor deposition system for coating a conductive core with an insulator coating according to the present invention. [0011]
  • FIG. 5 is a flow chart setting forth one embodiment of a method of manufacturing a packaged IC according to the present invention.[0012]
  • The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. [0013]
  • DETAILED DESCRIPTION
  • The following sets forth a detailed description of a mode for carrying out the invention. The description is intended to be illustrative of the invention and should not be taken to be limiting. [0014]
  • FIG. 1 is a top view of one embodiment of an IC die [0015] 114 attached to package substrate 112 prior to an encapsulation of IC die 114. Wires (e.g. 120) are utilized to electrically connect bond pads (e.g. 118) on IC die 114 with bond fingers (e.g. 116) of package substrate 112. Wires are also utilized for electrically connecting bond fingers of substrate 112 to each other. For example, wire 132 electrically connects substrate bond finger 142 with bond finger 144. Also wires can be utilized to electrically connect IC bond pads with each other. For example, wire 134 electrically connects bond pad 150 with bond pad 152.
  • The wires shown in FIG. 1 have an insulator coating surrounding a conductive core for preventing the wires from shorting to other wires or other conductive structures of the packaged IC ([0016] 201 of FIG. 2). For example, the insulative coating on wires 132 and 136 would prevent the conductive cores of those wires from shorting to each other in the event that the wires contact each other.
  • Referring to FIG. 3, [0017] insulator coating 304 surrounds conductive core 306. In some embodiments, the conductive core is made from a metal such as copper, gold, or aluminum.
  • In one embodiment, [0018] insulator coating 304 includes an inorganic covalently-bonded substance having insulative properties such that the thickness of the coating is sufficient to meet the insulative requirements of the IC package. An inorganic covalently-bonded substance is a covalently-bonded substance that does not include a compound with carbon and another element. Examples of an inorganic covalently-bonded substance that have insulative properties such that it can be used in the insulative coating include nitrides such as, e.g. silicon nitride, aluminum nitride, and boron nitride; oxides such as e.g. silicon oxide, titanium oxide, magnesium oxide, tantalum oxide, boron oxide, beryllium oxide, phosphorous oxide, vanadium oxide, chromium oxide, zirconium oxide; carbides such as silicon carbide; silicon oxynitride; and diamond and diamond-like carbon. In some embodiments, the oxides that may be used are not oxides of the material of the conductive core. In some examples, the insulative coating is applied by a chemical vapor deposition (CVD) process such as, e.g., a plasma enhanced CVD (PECVD) process prior to the attachment of the wire to the electrically conductive structure of the die and substrate.
  • In some embodiments, the inorganic covalently-bonded substance of the insulator coating has a high breakdown voltage such that it that can provide the desired insulative properties with a relatively thin coating. In one embodiment, the insulative coating include stoichiometric silicon oxide (SiO2). In one example, a wire having a conductive core of gold would have a insulator coating of SiO2 having a thickness of 15-10,000 angstroms. However, in some embodiments, the thickness of the insulator coating should be minimized to allow the wire to be bent without cracking the insulator coating. [0019]
  • FIG. 2 is a partial cutaway view of a packaged [0020] IC 201 that includes substrate 112 and IC die 114 encapsulated in an encapsulant 224. Wire 120 electrically connects bond pad 118 to substrate bond finger 116. Bond finger 116 is connected to plated via 214, which is connected to ball grid array (BGA) pad 212. Ball 210 is electrically connected to pad 212 and as is utilized for the electrically coupling IC die 114 to external devices.
  • [0021] Wire 120 is attached to pad 118 by thermosonically bonding a formed ball 202 to pad 118 and wire 120. Wire is then routed to bond finger 116 where it is attached to bond finger 116 by wedge bonding wire 120 to bond finger 116 and then cutting the excess wire from bond finger 116. In other embodiments, both ends of the wire are attached by wedge bonding or by other conventional wire attachment techniques.
  • In some embodiments, the insulator coating including an inorganic covalently-bonded substance has a material hardness greater than and is more brittle than the conductive core. Accordingly the insulator coating provides an “egg shell” effect with respect to the conductive core. The brittle nature of the insulator coating may aid in the wedge bonding of the wire to a conductive structure. With these embodiments, the insulator coating material easily cracks at the point of attachment wherein small particles of the insulator become embedded in the softer conductive core material. Also, in some embodiments, the material hardness of the insulator coating aids in ability of the coating to withstand wear from friction such as e.g. from two wires rubbing together during e.g. the bonding or encapsulation process. [0022]
  • In some embodiments, the melting point of the inorganic covalently-bonded substance of the insulator coating is higher than that of the conductive core material. During the ball formation for the attachment of the wire to a pad or finger (e.g. during the attachment of [0023] wire 120 to pad 118), the conductive core material melts wherein insulator coating material covering the melted portion of the core becomes embedded as particulate matter in the ball. However, because insulator coating material has a higher melting point than the conductive core material, the insulator coating remains on the portions of the wire whose conductive core was not melted.
  • Referring back to FIG. 2, wires having an insulator coatings may be utilized in other types of packaged ICs. For example, wires with insulator coatings may be utilized to connect die pads of multiple IC dies located in a multi die IC package (such as, e.g., in a stacked die or side by side die packaged IC). Wires having insulator coatings may also be used in leaded packaged IC to connect the bond pads of the IC die to the lead frame of the leaded packaged IC. Wires having insulator coatings may also be used in other types of packages such as e.g. quad flat package (QFP), small outline integrated circuit (SOIC), quad flat package no leads (QFN), plastic ball grid array (PBGA), tape ball grid array (TBGA), and chip scale package (CSP). In addition, wires having insulator coatings may also be used to connect other types of conductive structures in a packaged IC. [0024]
  • FIG. 4 shows one embodiment of a chemical vapor deposition (CVD) [0025] system 410 for coating a conductive core (e.g. 306) with an insulator coating (e.g. 304) according to the present invention. In the embodiment shown, CVD system 410 is configured to perform plasma enhanced chemical vapor deposition (PECVD) on a conductive core 418, which is initially stored, uncoated, on reel 414. CVD system 410 includes a deposition chamber 412 with wire reels 414 and 416 located therein. Also located in chamber 412 are a gas manifold 420 and a bottom plate 422. Reactive species gas is introduced into chamber 412 through gas inlets 426 and 428 and gas manifold 420. Exhaust gas is removed from chamber 412 via exhaust tube 430.
  • A radio frequency (RF) plasma discharge is generated between [0026] gas manifold 420 and bottom plate 422 which causes a chemical reaction between the reactive species. The bottom plate 422 may be heated to 200-400 C to aid in the chemical reaction. This chemical reaction causes a vapor deposition in the deposition zone (located between manifold 420 and bottom plate 422) of the insulator coating material on the portion of conductive core 418 located between reel 414 and 416. As reels 414 and 416 are rotated in a clockwise direction, relative to the view shown in FIG. 4, an insulator coating (e.g. 304) is applied to the conductive core 418 as it passes through the deposition zone. System 410 may include other conventional CVD equipment not shown. In one embodiment, ammonia (NH4) is introduced in inlet 426 and silane (SiH4) diluted in helium is introduced in inlet 428 to cause a chemical reaction for the deposition of silicon nitride on the conductive core 418.
  • The thickness of the coating deposited on the [0027] conductive core 418 is controlled by the amount and/or rate of reactive species gas introduced in chamber 412, the RF power applied to manifold 420 and plate 422, the vacuum pumping rate in which gas is removed from tube 430, and the spool rate that conductive core 418 is transferred from reel 414 to reel 416. The PECVD occurs at a sufficiently low temperature to avoid melting the conductive core.
  • In other embodiments, other types of CVD processes may be utilized to apply an insulator coating on a conductive core. In addition, other methods for applying an insulator coating may be used such as, e.g., sputtering and evaporation. However, CVD processes provide for a faster and more uniform application of the insulator coating material. [0028]
  • FIG. 5 is a flow chart setting forth one embodiment of a method of manufacturing a packaged IC according to the present invention. In [0029] 504, IC die 114 is attached to substrate 112. After 504, the wires having an insulator coating formed by a CVD process in 514 are attached to bond fingers of the substrate and bond pads of the IC die. During the manufacturing process, wire having an insulator coating is initially located on a spool (not shown). In 506, the end of the wire (not shown) extending from the spool is attached to a bond pad (e.g. pad 118) of a die by thermosonically a formed ball (e.g. 202) to the pad and the wire end. In 508, the wire is then positioned over a bond finger (e.g. 116) where it is wedge bonded to the bond finger and cut from the remaining portion of the wire on the spool. If there are other wires to be implemented in the packaged IC, in 506, the new end of the wire from the spool (formed by the cutting in 508) is attached to another bond pad by thermosonically bonding a formed ball to the pad and the new end of the wire, and in 508, the wire is wedged bonded to the second bond finger and cut from the remaining portion of the wire on the spool. When all of the wires of the package have been installed, in 512, other processes are performed to complete the manufacturing of the packaged IC, including the encapsulation of the devices of the package (e.g. die 114, the wires and portions of the substrate such as e.g. shown in the embodiment of FIG. 2). In other embodiments, other manufacturing processes may be utilized.
  • In one aspect of the invention, a packaged integrated circuit (IC) includes an IC die having a plurality of sides, a first plurality of conductive structures, a second plurality of conductive structures, and a plurality of wires. Each wire of the plurality electrically connects a conductive structure of the first plurality of conductive structures to a conductive structure of the second plurality of conductive structures. Each wire of the plurality of wires includes an electrically conductive core with an insulator coating around the electrically conductive core. The insulator coating includes an inorganic covalently-bonded substance that is not an oxide of the electrically conductive core. The packaged IC also includes an encapsulant covering the plurality of wires and at least one side of the IC die. [0030]
  • In another aspect, the invention includes a method of making a packaged integrated circuit (IC). The method includes providing an IC die, providing a conductive core, and applying an insulator coating around the conductive core by a chemical vapor deposition process to form an insulated wire. The method also includes electrically connecting a first conductive structure with a second conductive structure with the insulated wire and encapsulating at least a portion of each of the IC die, the first conductive structure, the second conductive structure, and the insulated wire. [0031]
  • In another aspect of the invention, a wire includes a metal core and an insulator coating around the core. The insulator coating includes at least one of silicon nitride and silicon oxide. [0032]
  • In another aspect of the invention, a packaged integrated circuit (IC) includes a package substrate having a plurality of package bond fingers, an IC die mounted on the package substrate and having a plurality of IC bond pads, and a plurality of wires. Each of the plurality of wires connects a package bond finger of the plurality of package bond fingers to a IC bond pad of the plurality of IC bond pads. Each of the plurality of wires includes a metal core with an insulator coating including at least one of silicon nitride, silicon oxynitride, and silicon oxide. The packaged IC also includes an encapsulant covering the plurality of wires and at least one side of the IC die. [0033]
  • While particular embodiments of the present invention have been shown and described, it will be recognized to those skilled in the art that, based upon the teachings herein, further changes and modifications may be made without departing from this invention and its broader aspects, and thus, the appended claims are to encompass within their scope all such changes and modifications as are within the true spirit and scope of this invention. [0034]

Claims (30)

What is claimed is:
1. A packaged integrated circuit (IC), comprising:
an IC die having a plurality of sides;
a first plurality of conductive structures;
a second plurality of conductive structures;
a plurality of wires, each wire of the plurality electrically connecting a conductive structure of the first plurality of conductive structures to a conductive structure of the second plurality of conductive structures, wherein each wire of the plurality of wires includes an electrically conductive core with an insulator coating around the electrically conductive core, wherein the insulator coating includes an inorganic covalently-bonded substance that is not an oxide of the electrically conductive core; and
an encapsulant covering the plurality of wires and at least one side of the IC die.
2. The packaged IC of claim 1, wherein the insulator coating includes silicon oxynitride.
3. The packaged IC of claim 1, wherein the insulator coating includes an oxide of silicon.
4. The packaged IC of claim 1, wherein the insulator coating includes silicon nitride.
5. The packaged IC of claim 1, wherein the electrically conductive core includes metal.
6. The packaged IC of claim 5, wherein the electrically conductive core includes gold.
7. The packaged IC of claim 5, wherein the electrically conductive core includes copper.
8. The packaged IC of claim 5, wherein the electrically conductive core includes aluminum.
9. The packaged IC of claim 1, wherein the first plurality of conductive structures includes a plurality of IC bond pads on the IC die.
10. The packaged IC of claim 1, wherein the plurality of wires further includes a wire connecting a first IC bond pad of a plurality of IC bond pads to a second IC bond pad of the plurality of IC bond pads.
11. The packaged IC of claim 1, further comprising a package substrate, wherein a plurality of bond fingers is located on the package substrate and wherein the IC die is mounted on the package substrate.
12. The packaged IC of claim 11, wherein the plurality of wires further includes a wire connecting a first package bond finger of the plurality of package bond fingers to a second package bond finger of the plurality of package bond fingers.
13. The packaged IC of claim 1, wherein the insulator coating has a higher melting temperature than that of the electrically conductive core.
14. The packaged IC of claim 1, wherein the insulator coating has a material hardness greater than that of the electrically conductive core.
15. The packaged IC of claim 1, wherein the inorganic covalently-bonded substance is one of silicon nitride, alumium nitride, boron nitride, silicon oxide, silicon oxynitride, titanium oxide, magnesium oxide, tantalum oxide, boron oxide, berylium oxide, phosphorus oxide, vanadium oxide, chromium oxide, zirconium oxide, silicon carbide, diamond, and diamond-like carbon.
16. A method of making a packaged integrated circuit (IC), comprising:
providing an IC die;
providing a conductive core;
applying an insulator coating around the conductive core by a chemical vapor deposition process to form an insulated wire;
electrically connecting a first conductive structure with a second conductive structure with the insulated wire; and
encapsulating at least a portion of each of the IC die, the first conductive structure, the second conductive structure, and the insulated wire.
17. The method of claim 16 wherein the insulator coating includes an inorganic covalently-bonded substance that is not an oxide of the conductive core.
18. The method of claim 17, wherein the inorganic covalently-bonded substance is one of silicon nitride, aluminum nitride, boron nitride, silicon oxide, silicon oxynitride, titanium oxide, magnesium oxide, tantalum oxide, boron oxide, beryllium oxide, phosphorus oxide, vanadium oxide, chromium oxide, zirconium oxide, silicon carbide, diamond, and diamond-like carbon.
19. The method of claim 16 wherein the first conductive structure is a bond pad of the IC die.
20. The method of claim 16, wherein the CVD process includes a plasma enhanced chemical vapor deposition (PECVD) process.
21. The method of claim 16, wherein the insulator coating includes at least one of silicon oxide or silicon nitride.
22. The method of claim 16, wherein the conductive core includes copper.
23. The method of claim 16, wherein the conductive core includes gold.
24. The method of claim 16, wherein the conductive core includes aluminum.
25. The method of claim 16, wherein the insulator coating has a higher melting temperature than that of the conductive core.
26. The method of claim 16, wherein the insulator coating has a thickness of at least 15 Angstroms.
27. The method of claim 16, where in the insulator coating has a material hardness greater than that of the conductive core.
28. A wire comprising:
a metal core; and
an insulator coating around the core, the insulator coating including at least one of silicon nitride and silicon oxide.
29. A packaged integrated circuit (IC), comprising:
a package substrate having a plurality of package bond fingers;
an IC die mounted on the package substrate and having a plurality of IC bond pads;
a plurality of wires, each of the plurality of wires connecting a package bond finger of the plurality of package bond fingers to a IC bond pad of the plurality of IC bond pads, wherein each of the plurality of wires includes a metal core with an insulator coating including at least one of silicon nitride, silicon oxynitride, and silicon oxide; and
an encapsulant covering the plurality of wires and at least one side of the IC die.
30. The packaged IC of claim 29, wherein the insulator coating has a thickness of at least 15 nanometers.
US10/323,293 2002-12-18 2002-12-18 Packaged IC using insulated wire Abandoned US20040119172A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US10/323,293 US20040119172A1 (en) 2002-12-18 2002-12-18 Packaged IC using insulated wire
AU2003270913A AU2003270913A1 (en) 2002-12-18 2003-09-23 Packaged ic using insulated wire
PCT/US2003/030593 WO2004061959A1 (en) 2002-12-18 2003-09-23 Packaged ic using insulated wire
TW092128310A TWI317541B (en) 2002-12-18 2003-10-13 Method of making a packaged integrated circuit
US10/847,775 US7138328B2 (en) 2002-12-18 2004-05-18 Packaged IC using insulated wire

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/323,293 US20040119172A1 (en) 2002-12-18 2002-12-18 Packaged IC using insulated wire

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/847,775 Division US7138328B2 (en) 2002-12-18 2004-05-18 Packaged IC using insulated wire

Publications (1)

Publication Number Publication Date
US20040119172A1 true US20040119172A1 (en) 2004-06-24

Family

ID=32593175

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/323,293 Abandoned US20040119172A1 (en) 2002-12-18 2002-12-18 Packaged IC using insulated wire
US10/847,775 Active 2024-07-04 US7138328B2 (en) 2002-12-18 2004-05-18 Packaged IC using insulated wire

Family Applications After (1)

Application Number Title Priority Date Filing Date
US10/847,775 Active 2024-07-04 US7138328B2 (en) 2002-12-18 2004-05-18 Packaged IC using insulated wire

Country Status (4)

Country Link
US (2) US20040119172A1 (en)
AU (1) AU2003270913A1 (en)
TW (1) TWI317541B (en)
WO (1) WO2004061959A1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060097374A1 (en) * 2004-11-10 2006-05-11 Yoshimi Egawa Multi chip package
US20060175712A1 (en) * 2005-02-10 2006-08-10 Microbonds, Inc. High performance IC package and method
WO2007107964A1 (en) * 2006-03-23 2007-09-27 Nxp B.V. Electrically enhanced wirebond package
WO2011087485A3 (en) * 2009-12-22 2012-01-26 Tessera, Inc Microelectronic assembly with joined bond elements having lowered inductance
WO2016209286A1 (en) * 2015-06-26 2016-12-29 Intel Corporation Package assembly with gathered insulated wires

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080131998A1 (en) * 2006-12-01 2008-06-05 Hem Takiar Method of fabricating a film-on-wire bond semiconductor device
WO2011139619A1 (en) 2010-04-26 2011-11-10 Hsio Technologies, Llc Semiconductor device package adapter
WO2014011232A1 (en) 2012-07-12 2014-01-16 Hsio Technologies, Llc Semiconductor socket with direct selective metalization
WO2010138493A1 (en) 2009-05-28 2010-12-02 Hsio Technologies, Llc High performance surface mount electrical interconnect
US9276336B2 (en) 2009-05-28 2016-03-01 Hsio Technologies, Llc Metalized pad to electrical contact interface
WO2010141297A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed circuit wafer level semiconductor package
US8955216B2 (en) 2009-06-02 2015-02-17 Hsio Technologies, Llc Method of making a compliant printed circuit peripheral lead semiconductor package
US9184527B2 (en) 2009-06-02 2015-11-10 Hsio Technologies, Llc Electrical connector insulator housing
US9277654B2 (en) 2009-06-02 2016-03-01 Hsio Technologies, Llc Composite polymer-metal electrical contacts
US9603249B2 (en) 2009-06-02 2017-03-21 Hsio Technologies, Llc Direct metalization of electrical circuit structures
US8988093B2 (en) 2009-06-02 2015-03-24 Hsio Technologies, Llc Bumped semiconductor wafer or die level electrical interconnect
US8912812B2 (en) 2009-06-02 2014-12-16 Hsio Technologies, Llc Compliant printed circuit wafer probe diagnostic tool
US9276339B2 (en) 2009-06-02 2016-03-01 Hsio Technologies, Llc Electrical interconnect IC device socket
WO2010141296A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed circuit semiconductor package
WO2014011226A1 (en) 2012-07-10 2014-01-16 Hsio Technologies, Llc Hybrid printed circuit assembly with low density main core and embedded high density circuit regions
US8970031B2 (en) 2009-06-16 2015-03-03 Hsio Technologies, Llc Semiconductor die terminal
US9231328B2 (en) 2009-06-02 2016-01-05 Hsio Technologies, Llc Resilient conductive electrical interconnect
US9930775B2 (en) 2009-06-02 2018-03-27 Hsio Technologies, Llc Copper pillar full metal via electrical circuit structure
WO2010141295A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed flexible circuit
WO2011002709A1 (en) 2009-06-29 2011-01-06 Hsio Technologies, Llc Compliant printed circuit semiconductor tester interface
US9613841B2 (en) 2009-06-02 2017-04-04 Hsio Technologies, Llc Area array semiconductor device package interconnect structure with optional package-to-package or flexible circuit to package connection
US9196980B2 (en) 2009-06-02 2015-11-24 Hsio Technologies, Llc High performance surface mount electrical interconnect with external biased normal force loading
WO2012074963A1 (en) 2010-12-01 2012-06-07 Hsio Technologies, Llc High performance surface mount electrical interconnect
US9320133B2 (en) 2009-06-02 2016-04-19 Hsio Technologies, Llc Electrical interconnect IC device socket
WO2010141313A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed circuit socket diagnostic tool
US9232654B2 (en) 2009-06-02 2016-01-05 Hsio Technologies, Llc High performance electrical circuit structure
US9318862B2 (en) 2009-06-02 2016-04-19 Hsio Technologies, Llc Method of making an electronic interconnect
US9054097B2 (en) 2009-06-02 2015-06-09 Hsio Technologies, Llc Compliant printed circuit area array semiconductor device package
WO2010147782A1 (en) * 2009-06-16 2010-12-23 Hsio Technologies, Llc Simulated wirebond semiconductor package
US9320144B2 (en) 2009-06-17 2016-04-19 Hsio Technologies, Llc Method of forming a semiconductor socket
US8984748B2 (en) 2009-06-29 2015-03-24 Hsio Technologies, Llc Singulated semiconductor device separable electrical interconnect
US9350093B2 (en) 2010-06-03 2016-05-24 Hsio Technologies, Llc Selective metalization of electrical connector or socket housing
US9689897B2 (en) 2010-06-03 2017-06-27 Hsio Technologies, Llc Performance enhanced semiconductor socket
US10159154B2 (en) 2010-06-03 2018-12-18 Hsio Technologies, Llc Fusion bonded liquid crystal polymer circuit structure
US8283780B2 (en) 2010-11-25 2012-10-09 Freescale Semiconductor, Inc Surface mount semiconductor device
US9761520B2 (en) 2012-07-10 2017-09-12 Hsio Technologies, Llc Method of making an electrical connector having electrodeposited terminals
US10506722B2 (en) 2013-07-11 2019-12-10 Hsio Technologies, Llc Fusion bonded liquid crystal polymer electrical circuit structure
US10667410B2 (en) 2013-07-11 2020-05-26 Hsio Technologies, Llc Method of making a fusion bonded circuit structure
US9368470B2 (en) 2014-10-31 2016-06-14 Freescale Semiconductor, Inc. Coated bonding wire and methods for bonding using same
US9755335B2 (en) 2015-03-18 2017-09-05 Hsio Technologies, Llc Low profile electrical interconnect with fusion bonded contact retention and solder wick reduction

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4722852A (en) * 1984-06-13 1988-02-02 U.S. Philips Corporation Device for electron emission including device for providing work function reducing layer and method of applying such a layer
US5350638A (en) * 1991-04-26 1994-09-27 Sumitomo Electric Industries, Ltd. Electrical insulated wire
US5372886A (en) * 1989-03-28 1994-12-13 Sumitomo Electric Industries, Ltd. Insulated wire with an intermediate adhesion layer and an insulating layer
US5396104A (en) * 1989-03-28 1995-03-07 Nippon Steel Corporation Resin coated bonding wire, method of manufacturing the same, and semiconductor device
US5402006A (en) * 1992-11-10 1995-03-28 Texas Instruments Incorporated Semiconductor device with enhanced adhesion between heat spreader and leads and plastic mold compound
US5443905A (en) * 1991-01-24 1995-08-22 Sumitomo Electric Industries, Ltd. Heat and oxidation resistant composite electrical conductor
US5468557A (en) * 1989-01-12 1995-11-21 Sumitomo Electric Industries, Ltd. Ceramic insulated electrical conductor wire and method for manufacturing such a wire
US20010017221A1 (en) * 2000-02-28 2001-08-30 Michio Horiuchi Wiring boards, semiconductor devices and their production processes

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3011047C2 (en) * 1979-03-23 1982-12-16 Nippondenso Co., Ltd., Kariya, Aichi Heat-resistant, insulated electrical conductor wire and method for making the same
JPS55136514A (en) 1979-04-09 1980-10-24 Kawai Denki Seisakusho:Kk Heating die
JPS5863142A (en) * 1981-10-12 1983-04-14 Toshiba Corp Bonding wire and bonding process
JPS61287155A (en) * 1985-06-14 1986-12-17 Hitachi Ltd Semiconductor device
US6043563A (en) * 1997-05-06 2000-03-28 Formfactor, Inc. Electronic components with terminals and spring contact elements extending from areas which are remote from the terminals
US4860941A (en) * 1986-03-26 1989-08-29 Alcan International Limited Ball bonding of aluminum bonding wire
US5285949A (en) * 1987-01-26 1994-02-15 Hitachi, Ltd. Wire-bonding method, wire-bonding apparatus, and semiconductor device produced by the wire-bonding method
JPS63187639A (en) * 1987-01-30 1988-08-03 Hitachi Ltd Semiconductor device
JPS63276940A (en) * 1987-03-26 1988-11-15 Ricoh Co Ltd Node equipment for indefinite communication network
DE68923732T2 (en) * 1988-05-19 1996-01-18 Semiconductor Energy Lab Method of manufacturing an electrical device.
US5208467A (en) * 1988-07-28 1993-05-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a film-covered packaged component
JPH01292849A (en) * 1988-08-05 1989-11-27 Semiconductor Energy Lab Co Ltd Manufacture of electronic device
JPH0244738A (en) * 1988-08-05 1990-02-14 Semiconductor Energy Lab Co Ltd Manufacture of electronic device
US6756670B1 (en) * 1988-08-26 2004-06-29 Semiconductor Energy Laboratory Co., Ltd. Electronic device and its manufacturing method
US5021401A (en) * 1989-04-03 1991-06-04 Westinghouse Electric Corp. Integrated production of superconductor insulation for chemical vapor deposition of nickel carbonyl
JPH02270217A (en) 1989-04-11 1990-11-05 Sumitomo Electric Ind Ltd Insulated wire
JPH0364811A (en) 1989-07-31 1991-03-20 Okazaki Seisakusho:Kk Hollow core wire mi cable and manufacture thereof
WO1991012227A1 (en) * 1990-02-19 1991-08-22 Sumitomo Chemical Company, Limited Aromatic oligomer and production thereof
JP2766369B2 (en) * 1990-03-20 1998-06-18 新日本製鐵株式会社 Bonding wire for semiconductor
JPH04158557A (en) * 1990-10-22 1992-06-01 Matsushita Electron Corp Reasin-sealed type semiconductor device and manufacture thereof
JPH04315445A (en) 1991-04-15 1992-11-06 Hitachi Ltd Bonding wire and manufacture of semiconductor integrated circuit device using same
US5656830A (en) * 1992-12-10 1997-08-12 International Business Machines Corp. Integrated circuit chip composite having a parylene coating
JPH06268100A (en) * 1993-03-12 1994-09-22 Nippon Telegr & Teleph Corp <Ntt> Sealing structure of semiconductor device and sealing method therefor
US5455745A (en) * 1993-07-26 1995-10-03 National Semiconductor Corporation Coated bonding wires in high lead count packages
US5376602A (en) * 1993-12-23 1994-12-27 The Dow Chemical Company Low temperature, pressureless sintering of silicon nitride
JPH08330346A (en) * 1995-05-31 1996-12-13 Nec Kyushu Ltd Manufacture of semiconductor device
US5951813A (en) * 1996-05-02 1999-09-14 Raytheon Company Top of die chip-on-board encapsulation
EP0960438A1 (en) 1996-12-09 1999-12-01 Microbonds, Inc. High density integrated circuits and the method of packaging the same
US6046075A (en) * 1997-12-23 2000-04-04 Vlsi Technology, Inc. Oxide wire bond insulation in semiconductor assemblies
US6177726B1 (en) * 1999-02-11 2001-01-23 Philips Electronics North America Corporation SiO2 wire bond insulation in semiconductor assemblies
EP1215724B1 (en) * 2000-11-20 2012-10-31 Texas Instruments Incorporated Wire bonded semiconductor device with low capacitance coupling
US6783589B2 (en) * 2001-01-19 2004-08-31 Chevron U.S.A. Inc. Diamondoid-containing materials in microelectronics

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4722852A (en) * 1984-06-13 1988-02-02 U.S. Philips Corporation Device for electron emission including device for providing work function reducing layer and method of applying such a layer
US5468557A (en) * 1989-01-12 1995-11-21 Sumitomo Electric Industries, Ltd. Ceramic insulated electrical conductor wire and method for manufacturing such a wire
US5372886A (en) * 1989-03-28 1994-12-13 Sumitomo Electric Industries, Ltd. Insulated wire with an intermediate adhesion layer and an insulating layer
US5396104A (en) * 1989-03-28 1995-03-07 Nippon Steel Corporation Resin coated bonding wire, method of manufacturing the same, and semiconductor device
US5443905A (en) * 1991-01-24 1995-08-22 Sumitomo Electric Industries, Ltd. Heat and oxidation resistant composite electrical conductor
US5350638A (en) * 1991-04-26 1994-09-27 Sumitomo Electric Industries, Ltd. Electrical insulated wire
US5402006A (en) * 1992-11-10 1995-03-28 Texas Instruments Incorporated Semiconductor device with enhanced adhesion between heat spreader and leads and plastic mold compound
US20010017221A1 (en) * 2000-02-28 2001-08-30 Michio Horiuchi Wiring boards, semiconductor devices and their production processes

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060097374A1 (en) * 2004-11-10 2006-05-11 Yoshimi Egawa Multi chip package
US7215031B2 (en) * 2004-11-10 2007-05-08 Oki Electric Industry Co., Ltd. Multi chip package
US20060175712A1 (en) * 2005-02-10 2006-08-10 Microbonds, Inc. High performance IC package and method
WO2007107964A1 (en) * 2006-03-23 2007-09-27 Nxp B.V. Electrically enhanced wirebond package
US20090102067A1 (en) * 2006-03-23 2009-04-23 Nxp B.V. Electrically enhanced wirebond package
US8203219B2 (en) 2006-03-23 2012-06-19 Taiwan Semiconductor Manufacturing Company, Ltd. Electrically enhanced wirebond package
WO2011087485A3 (en) * 2009-12-22 2012-01-26 Tessera, Inc Microelectronic assembly with joined bond elements having lowered inductance
US8410618B2 (en) 2009-12-22 2013-04-02 Tessera, Inc. Microelectronic assembly with joined bond elements having lowered inductance
US8816514B2 (en) 2009-12-22 2014-08-26 Tessera, Inc. Microelectronic assembly with joined bond elements having lowered inductance
WO2016209286A1 (en) * 2015-06-26 2016-12-29 Intel Corporation Package assembly with gathered insulated wires
US9935036B2 (en) 2015-06-26 2018-04-03 Intel Corporation Package assembly with gathered insulated wires

Also Published As

Publication number Publication date
WO2004061959A1 (en) 2004-07-22
US20040217458A1 (en) 2004-11-04
TWI317541B (en) 2009-11-21
US7138328B2 (en) 2006-11-21
TW200414482A (en) 2004-08-01
AU2003270913A1 (en) 2004-07-29

Similar Documents

Publication Publication Date Title
US7138328B2 (en) Packaged IC using insulated wire
US7759805B2 (en) Semiconductor device encapsulated by an electrically conductive plastic housing composition with conductive particles
US7709938B2 (en) Arrangement for electrically connecting semiconductor circuit arrangements to an external contact device and method for producing the same
US6368899B1 (en) Electronic device packaging
US20080014678A1 (en) System and method of attenuating electromagnetic interference with a grounded top film
CN101246883B (en) Integrated circuit packaging
US8866274B2 (en) Semiconductor packages and methods of formation thereof
EP0588501A1 (en) Technique for enhancing adhesion capability of heat spreaders in molded packages
US8242614B2 (en) Thermally improved semiconductor QFN/SON package
US20040061206A1 (en) Discrete package having insulated ceramic heat sink
KR20030074155A (en) Semiconductor package having oxidation-free Copper wire and method for manufacturing the same
US9812420B2 (en) Die packaging with fully or partially fused dielectric leads
US7102241B2 (en) Leadless semiconductor package
US7683465B2 (en) Integrated circuit including clip
US8187964B2 (en) Integrated circuit device and method
JP2579142B2 (en) Resin-sealed semiconductor device
EP0930378A1 (en) Method of processing of CVD diamond coatings
CN116165578A (en) Conformal deposition for high voltage isolation
US7199477B1 (en) Multi-tiered lead package for an integrated circuit
US6525423B2 (en) Semiconductor device package and method of die attach
CN116072645A (en) Semiconductor package assembly and method of manufacturing the same
JPS6129139A (en) Semiconductor device
JPS62205650A (en) Substrate for semiconductor device
US20020061640A1 (en) Method of manufacturing passivation layer
CN115050722A (en) Semiconductor device, semiconductor device and method for manufacturing the same

Legal Events

Date Code Title Description
AS Assignment

Owner name: MOTOROLA, INC., ILLINOIS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DOWNEY, SUSAN H.;HARPER, PETER R.;REEL/FRAME:013612/0842

Effective date: 20021217

AS Assignment

Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOTOROLA, INC;REEL/FRAME:015360/0718

Effective date: 20040404

Owner name: FREESCALE SEMICONDUCTOR, INC.,TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOTOROLA, INC;REEL/FRAME:015360/0718

Effective date: 20040404

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION