JP2005536057A - エピレス基板における分離型の相補型mos装置 - Google Patents
エピレス基板における分離型の相補型mos装置 Download PDFInfo
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Abstract
Description
この発明は半導体装置技術に関し、より特定的には、相補型MOS(metal-oxide-silicon)装置であって、互いにおよびそれが形成される基板から電気的に分離された相補型MOS装置に関する。
相補型MOS(CMOS)装置の開発において、半導体ウェハの所与の面積にもっと多くの装置を収めるべく絶えざる努力がなされている。図1〜5はその開発におけるいくつかの段階を説明するための図である。
向にわたる電圧降下を防ぐことで装置のラッチアップ特性を改善するためである。大量ドープのP+基板40は、図2Aに示すP−基板11よりも低い抵抗率を有する。これは少量ドープの共通のボディ領域を共有する非分離型装置で生じ得る問題の表われである。大量ドープの基板は、通常のデジタルICにおいてはラッチアップの低減が可能だが、パワーICおよび大電流ICにおけるラッチアップに対しては十分な保護を提供するものではない。
シリサイド層59が堆積される。Pウェル56とのコンタクトはP+領域61cによって与えられる。
チモン(または砒素)からなるN型埋込層102(NBL1)とである。PMOSFET100aおよびNMOSFET100bは、図3A,3Bに示すPMOSFET50aおよびNMOSFET50bと類似のものである。
この発明に従うと、高エネルギでの打込みを用いて、トランジスタおよびその他の装置を半導体基板からおよび互いに電気的に分離するための種々の構造を作製する。これに代えて、異なるエネルギでの一連の打込みを用いてもよい。現在行なわれている手法とは極めて対照的に、分離構造および装置はノンエピタキシャル半導体基板内に形成される。基板は極めて限られた熱収支に晒されるため、垂直方向および水平方向の両方で打込みの広がりが抑制される。
構造それ自体の中、またはその両方において形成され得る。
図6A〜6Wは、この発明の方法を用いて形成され得るいくつかの基本的な構造を例示する。ここでの一般的な目的は、打込まれた「表面下」の深い層の上に亘って位置した或る数の打込みウェルを形成することである。これらは実際、使用できる装置を製造する際に種々の態様で組合せることのできる「構成単位」である。ここに記載の打込まれた深い層は、従来の「埋込層」とは対照的なものであり、後者はエピタキシャル層の成長前および成長中にエピタキシャル層の最下部に形成される。このようなエピタキシャル前に形成された埋込層では必然的にエピタキシャル層の成長中にドーパントが再び行き渡る現象が見られる。
いずれかによって占められ、N型埋込層がPウェルおよびNウェルの下地をなしかつこれらに接する。Nウェル135がPウェル134のうちの中心部分まわりのリングまたは環状の構造を形成する場合、この中心部分は、図6Hに示す分離された構造と同じ態様で完全に分離されることになる。図6Lは図6Hと類似するが、1つのPウェル134がNウェル135よりも浅い深さまで打込まれて、Nウェル135により形成された環状のリングによって取囲まれている構造を示している。図6Mは図6Lと類似するが、Pウェル134は深いN分離層131の下に延びる。図6Lおよび図6Mの両方において、Pウェル134はP基板130から完全に分離される。
ープのドレイン)の横型二重拡散チャネルMOSFET(LDMOS)169eとを含む。
フィ技術を用いてパターニングされて開口部が形成される。図8Bに示すように、酸化物層170は上記開口部を通じてエッチングされる。制御されたエッチングを行なって酸化物層170の一部を適当に残す場合も、または酸化物層170のうち開口部の下の部分を完全に除去してから新たに薄い酸化物層を成長させる場合もある。いずれの場合においても、P基板173上において開口部内に薄い酸化物層170aが残る。そして、薄い酸化物層170aを通じてリンといったN型ドーパントが打込まれて深いN層174が形成される。次に、酸化物層170,170aおよびフォトレジスト層171が剥ぎ取られて図7Cに示す構造が残る。ここでは、コンパクトでよく規定された深いN層174がP基板173の中に浮遊している。
たP型ドーパントが上記開口部を通じて打込まれ、ドーパント密度がP基板173のドーパント密度よりも大きい分離されたPウェル178が形成される。結果として得られる構造を図8Eに示す。Pウェル178の形成に用いられるイオン打込みを分離領域177すべてが受ける必要はない。
cm-2のリン打込みを含み得る。600keVなど中間のエネルギで、たとえばさらなる7E12cm-2などの追加の打込みを含めてもよい。この追加の打込みのエネルギが低ければ低いほど、表面濃度が影響を受ける可能性は高い。
ドープ(NFD)領域183が形成される。Nウェル175内に入るドーパントはNFD領域183を形成する一方、Pウェル178内に入るNFDドーパントは、PFD領域182に対して完全に対抗ドープするのに十分な濃度とならない。従来のCMOS装置の場合とは異なり、深いN層ならびにNウェルおよびPウェル、特に大量にドープした部分においてドーパントが再び行き渡ることを防ぐため、熱酸化の時間および温度は最小限に抑えられなければならない。厚みが約4000Åのフィールド酸化物の場合、約5E13cm-2のNFD打込みが採用される一方でこのドーズ量の2倍のPFD打込みが必要とされる。このような打込みは低エネルギで行なわれ、典型的には約50keVで行なわれる。
じて実行されている(イオン打込みからマスクされた領域を除く)。その結果として得られるウェルおよび深い層のドーパントプロファイルおよび接合はウェハの元の平坦な表面に対して実質的に平行に走る。
びPウェル259が形成されている。
との間の、P基板351のうちの領域352の中での垂直方向の寸法XDPを示す。Pウェル353は領域352よりも多くドープされると仮定する。深いN層354、領域352およびP+領域356により形成されるダイオード352aは実質的にPINダイオードであり、一方で深いN層354およびPウェル353により形成されるダイオード353aはPNダイオードである。
419を形成する。重なり合いの領域を415〜418で示す。
場合、この深い打込みの結果として本来的に生じる水平方向の散在の量は、装置についての所望の最小フィーチャーサイズ実現のために許容可能な量を上回るおそれがある。
れる時点から測定される。熱処理中のこのようなドーパントの動きは、A. S. グローブ、「半導体装置についての物理および技術」、1967年、第50頁、に記載のフィックの拡散法則によって支配され、これは時間、拡散率および打込みドーズ量Qの関数として濃度のガウスドーパントプロファイルN(x)を記述する式として挙げられている。これは以下の式で与えられる。
Claims (45)
- 半導体装置の製造プロセスであって、
エピタキシャル層を含まない、第1導電型の半導体基板を設ける工程と、
横方向の次元で深い層の場所を規定する第1の開口部を有する第1のマスクを、前記基板の表面上に形成する工程と、
前記深い層を形成するように前記第1の開口部を通じて第2導電型のドーパントを打込む工程と、
前記横方向の次元で側壁部の場所を規定する第2の開口部を有する第2のマスクを、前記基板の前記表面上に形成する工程と、
前記側壁部を形成するように前記第2の開口部を通じて前記第2導電型のドーパントを打込む工程とを備え、前記側壁部は前記深い層から前記基板の前記表面まで延び、前記深い層および前記側壁部は一緒になって分離領域を形成する、プロセス。 - 前記第2の開口部を通じて前記第2導電型のドーパントを打込む工程は、前記第2導電型の前記ドーパントのうちの第1の部分を第1のエネルギで打込む工程と、前記第2導電型の前記ドーパントのうちの第2の部分を第2のエネルギで打込む工程とを含む、請求項1に記載のプロセス。
- 前記基板は、ボロンについて0.3μm2未満のDt熱収支に晒される、請求項1に記載のプロセス。
- 前記基板は、ボロンについて0.03μm2未満のDt熱収支に晒される、請求項3に記載のプロセス。
- 前記基板は、リンについて0.5μm2未満のDt熱収支に晒される、請求項1に記載のプロセス。
- 前記基板は、リンについて0.05μm2未満のDt熱収支に晒される、請求項5に記載のプロセス。
- 前記基板は、850℃で4時間未満と等価の熱収支に晒される、請求項1に記載のプロセス。
- 前記基板は、1100℃で3時間未満と等価の熱収支に晒される、請求項1に記載のプロセス。
- 前記深い層および前記側壁部は一緒になって前記基板における取囲まれた領域を取囲み、前記プロセスは前記取囲まれた領域内に第1の半導体装置を形成する工程を備える、請求項1に記載のプロセス。
- 前記第1の半導体装置はMOSFETを含む、請求項9に記載のプロセス。
- 前記分離構造内に第2の半導体装置を形成する工程を備える、請求項9に記載のプロセス。
- 前記第2の半導体装置はMOSFETを含む、請求項11に記載のプロセス。
- 前記深い層および前記側壁部は一緒になって前記基板における取囲まれた領域を取囲み、前記プロセスはバイポーラトランジスタを形成する工程を備え、前記バイポーラトラン
ジスタは、前記側壁部内にある少なくとも1つの端子と、前記取囲まれた領域内にある少なくとも1つの他の端子とを有する、請求項1に記載のプロセス。 - 前記取囲まれた領域はベースおよびエミッタを含み、前記側壁部はコレクタを含む、請求項13に記載のプロセス。
- 前記深い層および前記側壁部は一緒になって前記基板における取囲まれた領域を取囲み、前記プロセスは電界効果トランジスタを形成する工程を備え、前記電界効果トランジスタは、前記側壁部内にある少なくとも1つの端子と、前記取囲まれた領域内にある少なくとも1つの他の端子とを有する、請求項1に記載のプロセス。
- 前記取囲まれた領域はソースおよびボディを含み、前記側壁部はドレインを含む、請求項15に記載のプロセス。
- 前記深い層および前記側壁部は一緒になって前記基板における取囲まれた領域を取囲み、前記第1導電型はP型であり、前記第2導電型はP型であり、前記プロセスは、前記側壁部内にPチャネルトランジスタを形成する工程と、前記取囲まれた領域内にNチャネルトランジスタを形成する工程とを備える、請求項1に記載のプロセス。
- 前記取囲まれた領域内にPウェルを形成するようにP型ドーパントを打込む工程を備える、請求項17に記載のプロセス。
- 前記深い層および前記側壁部は一緒になって前記基板における取囲まれた領域を取囲み、前記プロセスは、前記取囲まれた領域内に前記第1導電型のウェルを形成するように前記第1導電型のドーパントを打込む工程を備える、請求項1に記載のプロセス。
- 前記第1導電型のドーパントを打込む工程は、前記第1導電型の前記ウェルが前記深い層から隔てられるようなエネルギでドーパントを打込む工程を含む、請求項19に記載のプロセス。
- 前記第1導電型のドーパントを打込む工程は、前記第1導電型の前記ウェルが前記深い層に重なるようなエネルギでドーパントを打込む工程を含む、請求項19に記載のプロセス。
- 前記第1導電型のドーパントを打込む工程は、前記第1導電型の前記ウェルが前記深い層を通って前記深い層の下に延びるようなエネルギでドーパントを打込む工程を含む、請求項19に記載のプロセス。
- 前記深い層および前記側壁部は一緒になって前記基板における取囲まれた領域を取囲み、前記プロセスは、前記取囲まれた領域内に前記第2導電型のウェルを形成するように前記第2導電型のドーパントを打込む工程を備える、請求項1に記載のプロセス。
- 前記第2導電型のウェルを形成するように前記第2導電型のドーパントを打込む工程は、前記第2導電型の前記ウェルが前記深い層から隔てられるようなエネルギでドーパントを打込む工程を含む、請求項23に記載のプロセス。
- 前記第2導電型のウェルを形成するように前記第2導電型のドーパントを打込む工程は、前記第2導電型の前記ウェルが前記深い層に重なるようなエネルギでドーパントを打込む工程を含む、請求項23に記載のプロセス。
- 前記取囲まれた領域内に前記第2導電型のウェルを形成するように前記第2導電型のドーパントを打込む工程を備える、請求項23に記載のプロセス。
- 半導体装置の製造プロセスであって、
エピタキシャル層を含まない、第1導電型の半導体基板を設ける工程と、
横方向の次元で第1の深い層の場所を規定する第1の開口部を有する第1のマスクを、前記基板の表面上に形成する工程と、
前記第1の深い層を形成するように前記第1の開口部を通じて第2導電型のドーパントを打込む工程と、
前記横方向の次元で第2の深い層の場所を規定し、前記第1の開口部の幅よりも小さい幅を有する第2の開口部を有する第2のマスクを、前記基板の前記表面上に形成する工程と、
前記第2の深い層を形成するように前記第2の開口部を通じて前記第1導電型のドーパントを打込む工程とを備え、
前記第1導電型のドーパントを打込む前記工程の打込み範囲は前記第2導電型のドーパントを打込む前記工程の打込み範囲よりも小さく、前記第2の深い層は前記第1の深い層に重なって前記第1の深い層の上に延びる、プロセス。 - 半導体装置の製造プロセスであって、
エピタキシャル層を含まない、第1導電型の半導体基板を設ける工程と、
横方向の次元で第1の深い層の場所を規定する第1の開口部を有する第1のマスクを、前記基板の表面上に形成する工程と、
前記第1の深い層を形成するように前記第1の開口部を通じて第2導電型のドーパントを打込む工程と、
前記横方向の次元で第2の深い層の場所を規定し、第1の開口部の幅よりも小さい幅を有する第2の開口部を有する第2のマスクを、前記基板の前記表面上に形成する工程と、
前記第2の深い層を形成するように前記第2の開口部を通じて前記第1導電型のドーパントを打込む工程とを備え、
前記第1導電型のドーパントを打込む前記工程の打込み範囲は前記第2導電型のドーパントを打込む前記工程の打込み範囲よりも大きく、前記第2の深い層は前記第1の深い層に重なって前記第1の深い層の下に延びる、プロセス。 - 半導体装置の製造プロセスであって、
エピタキシャル層を含まない、第1導電型の半導体基板を設ける工程と、
横方向の次元で第1の深い層の場所を規定する第1の開口部を有する第1のマスクを、前記基板の表面上に形成する工程と、
前記第1の深い層を形成するように前記第1の開口部を通じて第2導電型のドーパントを打込む工程と、
前記横方向の次元で第2の深い層の場所を規定し、前記第1の開口部の幅よりも小さい幅を有する第2の開口部を有する第2のマスクを、前記基板の前記表面上に形成する工程と、
前記第2の深い層を形成するように前記第2の開口部を通じて前記第1導電型のドーパントを打込む工程とを備え、
前記第1導電型のドーパントを打込む前記工程の散在は前記第2導電型のドーパントを打込む前記工程の散在よりも小さく、前記第2の深い層は前記第1の深い層に重なって前記第1の深い層の上および下に延びる、プロセス。 - 前記第1導電型の前記ドーパントはボロンを含み、前記第2導電型の前記ドーパントはリンを含む、請求項29に記載のプロセス。
- 半導体装置の製造プロセスであって、
エピタキシャル層を含まない、第1導電型の半導体基板を設ける工程と、
横方向の次元で第1の深い層の場所を規定する第1の開口部を有する第1のマスクを、前記基板の表面上に形成する工程と、
前記第1の深い層を形成するように前記第1の開口部を通じて第2導電型のドーパントを打込む工程と、
前記横方向の次元で第2の深い層の場所を規定し、前記第1の開口部の幅よりも小さい幅を有する第2の開口部を有する第2のマスクを、前記基板の前記表面上に形成する工程と、
前記第2の深い層のうち、前記第1の深い層に重なって前記第1の深い層の上に延びる第1の部分が形成されるような第1のエネルギで、前記第2の開口部を通じて前記第1導電型のドーパントを打込む工程と、
前記第2の深い層のうち、前記第1の深い層に重なって前記第1の深い層の下に延びる第2の部分が形成されるような第2のエネルギで、前記第2の開口部を通じて前記第1導電型のドーパントを打込む工程とを備える、プロセス。 - 半導体装置の製造プロセスであって、
エピタキシャル層を含まない、第1導電型の半導体基板を設ける工程と、
第1の厚さを有する第1のセクションと、
前記第1のセクションの両側に位置し、前記第1の厚さよりも大きい第2の厚さを有する、第2および第3のセクションと
を含む階段状の段差マスク層を、前記基板の表面上に形成する工程と、
前記基板における取囲まれた領域を前記基板の残りの部分から分離する分離領域を前記基板の中に形成するように前記マスク層を通じて第2導電型のドーパントを打込む工程と、
前記マスク層を除去する工程とを備える、プロセス。 - 前記分離領域は側壁部を含み、前記側壁部は、前記基板のうちそれぞれ前記マスク層の前記第2および第3のセクションの下の区域内の表面に達する、請求項32に記載のプロセス。
- 前記取囲まれた領域は前記マスク層の前記第1のセクションの略直下に位置する、請求項32に記載のプロセス。
- 前記マスク層は酸化物を含む、請求項34に記載のプロセス。
- 半導体装置の製造プロセスであって、
エピタキシャル層を含まない、第1導電型の半導体基板を設ける工程と、
前記基板の第1の区域の上に亘って窒化物層を形成する工程と、
前記第1の区域の第1の側にある第2の区域および前記第1の区域の第2の側にある第3の区域に酸化物層を成長させる工程とを備え、前記窒化物層は前記酸化物層が前記第1の区域内に成長することを実質的に防止し、前記プロセスはさらに、
前記窒化物層を除去する工程と、
第2導電型のドーパントを前記基板内に打込む工程とを備え、前記ドーパントは、前記基板における取囲まれた領域を前記基板の残りの部分から分離する分離領域を形成する、プロセス。 - 前記取囲まれた領域は前記基板の前記第1の区域の略下にある、請求項36に記載のプロセス。
- 前記取囲まれた領域内に前記第2導電型のウェルを形成するように第2導電型のドーパントを打込む工程を備える、請求項36に記載のプロセス。
- 前記取囲まれた領域内に前記第1導電型のウェルを形成するように前記第1導電型のドーパントを打込む工程を備える、請求項38に記載のプロセス。
- 前記基板の前記第3の区域に隣接する第4の区域の上に亘って第2の窒化物層を形成する工程と、
前記第2の窒化物層の前記第3の区域とは反対の側にある前記基板の第5の区域に酸化物層を成長させる工程とを備え、
前記第2導電型のドーパントを打込む工程は、前記基板の第2の取囲まれた領域を取囲む第2の分離領域を形成する、請求項36に記載のプロセス。 - 前記第1の分離領域に重なる第1のコンタクト領域と、前記第2の分離領域に重なる第2のコンタクト領域とを形成する工程を備える、請求項40に記載のプロセス。
- 前記第2導電型のドーパントを打込む工程は前記基板の前記第3の区域の下に連結領域を形成し、ドープした前記領域は、前記第1および第2の分離領域間に電気接触をもたらす、請求項40に記載のプロセス。
- 半導体装置の製造プロセスであって、
エピタキシャル層を含まない、第1導電型の半導体基板を設ける工程と、
前記基板における取囲まれた領域を取囲む第2導電型の環状領域を形成するように前記第2導電型のドーパントを打込む工程と、
前記環状領域を拡散させるように前記基板を加熱する工程と、
前記取囲まれた領域内に前記第1導電型のウェルを形成するように前記第1導電型のドーパントを打込む工程と、
前記ウェルを拡散させるように前記基板を加熱する工程と、
前記環状領域に重なって分離領域を形成する深い層を形成するように、前記第2導電型のドーパントを打込む工程とを備える、プロセス。 - 半導体装置の製造プロセスであって、
エピタキシャル層を含まない、第1導電型の半導体基板を設ける工程と、
前記基板内に深い層を形成するように第2導電型のドーパントを打込む工程と、
前記深い層の中まで延びるトレンチを前記基板の中に形成する工程と、
誘電材料を前記トレンチ内に導入する工程とを備え、前記トレンチおよび前記深い層は分離構造を形成して、前記基板における取囲まれた領域を取囲む、プロセス。 - 半導体装置の製造プロセスであって、
エピタキシャル層を含まない、第1導電型の半導体基板を設ける工程と、
深い層の中まで延びるトレンチを前記基板内に形成する工程と、
前記トレンチ内に誘電材料を導入する工程と、
前記トレンチから延びて前記基板における分離された領域を取囲む埋没領域を形成するように第2導電型のドーパントを打込む工程とを備える、プロセス。
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