JP2014207464A - 分離されたcmosおよびバイポーラトランジスタ、それらのための分離構造、ならびにその作製方法 - Google Patents
分離されたcmosおよびバイポーラトランジスタ、それらのための分離構造、ならびにその作製方法 Download PDFInfo
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- Crystallography & Structural Chemistry (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
本願は、2007年8月8日に出願された出願番号11/890,993の一部継続出願である。出願番号11/890,993は、2006年5月31日に出願された出願番号11/444,102の継続出願であり、以下の出願の一部継続出願である。以下の出願とは、(a)2002年8月14日に出願された出願番号10/218,668、現在の米国特許第6,900,091号の分割出願である、2004年8月14日に出願された出願番号10/918,316、および、(b)2002年8月14日に出願された出願番号10/218,678、現在の米国特許第6,943,426号の分割出願である、2005年8月15日に出願された出願番号11/204,215である。上記の出願および特許の各々は、全文が引用によって本明細書に援用される。
半導体集積回路(integrated circuit)(IC)チップの作製の際に、異なるデバイスを半導体基板から電気的に分離すること、および、異なるデバイスを互いに電気的に分離することがしばしば必要である。デバイスを横方向に分離する1つの方法は周知のシリコンの局所酸化(Local Oxidation Of Silicon)(LOCOS)プロセスであり、このプロセスでは、チップの表面が窒化シリコンなどの比較的硬質の材料でマスキングされ、厚い酸化物層がマスクの開口において熱的に成長する。別の方法は、シリコンにトレンチをエッチングし、次いで、酸化シリコンなどの誘電性材料でトレンチを充填するというものであり、これはトレンチアイソレーションとしても知られている。LOCOSもトレンチアイソレーションもデバイス間の不要な表面導通を防ぐことができるが、完全な電気的分離を容易にすることはない。
タを含む特定のタイプのトランジスタを集積するために必要である。完全な分離は、CMOS制御回路が動作中に基板電位をはるかに上回る電位に浮動することができるようにするためにも必要である。完全な分離は、アナログ、パワーおよび混合信号集積回路の作製の際に特に重要である。
この発明の分離されたCMOSトランジスタは、基板の分離されたポケットに形成され、分離されたポケットは、基板とは逆の導電型のフロア分離領域と、基板の表面から少なくともフロア分離領域まで下向きに延びる充填されたトレンチと境を接している。充填されたトレンチは、誘電性材料を備え、誘電性材料で完全に充填されてもよく、または、誘電性材料で裏打ちされた壁を有し、基板の表面からフロア分離領域まで延びる導電性材料を含んでいてもよい。基板はエピタキシャル層を含んでおらず、これは上述の多くの問題を回避する。
1つのプロセスは、第1の導電型の半導体基板の表面の上方に第1のマスク層を形成するステップと、第1のマスク層に第1の開口を形成するために第1のマスク層をパターニングするステップと、フロア分離領域を形成するために第1のマスク層の開口を通して第2の導電型のドーパントを注入するステップとを備え、フロア分離領域は基板の表面の下方に上部境界を有し、上記プロセスはさらに、第1のマスク層の開口内で基板の表面の上方に第2のマスク層を形成するステップを備え、第2のマスク層の端縁は第1のマスク層の第1の開口の端縁から隔てられて間隙を作り、上記プロセスはさらに、トレンチを形成するために間隙を通して基板をエッチングするステップを備え、トレンチは少なくともフロア分離領域まで下向きに延びており、上記プロセスはさらに、基板の分離されたポケットを形成するために誘電性材料をトレンチに導入するステップを備える。
最初に、この発明に従って作製することができる種々の分離されたCMOSおよびバイポーラトランジスタについて説明する。これに続いて、分離構造を作製するための代替的なプロセスフローについて説明する。
Claims (10)
- 集積回路デバイスのための分離構造を形成するためのプロセスであって、
第1の導電型の半導体基板を設けるステップを備え、前記基板はエピタキシャル層を備えておらず、前記プロセスはさらに、
前記基板の表面の上方に第1のマスク層を形成するステップと、
前記第1のマスク層に開口を形成するために前記第1のマスク層をパターニングするステップと、
フロア分離領域を形成するために前記第1のマスク層の前記開口を通して第2の導電型のドーパントを注入するステップとを備え、前記フロア分離領域は、前記基板の前記表面の下方に上部境界を有し、前記プロセスはさらに、
前記第1のマスク層の前記開口内で前記基板の前記表面の上方に第2のマスク層を形成するステップと、
前記第2のマスク層の上方に第3のマスク層を形成するステップを備え、前記第3のマスク層の端縁は、前記第1のマスク層の前記開口の端縁から隔てられて間隙を作り、前記プロセスはさらに、
トレンチを形成するために前記間隙を通して前記第2のマスク層および前記基板をエッチングするステップを備え、前記トレンチは、少なくとも前記フロア分離領域まで下向きに延びている、プロセス。 - 前記トレンチを完全に充填するように誘電性材料を堆積させることによって前記トレンチを充填するステップをさらに備える、請求項1に記載のプロセス。
- 前記トレンチの側壁をコーティングするように誘電性材料を堆積させ、前記トレンチを完全に充填するように導電性材料を堆積させることによって前記トレンチを充填するステップをさらに備える、請求項1に記載のプロセス。
- 前記第2の導電型のドーパントを注入するステップは、100万電子ボルトから300万電子ボルトを超える範囲のエネルギーで前記第2の導電型のドーパントを注入するステップを含む、請求項1〜請求項3のいずれか1項に記載のプロセス。
- 前記第2の導電型のドーパントを注入するステップは、
1E12cm-2〜1E14cm-2の範囲の投与量で、前記第2の導電型のドーパントを注入するステップを含む、請求項4に記載のプロセス。 - 前記第2の導電型のドーパントを注入するステップは、
5E12cm-2〜5E13cm-2の範囲の投与量で、前記第2の導電型のドーパントを注入するステップを含む、請求項4に記載のプロセス。 - 前記プロセスは、さらに、
前記第1のマスク層の前記開口を通して前記第2の導電型のドーパントを注入するのに先立って、前記第1のマスク層の前記開口の上に薄い酸化物を形成するステップをさらに備える、請求項1〜請求項6のいずれか1項に記載のプロセス。 - 前記第2の酸化膜の上方に前記第3のマスク層を形成するステップは、
前記第2の酸化膜の上方に前記第3のマスク層を形成して、前記第3のマスク層の前記端縁と、前記第1のマスク層の前記開口の前記端縁との間の前記間隙により前記第3のマスク層を囲むステップを含む、請求項1〜請求項7のいずれか1項に記載のプロセス。 - 前記トレンチを形成するために前記間隙を通して前記第2のマスク層および前記基板をエッチングするステップは、
少なくとも前記フロア分離領域へと下向きに延びるトレンチを形成して、前記トレンチが前記フロア分離領域とともに、前記半導体基板のポケットを分離する、請求項8に記載のプロセス。 - 前記プロセスは、
前記半導体基板に、複数の浅いトレンチを形成するステップをさらに備え、
前記複数の浅いトレンチの各々の浅いトレンチは、下方に延びるとともに、前記フロア分離領域に接触する前に終端する、請求項1〜請求項9のいずれか1項に記載のプロセス。
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TWI462271B (zh) | 2014-11-21 |
US20080210980A1 (en) | 2008-09-04 |
US8089129B2 (en) | 2012-01-03 |
JP2011512672A (ja) | 2011-04-21 |
WO2009102499A3 (en) | 2009-11-12 |
TW200945557A (en) | 2009-11-01 |
KR20100132953A (ko) | 2010-12-20 |
CN105206560B (zh) | 2018-03-27 |
WO2009102499A2 (en) | 2009-08-20 |
KR101307695B1 (ko) | 2013-09-11 |
EP2243158A4 (en) | 2013-08-21 |
CN105206560A (zh) | 2015-12-30 |
JP5908530B2 (ja) | 2016-04-26 |
JP2016164989A (ja) | 2016-09-08 |
CN102037558B (zh) | 2015-11-25 |
JP6349337B2 (ja) | 2018-06-27 |
HK1212819A1 (zh) | 2016-06-17 |
EP2243158A2 (en) | 2010-10-27 |
CN102037558A (zh) | 2011-04-27 |
EP2243158B1 (en) | 2016-10-19 |
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