JP4906267B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 41
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000012535 impurity Substances 0.000 claims description 44
- 239000000758 substrate Substances 0.000 claims description 44
- 238000005468 ion implantation Methods 0.000 claims description 27
- 239000004020 conductor Substances 0.000 claims description 14
- 230000002093 peripheral effect Effects 0.000 claims description 11
- 238000000605 extraction Methods 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 21
- 229910052710 silicon Inorganic materials 0.000 description 21
- 239000010703 silicon Substances 0.000 description 21
- 230000001133 acceleration Effects 0.000 description 15
- 238000009826 distribution Methods 0.000 description 11
- 238000002513 implantation Methods 0.000 description 11
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 9
- 238000011835 investigation Methods 0.000 description 9
- 238000002955 isolation Methods 0.000 description 9
- 229910052698 phosphorus Inorganic materials 0.000 description 9
- 239000011574 phosphorus Substances 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 7
- 230000005465 channeling Effects 0.000 description 6
- 230000007423 decrease Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 239000013078 crystal Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
- H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Description
は、ベース領域53の付近のN型不純物の濃度を高めることなく、コレクタ引出部58近傍のN型不純物の濃度を局所的に高めることができる。そのため、エミッタ−コレクタ間の耐圧BVceoの低下を抑えつつ、コレクタ抵抗を低減することが可能となる。
層12aとの導電抵抗が低く抑えられ、ひいてはコレクタ抵抗の低減が図られるようになる。
る。なお図5(a),(b)には、STI構造15の下面とP型シリコン基板11との界面(STI/Si界面)の深さが点線で表されている。
TI構造15下のコレクタ領域12の高濃度層12aが浅くなるにつれ、図1の破線円に示されるコレクタ引出部18周縁部がSTI構造15下の高濃度層12aと近接するためである。一方、上記深さの差Δpが0.25マイクロメータ付近を超えて更に大きくなると、同深さの差Δpの増大とともにコレクタ抵抗が増加していく。これは、高濃度層12aがある程度よりも浅くなると、その一部がSTI構造15内に入り込んでしまい、STI構造15下の導電層の幅が狭くなってしまうためである。
抵抗を低減することができる。
Claims (2)
- 第1導電体型の半導体基板と、前記半導体基板の内部に形成された第2導電体型のコレクタ領域と、前記半導体基板の主表面から形成され、前記主表面側を少なくとも2つの活性領域へと分離する溝と、前記主表面と平坦になるように前記溝を埋設する絶縁膜と、前記一方の活性領域に形成された第2導電体型のコレクタ引出部と、前記他方の活性領域上に形成された第1導電体型のベース領域および第2導電体型のエミッタ領域とを有して構成された双極性トランジスタを備え、
前記コレクタ引出部は、前記絶縁膜の側壁に沿って、前記絶縁膜の底面よりも深い拡散領域を有し深くまで拡散し、
前記主表面から前記コレクタ領域の不純物濃度のピークまでの深さは、前記一方の活性領域の下方よりも、前記絶縁膜下方の方が浅くなり、且つ、前記コレクタ領域は、少なくとも前記コレクタ引出部の周囲を囲む前記絶縁膜の底面の周縁部に沿って配置され、
前記一方の活性領域下方での前記不純物濃度のピークまでの深さと前記絶縁膜下方の前記不純物濃度のピークまでの深さとの差は、0.1〜0.3μmとすることを特徴とする半導体装置。 - 第1導電体型の半導体基板の内部に形成される第2導電体型のコレクタ領域と、前記半導体基板の主表面から形成され、前記主表面側を少なくとも2つの活性領域へと分離する溝と、前記主表面と平坦になるように前記溝を埋設する絶縁膜と、前記一方の活性領域に形成される第2導電体型のコレクタ引出部と、前記他方の活性領域上に形成される第1導電体型のベース領域及び第2導電体型のエミッタ領域と、を有して構成される双極性トランジスタを備える半導体装置の製造方法であって、
前記半導体基板の主表面に前記溝を形成し、前記溝を前記絶縁膜にて埋設し、前記絶縁膜の表面と前記主表面とを平坦面に形成する工程と、
前記半導体基板上面からイオン注入を行い、前記絶縁膜の側壁に沿って、前記絶縁膜の底面よりも深くまで拡散するように前記コレクタ引出部を形成する工程と、
前記半導体基板に対してその主表面に垂直な角度でイオン注入を行い、前記主表面から前記コレクタ領域の不純物濃度のピークまでの深さが、前記一方の活性領域の下方よりも、前記絶縁膜下方の方が浅くなり、且つ、少なくとも前記コレクタ引出部の周囲を囲む前記絶縁膜の底面の周縁部に沿って、前記コレクタ領域の不純物濃度のピークまでの深さの浅い領域が配置されるように、前記コレクタ領域を形成する工程と、
前記コレクタ領域の形成された前記半導体基板の前記他方の活性領域上に、前記ベース領域及び前記エミッタ領域をそれぞれ形成する工程と、を有することを特徴とする半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005100949A JP4906267B2 (ja) | 2005-03-31 | 2005-03-31 | 半導体装置及びその製造方法 |
US11/392,613 US7459766B2 (en) | 2005-03-31 | 2006-03-30 | Semiconductor bipolar transistor |
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JP2005100949A JP4906267B2 (ja) | 2005-03-31 | 2005-03-31 | 半導体装置及びその製造方法 |
Publications (2)
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JP2006286695A JP2006286695A (ja) | 2006-10-19 |
JP4906267B2 true JP4906267B2 (ja) | 2012-03-28 |
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JP2005100949A Expired - Fee Related JP4906267B2 (ja) | 2005-03-31 | 2005-03-31 | 半導体装置及びその製造方法 |
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JP (1) | JP4906267B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8089129B2 (en) * | 2002-08-14 | 2012-01-03 | Advanced Analogic Technologies, Inc. | Isolated CMOS transistors |
WO2007142622A1 (en) * | 2006-06-02 | 2007-12-13 | Agere Systems Inc. | Bipolar junction transistor with a reduced collector- substrate capacitance |
US8110483B2 (en) * | 2009-10-22 | 2012-02-07 | International Business Machines Corporation | Forming an extremely thin semiconductor-on-insulator (ETSOI) layer |
US9343458B2 (en) * | 2011-09-29 | 2016-05-17 | Taiwan Semiconductor Manufacturing Company Limited | Isolation structure for ESD device |
Family Cites Families (15)
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DE2529598C3 (de) * | 1975-07-02 | 1978-05-24 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Verfahren zur Herstellung einer monolithisch integrierten Halbleiterschaltung mit bipolaren Transistoren |
JP2746499B2 (ja) * | 1992-05-15 | 1998-05-06 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
JPH08107114A (ja) * | 1994-10-04 | 1996-04-23 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2748898B2 (ja) * | 1995-08-31 | 1998-05-13 | 日本電気株式会社 | 半導体装置およびその製造方法 |
US6570242B1 (en) * | 1997-11-20 | 2003-05-27 | Texas Instruments Incorporated | Bipolar transistor with high breakdown voltage collector |
US6232165B1 (en) * | 1998-12-09 | 2001-05-15 | Winbond Electronics Corporation | Buried guard rings and method for forming the same |
US6117747A (en) * | 1999-11-22 | 2000-09-12 | Chartered Semiconductor Manufacturing Ltd. | Integration of MOM capacitor into dual damascene process |
US6458648B1 (en) * | 1999-12-17 | 2002-10-01 | Agere Systems Guardian Corp. | Method for in-situ removal of side walls in MOM capacitor formation |
US6680542B1 (en) * | 2000-05-18 | 2004-01-20 | Agere Systems Inc. | Damascene structure having a metal-oxide-metal capacitor associated therewith |
JP2004079719A (ja) | 2002-08-15 | 2004-03-11 | Nec Electronics Corp | 半導体装置及びその製造方法 |
JP2004087599A (ja) | 2002-08-23 | 2004-03-18 | Nec Electronics Corp | 半導体装置及びその製造方法 |
US6630377B1 (en) * | 2002-09-18 | 2003-10-07 | Chartered Semiconductor Manufacturing Ltd. | Method for making high-gain vertical bipolar junction transistor structures compatible with CMOS process |
US6639284B1 (en) * | 2002-10-25 | 2003-10-28 | Texas Instruments Incorporated | Compensated-well electrostatic discharge protection structure |
DE10314574B4 (de) * | 2003-03-31 | 2007-06-28 | Infineon Technologies Ag | Verfahren zur Herstellung einer Grabenisolationsstruktur |
JP2005026523A (ja) * | 2003-07-03 | 2005-01-27 | Ricoh Co Ltd | 半導体装置 |
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2005
- 2005-03-31 JP JP2005100949A patent/JP4906267B2/ja not_active Expired - Fee Related
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- 2006-03-30 US US11/392,613 patent/US7459766B2/en active Active
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US20060220104A1 (en) | 2006-10-05 |
US7459766B2 (en) | 2008-12-02 |
JP2006286695A (ja) | 2006-10-19 |
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