IT1250772B - Dispositivo di memoria a semiconduttori con condensatore impilato. - Google Patents
Dispositivo di memoria a semiconduttori con condensatore impilato.Info
- Publication number
- IT1250772B IT1250772B ITRM910657A ITRM910657A IT1250772B IT 1250772 B IT1250772 B IT 1250772B IT RM910657 A ITRM910657 A IT RM910657A IT RM910657 A ITRM910657 A IT RM910657A IT 1250772 B IT1250772 B IT 1250772B
- Authority
- IT
- Italy
- Prior art keywords
- zone
- source
- memory device
- semiconductor memory
- substrate
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
Landscapes
- Semiconductor Memories (AREA)
Abstract
Viene illustrato un dispositivo di memoria a semiconduttori con un condensatore impilato. Quando si produce un disallineamento nel formare la zona 42 di contatto per il contatto tra l'elettrodo di immagazzinamento del condensatore impilato e la zona 34 di sorgente, viene eseguito il procedimento di impianto di ioni con lo stesso tipo di conduttività della regione di sorgente, per formare l'altra zona 48 di sorgente sotto la superficie inferiore della zona 42 di contatto in cui viene impiegato come maschera lo strato di silicio policristallino sul substrato. Il successivo impianto ionico fornisce la zona di diffusione 58 in grado di circondare interamente l'altra zona 48 di sorgente, in cui la zona 58 di diffusione contiene una più elevata concentrazione rispetto a quella del substrato e simultaneamente più bassa di quella della zona di sorgente, con lo stesso tipo di conduttività del substrato. D'altro canto, quando non si produce un disallineamento, il dispositivo di memoria al semiconduttore comprende inoltre un'altra zona 58a di diffusione formata sotto la zona 34a di sorgente, la zona di diffusione 58a avendo tipo di conduttività opposto rispetto a quello della zona di sorgente. Di conseguenza, si fornisce un dispositivo a memoria con miglioramento nelle caratteristiche di rinfresco e con diminuzione del tasso di errore "soft".
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910002988A KR930009127B1 (ko) | 1991-02-25 | 1991-02-25 | 스택형캐패시터를구비하는반도체메모리장치 |
Publications (3)
Publication Number | Publication Date |
---|---|
ITRM910657A0 ITRM910657A0 (it) | 1991-09-03 |
ITRM910657A1 ITRM910657A1 (it) | 1992-08-26 |
IT1250772B true IT1250772B (it) | 1995-04-21 |
Family
ID=19311444
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ITRM910657A IT1250772B (it) | 1991-02-25 | 1991-09-03 | Dispositivo di memoria a semiconduttori con condensatore impilato. |
Country Status (8)
Country | Link |
---|---|
US (1) | US5208470A (it) |
JP (1) | JP2532182B2 (it) |
KR (1) | KR930009127B1 (it) |
DE (1) | DE4129130C2 (it) |
FR (1) | FR2673325B1 (it) |
GB (1) | GB2253092B (it) |
IT (1) | IT1250772B (it) |
TW (1) | TW198117B (it) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3212150B2 (ja) * | 1992-08-07 | 2001-09-25 | 株式会社日立製作所 | 半導体装置 |
JP3653107B2 (ja) * | 1994-03-14 | 2005-05-25 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
KR100190834B1 (ko) * | 1994-12-08 | 1999-06-01 | 다니구찌 이찌로오, 기타오카 다카시 | 반도체장치및그제조방법 |
TW288200B (en) * | 1995-06-28 | 1996-10-11 | Mitsubishi Electric Corp | Semiconductor device and process thereof |
KR100239690B1 (ko) * | 1996-04-30 | 2000-01-15 | 김영환 | 반도체 메모리 셀의 필드산화막 형성방법 |
US6021064A (en) * | 1998-02-04 | 2000-02-01 | Vlsi Technology, Inc. | Layout for data storage circuit using shared bit line and method therefor |
US6072713A (en) * | 1998-02-04 | 2000-06-06 | Vlsi Technology, Inc. | Data storage circuit using shared bit line and method therefor |
KR100292943B1 (ko) | 1998-03-25 | 2001-09-17 | 윤종용 | 디램장치의제조방법 |
KR100464414B1 (ko) * | 2002-05-02 | 2005-01-03 | 삼성전자주식회사 | Dc 노드와 bc 노드에 연결된 소오스/드레인 접합영역의 접합 프로파일이 서로 다른 디램 소자의 메모리 셀트랜지스터 및 그 제조방법 |
JP5191132B2 (ja) * | 2007-01-29 | 2013-04-24 | 三菱電機株式会社 | 半導体装置 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5574175A (en) * | 1978-11-29 | 1980-06-04 | Nec Corp | Preparing interpolation type mos semiconductor device |
JPS56134757A (en) * | 1980-03-26 | 1981-10-21 | Nec Corp | Complementary type mos semiconductor device and its manufacture |
JPS5885559A (ja) * | 1981-11-18 | 1983-05-21 | Nec Corp | Cmos型半導体集積回路装置 |
JPS61156862A (ja) * | 1984-12-28 | 1986-07-16 | Toshiba Corp | 半導体記憶装置 |
JPS6260256A (ja) * | 1985-09-10 | 1987-03-16 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
JPS62114265A (ja) * | 1985-11-13 | 1987-05-26 | Mitsubishi Electric Corp | 半導体記憶装置 |
KR900002474B1 (ko) * | 1985-11-22 | 1990-04-16 | 미쓰비시 뎅기 가부시끼가이샤 | 반도체 메모리 |
KR900003028B1 (ko) * | 1985-12-13 | 1990-05-04 | 미쓰비시 뎅기 가부시끼가이샤 | 반도체 집적회로장치 |
JPS62145860A (ja) * | 1985-12-20 | 1987-06-29 | Mitsubishi Electric Corp | 半導体記憶装置の製造方法 |
JPS63260065A (ja) * | 1987-04-17 | 1988-10-27 | Hitachi Ltd | 半導体記憶装置とその製造方法 |
JPS63318150A (ja) * | 1987-06-22 | 1988-12-27 | Oki Electric Ind Co Ltd | Dramメモリセルの製造方法 |
JPS63318151A (ja) * | 1987-06-22 | 1988-12-27 | Oki Electric Ind Co Ltd | Dramメモリセル |
JPH01120862A (ja) * | 1987-11-04 | 1989-05-12 | Oki Electric Ind Co Ltd | 半導体メモリ装置の製造方法 |
DE3918924C2 (de) * | 1988-06-10 | 1996-03-21 | Mitsubishi Electric Corp | Herstellungsverfahren für eine Halbleiterspeichereinrichtung |
JPH02101769A (ja) * | 1988-10-11 | 1990-04-13 | Mitsubishi Electric Corp | 半導体記憶装置 |
JPH07114257B2 (ja) * | 1988-11-15 | 1995-12-06 | 三菱電機株式会社 | 半導体装置 |
US5068707A (en) * | 1990-05-02 | 1991-11-26 | Nec Electronics Inc. | DRAM memory cell with tapered capacitor electrodes |
-
1991
- 1991-02-25 KR KR1019910002988A patent/KR930009127B1/ko not_active IP Right Cessation
- 1991-07-30 US US07/738,132 patent/US5208470A/en not_active Expired - Lifetime
- 1991-08-02 TW TW080106061A patent/TW198117B/zh not_active IP Right Cessation
- 1991-08-20 FR FR9110439A patent/FR2673325B1/fr not_active Expired - Lifetime
- 1991-09-02 DE DE4129130A patent/DE4129130C2/de not_active Expired - Lifetime
- 1991-09-03 GB GB9118795A patent/GB2253092B/en not_active Expired - Lifetime
- 1991-09-03 IT ITRM910657A patent/IT1250772B/it active IP Right Grant
- 1991-09-03 JP JP3248446A patent/JP2532182B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
ITRM910657A0 (it) | 1991-09-03 |
DE4129130A1 (de) | 1992-09-03 |
TW198117B (it) | 1993-01-11 |
GB2253092B (en) | 1994-11-16 |
GB2253092A (en) | 1992-08-26 |
KR920017249A (ko) | 1992-09-26 |
FR2673325A1 (fr) | 1992-08-28 |
ITRM910657A1 (it) | 1992-08-26 |
FR2673325B1 (fr) | 1997-03-14 |
KR930009127B1 (ko) | 1993-09-23 |
DE4129130C2 (de) | 1995-03-23 |
JP2532182B2 (ja) | 1996-09-11 |
US5208470A (en) | 1993-05-04 |
GB9118795D0 (en) | 1991-10-16 |
JPH04278579A (ja) | 1992-10-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
0001 | Granted | ||
TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19970829 |