ES2003376A6 - Dispositivo de memoria dinamica y metodo para fabricarlo. - Google Patents

Dispositivo de memoria dinamica y metodo para fabricarlo.

Info

Publication number
ES2003376A6
ES2003376A6 ES8602599A ES8602599A ES2003376A6 ES 2003376 A6 ES2003376 A6 ES 2003376A6 ES 8602599 A ES8602599 A ES 8602599A ES 8602599 A ES8602599 A ES 8602599A ES 2003376 A6 ES2003376 A6 ES 2003376A6
Authority
ES
Spain
Prior art keywords
trench
sio2
dynamic random
random access
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES8602599A
Other languages
English (en)
Inventor
Nicky Chau-Chun Lu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of ES2003376A6 publication Critical patent/ES2003376A6/es
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H10B12/373—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate the capacitor extending under or around the transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

DISPOSITIVO DE MEMORIA DINAMICA Y METODO PARA FABRICARLO, EN DONDE EL DISPOSITIVO COMPRENDE UN SUSTRATO DE SILICIO MONOCRISTALINO PB, UN CONDENSADOR DE DEPRESION, UNA CAPA DE SILICIO EPITAXIAL MONOCRISTALINO, UN TRANSISTOR DE ACCESO Y UNA REGION DE SILICIO POLICRISTALINO NB, MIENTRAS QUE EL METODO COMPRENDE SITUAR UNA DEPRESION EN EL SUSTRATO, HABILITAR UNA PELICULA DE SIO2/SI3N4/SIO2 PARA AISLAR EL CONDENSADOR, SOBREPONER AL SILICIO POLICRISTALINO UNA DELGADA CAPA DE SIO2, APLICAR UNA CAPA DE SILICIO EPITAXIAL P SOBRE EL SUSTRATO Y LA CAPA DE SIO2, Y COLOCAR EL TRANSISTOR DE ACCESO ENCIMA DEL CONDENSADOR, CONECTANDO UN MATERIAL IMPURIFICADO NB LA REGION DE FUENTE DEL TRANSISTOR CON EL SILICIO POLICRISTALINO Y PUDIENDO DISPONERSE UNA REGION P IMPURIFICADA ENCIMA DE LA SUPERFICIE DE LA DEPRESION. EL INVENTO ES APLICABLE A MEMORIAS ELECTRONICAS DINAMICAS DE ACCESO ALEATORIO.
ES8602599A 1985-10-21 1986-10-15 Dispositivo de memoria dinamica y metodo para fabricarlo. Expired ES2003376A6 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/789,675 US4649625A (en) 1985-10-21 1985-10-21 Dynamic memory device having a single-crystal transistor on a trench capacitor structure and a fabrication method therefor

Publications (1)

Publication Number Publication Date
ES2003376A6 true ES2003376A6 (es) 1988-11-01

Family

ID=25148357

Family Applications (1)

Application Number Title Priority Date Filing Date
ES8602599A Expired ES2003376A6 (es) 1985-10-21 1986-10-15 Dispositivo de memoria dinamica y metodo para fabricarlo.

Country Status (13)

Country Link
US (1) US4649625A (es)
EP (1) EP0220410B1 (es)
JP (1) JPH06101546B2 (es)
KR (1) KR900002885B1 (es)
CN (1) CN1005883B (es)
AU (1) AU575499B2 (es)
BR (1) BR8604546A (es)
CA (1) CA1232362A (es)
DE (1) DE3688231T2 (es)
ES (1) ES2003376A6 (es)
HK (1) HK90993A (es)
IN (1) IN167820B (es)
ZA (1) ZA866625B (es)

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US5208657A (en) * 1984-08-31 1993-05-04 Texas Instruments Incorporated DRAM Cell with trench capacitor and vertical channel in substrate
US5225697A (en) * 1984-09-27 1993-07-06 Texas Instruments, Incorporated dRAM cell and method
US4824793A (en) * 1984-09-27 1989-04-25 Texas Instruments Incorporated Method of making DRAM cell with trench capacitor
US4791463A (en) * 1984-10-31 1988-12-13 Texas Instruments Incorporated Structure for contacting devices in three dimensional circuitry
US5102817A (en) * 1985-03-21 1992-04-07 Texas Instruments Incorporated Vertical DRAM cell and method
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Also Published As

Publication number Publication date
DE3688231D1 (de) 1993-05-13
DE3688231T2 (de) 1993-11-04
EP0220410A2 (en) 1987-05-06
JPS6298766A (ja) 1987-05-08
AU6307186A (en) 1987-04-30
CN86105868A (zh) 1987-06-10
CA1232362A (en) 1988-02-02
BR8604546A (pt) 1987-05-26
JPH06101546B2 (ja) 1994-12-12
EP0220410A3 (en) 1989-05-10
HK90993A (en) 1993-09-10
KR900002885B1 (ko) 1990-05-01
CN1005883B (zh) 1989-11-22
IN167820B (es) 1990-12-22
ZA866625B (en) 1987-06-24
US4649625A (en) 1987-03-17
EP0220410B1 (en) 1993-04-07
KR870004513A (ko) 1987-05-11
AU575499B2 (en) 1988-07-28

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Legal Events

Date Code Title Description
SA6 Expiration date (snapshot 920101)

Free format text: 2006-10-15

FD1A Patent lapsed

Effective date: 20001204