CN1005883B - 动态存贮器器件及其制造方法 - Google Patents
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Abstract
在沟槽电容器顶部叠放一个单晶存取数晶体管的三维动态随机存取存贮器器件结构及其制造方法,其中,籽晶由环绕电路单元的单晶半导体区域和/或沟槽的垂直侧壁所提供,而且其中的存取数晶体管由绝缘体加以隔离。在本结构中,沟槽位于包含N+重掺杂多晶硅的P+型衬底中。SiO2/Si3N4/SiO2复合膜用作电容存贮器的绝缘体。薄层SiO2安置在多晶硅之上。轻掺杂的P-型外延硅位于衬底和SiO2层之上。
Description
本发明涉及多种动态随机存取存贮器(DRAM)器件,其中,含有一个存取数晶体管和一个存贮电容器的分立电路单元是做在一个单晶半导体芯片上的,特别涉及到在沟槽电容器的顶部叠放单晶存取数晶体管的三维动态随机存取存贮器(DRAM)的器件结构及其制造方法。其中,生长单晶的籽晶来自围绕电路单元的单晶半导体表面和/或来自沟槽的垂直侧壁,而其中的存取数晶体管靠绝缘层加以隔离。
以下的参考文献为具有沟槽电容器的DRAM的典型现有技术。
1982年10月5日颁发给Jaccodine等人的美国专利4,353,086号,题头为“硅集成电路”,该专利描述一种动态随机存取存贮器,其分立电路单元-包括一个存取数晶体管和一个存贮电容器-是做在硅芯片上形成的平台中的。存取数晶体管是在平台的顶面形成的,电路单元的存贮电容器的一块极板由平台的侧壁构成,而另一极板由围绕平台的沟槽中所填充的掺杂多晶硅构成,而极板间用二氧化硅层加以绝缘。采用这种几何结构,电容器可以获得大的存贮表面,从而获得大的电容量;而无须使用芯片的表面面积。在其它的实施例中,平台可以包包括其他形式的电路元件。
1985年5月4日颁发给Imai等人的美国专利4,327,476号,题头为“制造半导体器件的方法”,该专利描述的方法所包含的步骤为:在半导体衬底的给定位置上至少形成一条沟槽;在包括沟槽在内的整个半导体衬底的表面上覆盖一层绝缘膜;在绝缘层上淀积导电材料至厚度大于沟槽开口的半宽度;并且做留在沟槽中的导电层的MOS电容器电极,其做法是腐蚀所淀积的导电层直至除了沟槽中那部分以外所有的绝缘膜暴露出来为止。
1984年7月31日频发结Thompson等人的美国专利4,462,847号,题头为“采用低压气相淀积选择生长制造介质绝缘的微电子半导体电路”,该专利描述一种微电子半导体电路的制造方法,包括在预定图形中同时低压淀积单晶和多晶半导体材料。采用这种选择处理生长和接着进行的单晶和多晶淀积层的氧化处理的办法制造了一种介质隔离的电路。通过控制单晶和多晶的淀积速率比值和控制氧化步骤,可使多晶淀积物相当充分地转变为氧化物,而单晶只是部分地被氧化,从而留下基本上共平面而又互相隔离的钝化单晶矩阵,在其中制造电路元件以供互连。
日本专利58-137245,该专利描述了一种无须增加平面面积而增加电极面积的技术,这种技术利用刻进硅衬底中的沟槽侧壁部分作为电容器电极的表面。通过Locos法在硅衬底上有选择地形成仿二氧化硅膜,并在衬底上刻蚀出沟槽,而由氮化硅(Si3N4)构成的电容器绝缘膜则通过CVD法在这些表面上形成。绝缘膜的整个表面覆盖上由多晶硅构成的薄层。与此同时在沟槽中填入同样的多晶硅。使多晶硅薄层氧化而形成第一层层间氧化膜。当利用该氧化膜作掩模时,可除去氮化硅(Si3N4)膜和二氧化硅(SiO2)膜。再通过氧化形成栅氧化膜。在预定部分覆盖上字线,通过离子注入在没有被多晶薄层及栅覆盖的部分形成源-漏层,然后有选择地覆盖上第二层层间绝缘膜和电极。
本发明的一个目地是要提供一种改进的DRAM器件结构及其制造工艺。
本发明的另一个目的是要提供一种改进的单管动态随机存取存贮电路单元的结构,这种结构具有一个叠放在沟槽电容器顶部的单晶晶体管。
本发明还有一个目的是要为DRAM器件提供一种无须采用任何再结晶技术就能在单晶体或薄膜材料上制造存取数晶体管的制造方法。
本发明的又一个目的是要为三维DRAM电路单元提供一种结构和制造方法,该电路具有一个SOI(由绝缘层上的硅所做成的)存取数晶体管和一个沟槽电容器,其中形成单晶的籽晶来自围绕电路单元周围的硅表面和沟槽的垂直侧壁,而电路的存取数晶体管由氧化层加以隔离。
通过下面结合附图对本发明作更详细的说明,本发明的前述的以及其他的目的、特点和长处就会一目了然。
图1为根据本发明的原理由块状材料制作的三维DRAM器件实施例的剖面示意图。
图2为图1中DRAM器件顶视图细节的示意图,画出了沟槽电容。
图3为根据本发明的原理由膜状材料制作的三维DRAM器件另一实施例的剖面示意图。
图4为三维DRAM器件又一个实施例的剖面示意图,它包括一个用CMOS技术制作的位于n-阱内的P-沟存取数晶体管。
图5、图6和图7说明了图1或图2的结构处于制造工艺中不同阶段的情况,其中存取数晶体管做在单晶块状区域中。
图8说明了图4中器件的存取数晶体管和沟槽电容器结构的顶视图细节。
图9和图10说明图3结构处于制造工艺不同阶段的情况,其中存取数晶体管做在单晶膜中。
图1画出了DRAM器件的剖面图。10为硅衬底,为便于说明起见,衬底为P+型。沟槽位于含有重掺杂N+多晶硅12的衬底10之中。二氧化硅/氮化硅/二氧化硅(SiO2/Si3N4/SiO2)复合膜14用作电容存贮器的绝缘体。SiO2薄层34安置在多晶硅12上。轻掺杂的P-型外延硅层30位于衬底及SiO2薄层34之上。
存贮单元的存取数晶体管位于沟槽电容器的顶部。N+掺杂的材料将晶体管的源区50和沟槽内的多晶硅12相连。在沟槽表面顶部设置了中等掺杂的P区16,以防沿着沟槽表面存在任何明显的泄漏电流,但是,此层并非该结构的必要部分。
晶体管的剩余部分包括与字线连接的栅极26。位线28也按照向下凹的绝缘体20的形状表示出来了。
依晶体管是做在块状材料成膜状材料的不同,两种电路单元的结构分别画在图1和图3中。
将晶体管叠放在沟槽电容的顶部,可以使动态RAM电路单元只占一个管子的面积即可做成。如不叠放的话,直接按比例缩小沟槽电容器单元,就必然会挤缩沟槽电容器的开口尺寸,其结果是为了存贮足够的电荷,就必须采用大的沟槽深/宽比。这就使得沟槽的腐蚀和回填工艺变得非常困难。采用叠放结构的话,因为沟槽的开口可以和晶体管的有源区一样大,所以可以获得较易实现的沟槽深/宽比。叠放电路单元还有另几个好处。例如因沿位线方向的几何尺寸较小,从而有较小的位线电容;因为信号电荷存贮在沟槽电容器内部,从而有较高的抗噪声度;还有较为平整的表面形貌。本发明的优点是提供了一种叠放电路单元的工艺技术。该单元有一个位于沟槽电容器顶上的单晶膜状或块状晶体管,而又不存在使多晶硅再结晶成单晶硅这种常见的难题。
如前所述,电路单元结构示于图1,存取数晶体管叠放在沟槽电容器的顶部,N+掺杂材料18将存取数晶体管的源区50与沟槽内的多晶硅12相连。中等掺杂的P区16正好加在沟槽表面的顶部,以防沿沟槽表面又存在显著的泄漏电流(P区并非必须的)。对于CMOS工艺中,位于n-阱内的P-沟道存取数晶体管,可以制造一个如图4所示的类似结构,只要把晶体管源/漏区和沟槽内多晶硅的掺杂剂极性从n型变成p型就行。为了形成n-阱需要一步额外的加工步骤。
制造图1所示电路单元结构的方法步骤说明如下:
第1步 假定硅衬底10在P+重掺杂圆片(它只能是P+圆片)顶部具有P-外延层30在P-外延层上面形成一个SiO2和Si3N4的复合层14。经适当的光刻步骤以后,去除部分Si3N4/SiO2层,留下一个窗口,这样通过反应离子刻蚀(RIE)就能在硅衬底中形成一个沟槽。
第2步 在热生长薄氧化层之后,淀积一层薄氮化层,并在氧化气氛中加热致密以形成二氧化硅/氮化硅/二氧化硅(SiO2/Si3N4/SiO2)复合层,作为电容存贮器介质层14。然后淀积一层填充沟槽用的厚多晶硅膜12并作n+重掺杂,如图5所示。
第3步 通过RIE法或机械-化学抛光技术将多晶硅膜12作平面化处理以使多晶硅表面和衬底表面对齐。衬底表面上的氮化层作为腐蚀终点。
第4步 然后在多晶硅表面上“局部”热生长一层薄二氧化硅层34。因为衬底的其余表面有氮化硅层覆盖着,所以在其余区域上不会生长氧化层。
第5步 在衬底上的氮化硅层通过各向同性腐蚀去除。然后,除多晶硅上的氧化层34之外,将衬底表面的所有氧化层全部除去。(在第4步中生长在多晶硅上的氧化层应比第2步中生长在氧化硅层下面的氧化层厚得多。)
第6步 然后外延生长一层轻掺杂的P型硅层22(图5)。因为除了一小部分沟槽区域之外所有单晶硅衬底被暴露在外延生长条件下。因此垂直和侧向外延都可以取得大量的单晶籽晶。当形成的外延膜厚度大于沟槽缝隙的半宽时,在沟槽区域就可获得单晶外延层。
第7步 然后在P-外延层上形成二氧化硅/氮化硅(SiO2/Si3N4)复合层32,如图6所示。经过适当的光刻步骤之后,部分氮化硅/二氧化硅层32被刻掉,留下窗口,这样,就能采用RIE法刻去硅和沟槽电容器12顶部的氧化物。
第8步 然后用本征多晶硅膜18回填入窗口,并用RIE法或机械-化学抛光技术作平面化处理,以使本征多晶硅表面和薄层22的硅表面对齐,如图6所示。在硅表面上薄层32的氮化物用作腐蚀终点。然后除去氮化物和氧化物掩蔽层32。
第9步 然后可以采用常规的ROX或浅沟槽隔离20(图7)。如果晶体管要做在n-阱内,需在电路单元区域作n-阱离子注入。
第10步 经隔离后,生长栅氧化层40,确定栅26,并形成氧化物/氮化物分隔器。通过N+掺杂剂的浅注入形成源/漏24,此注入必须覆盖住本征多晶硅区域18。因为本征多晶硅对源/漏掺杂剂具有很高的扩散率,经热处理后,本征多晶硅能成为重掺杂状态,从而为存取数器件的源区提供至沟槽内多晶硅的互连,如图7所示。此后,继续采用常规MOS工艺以完成电路单元结构。整个工艺也完全和CMOS工艺相兼容。
以上工艺步骤做成的电路单元结构示于图1或图4中,其中存取数晶体管做在单晶块状区域中。存取数晶体管本体是通过外延区22由衬底电压源直接偏置的,或由n-阱电压源偏置。从实用的观点看,如果存在因侧向外延生长引起的任何缺陷区域,这种缺陷区可以隐藏在源扩散区内,并且大部分缺陷可以在诸如对沟槽电容形成本征多晶硅填层18和形成隔离区(例如浅沟槽隔离)等步骤中除去,用作存取数晶体管沟道区的高质量外延层总是能保存下来(图8)。
类似的原理可以用来实现图3所示的单元电路结构,其中晶体管做在单晶膜中,并且其位置也可以通过完整的氧化隔离而恰恰限于沟槽电容器的平面范围之内。其制造步骤如下:
步骤A、B和前述的第1、2步相同。
步骤C 多晶硅膜18通过RIE法或机械-化学抛光技术作平面化处理。直到多晶硅表面“低于”衬底表面,如图9所示。在衬底表面上的氮化层42用作腐蚀终点。
步骤D、E和前述4、5步相同。
步骤F 然后外延生长一层轻掺杂的P-型硅层,如图10所示。因为除了很小的沟槽氧化区域之外,所有的单晶硅衬底和沟槽中氧化层以上的硅侧壁都暴露在外延生长条件下,因此垂直和侧向外延都可以获得大量的单晶籽晶。当形成外延膜的厚度大于沟槽缝隙的半宽时,在沟槽区域就可以获得单晶外延层52。
步骤G、H和前述第7、8步一样。
步骤I 然后可以采用常规的ROX或浅沟槽隔离。参照图3,完整的氧化隔离层44和46可以用来完全隔离位于沟槽电容器平面范围内的存取数晶体管膜层。虽然晶体管本体不能直接偏置,但是只要使晶体管膜层足够薄,就不会有显著的波动(kink)效应影响电路单元的工作。
步骤J和前述第10步一样。图3画出了最后的电路单元结构,其中存取数晶体管完全被氧化物隔离,因而寄生电容很小。
至此已对一种新型单管动态存贮单元结构作了说明,该结构将一个处于块状或膜状材料中的“单晶体”晶体管叠放在沟槽电容器的顶部。该单晶直接由外延而不是求助于再结晶工艺获得。
至此也对一种能在非单晶材料组成的沟槽电容器顶部生长单晶材料的新型工艺方法作了说明。此新方法的关键是沟槽电容器周围的硅区必须暴露出来,以便为沟槽电容器上方的外延生长提供充足的晶种区。这使得不同种类的器件,包括横向的和纵向的晶体管、二极管、电阻等等都可以做在单晶中,并直接叠放在沟槽电容器的顶部。
Claims (26)
1、一种将单晶晶体管放在沟槽电容器结构之上的动态存贮单元的制造方法,它包括如下步骤:
第1步 在单晶硅衬底上形成掩蔽层;
第2步 在所说的掩蔽层上开窗口,并且在该窗口之下的所说的衬底上腐蚀沟槽;
第3步 在所述沟槽表面上形成一层绝缘层,并用多晶硅材料填充所说的沟槽,并对该多晶硅材料掺杂;
第4步 在填入沟槽的所说的多晶硅上形成一层氧化层;
其特征在于还包括以下步骤:
第5步 从所说的衬底上除去所说的掩蔽层;
第6步 在所说的衬底和覆盖沟槽区的氧化层上生长一层掺杂外延单晶硅;
第7步 在所说的外延硅层上形成一掩蔽层;
第8步 在所说的沟槽区上的所说的掩蔽层中开一窗口,并腐蚀掉所说的外延层硅和该沟槽上的氧化物;
第9步 用多晶硅材料回填在第8步中形成的该窗口;
第10步 除去在第7步中形成的所说的掩蔽层;
第11步 采用常规的栅氧化生长和栅确定方法以及源/漏掺杂剂(离子)注入方法,在所说的沟槽上形成一个存取数晶体管器件,所述注入方法包括对步骤9回填的所述多晶硅材料进行重掺杂,以提供从所述存取数晶体管的源到所述沟槽中所述多晶硅材料的连接。
2、根据权利要求1的一种方法,其附加特征是:为了提供一层单晶外延层,由第6步所生长的所说的外延层是从来自所说的单晶硅衬底的单晶籽晶生长成的,而且由第11步所形成的存取数晶体管器件由所说的单晶材料组成。
3、根据权利要求2的一种方法,其附加特征是:所说的单晶硅衬底为P+型重掺悉硅片。
4、根据权利要求2的一种方法,其附加特征是:所说的单晶衬底还包括配置在该P+重掺杂硅片顶部的P-外延层。
5、根据权利要求2的一种方法,其附加特征为:由第1步形成的掩模层是氧化硅和氮化硅的复合层。
6、一种具有沟槽电容器结构的动态存贮器器件,包括:
一个单晶硅衬底;
安排在该衬底中的一个沟槽电容器,该电容包括由绝缘材料壁包围的掺杂多晶硅材料区;
一层在所述沟槽之上的氧化层,其特征在于:
安排在该衬底和覆盖沟槽区的氧化物上的一层单晶外延硅;
安排在所说的沟槽电容器之上的一个存取数晶体管器件,该存取数晶体管器件具有由所说的单晶外延硅层材料形成的源/漏区,以及
在所说的沟槽电容器之上的所说的单晶外延硅层中的窗口中安置的一个多晶硅区域,此区将所说的存取数晶体管的源区连接到所说的沟槽电容器的掺杂多晶硅材料上。
7、根据权利要求6的一种动态存贮器器件,其中:
所说的衬底包括P+重掺杂硅片和安置在该P+掺杂硅片的P-外延硅层。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US789,675 | 1985-10-21 | ||
US06/789,675 US4649625A (en) | 1985-10-21 | 1985-10-21 | Dynamic memory device having a single-crystal transistor on a trench capacitor structure and a fabrication method therefor |
Publications (2)
Publication Number | Publication Date |
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CN86105868A CN86105868A (zh) | 1987-06-10 |
CN1005883B true CN1005883B (zh) | 1989-11-22 |
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CN86105868.2A Expired CN1005883B (zh) | 1985-10-21 | 1986-09-09 | 动态存贮器器件及其制造方法 |
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Country | Link |
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US (1) | US4649625A (zh) |
EP (1) | EP0220410B1 (zh) |
JP (1) | JPH06101546B2 (zh) |
KR (1) | KR900002885B1 (zh) |
CN (1) | CN1005883B (zh) |
AU (1) | AU575499B2 (zh) |
BR (1) | BR8604546A (zh) |
CA (1) | CA1232362A (zh) |
DE (1) | DE3688231T2 (zh) |
ES (1) | ES2003376A6 (zh) |
HK (1) | HK90993A (zh) |
IN (1) | IN167820B (zh) |
ZA (1) | ZA866625B (zh) |
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- 1986-08-22 EP EP86111645A patent/EP0220410B1/en not_active Expired - Lifetime
- 1986-08-22 DE DE86111645T patent/DE3688231T2/de not_active Expired - Fee Related
- 1986-08-30 KR KR1019860007237A patent/KR900002885B1/ko not_active IP Right Cessation
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KR870004513A (ko) | 1987-05-11 |
BR8604546A (pt) | 1987-05-26 |
IN167820B (zh) | 1990-12-22 |
EP0220410B1 (en) | 1993-04-07 |
CA1232362A (en) | 1988-02-02 |
CN86105868A (zh) | 1987-06-10 |
JPS6298766A (ja) | 1987-05-08 |
DE3688231T2 (de) | 1993-11-04 |
EP0220410A3 (en) | 1989-05-10 |
ES2003376A6 (es) | 1988-11-01 |
DE3688231D1 (de) | 1993-05-13 |
AU575499B2 (en) | 1988-07-28 |
JPH06101546B2 (ja) | 1994-12-12 |
US4649625A (en) | 1987-03-17 |
EP0220410A2 (en) | 1987-05-06 |
HK90993A (en) | 1993-09-10 |
ZA866625B (en) | 1987-06-24 |
AU6307186A (en) | 1987-04-30 |
KR900002885B1 (ko) | 1990-05-01 |
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