EP2028687B1 - Herstellungsverfahren für Dünnschichttransistor und organische lichtemittierende Diodenanzeigevorrichtung damit - Google Patents

Herstellungsverfahren für Dünnschichttransistor und organische lichtemittierende Diodenanzeigevorrichtung damit Download PDF

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EP2028687B1
EP2028687B1 EP08162758.0A EP08162758A EP2028687B1 EP 2028687 B1 EP2028687 B1 EP 2028687B1 EP 08162758 A EP08162758 A EP 08162758A EP 2028687 B1 EP2028687 B1 EP 2028687B1
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layer
metal
semiconductor layer
metal catalyst
forming
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EP2028687A1 (de
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Byoung-Keon Park
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Samsung Display Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1277—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using a crystallisation promoting species, e.g. local introduction of Ni catalyst
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements

Definitions

  • aspects of the present invention relates to a thin film transistor (TFT), a method of fabricating the same, and an organic light emitting diode (OLED) display device having the same. More particularly, aspects of the present invention relate to a TFT having good electrical characteristics in which metal catalysts remaining in a channel region of a semiconductor layer crystallized using the metal catalysts are gettered to reduce the amount of the metal catalysts remaining in the semiconductor layer, a method of fabricating the same, and an OLED display device having the same. Methods for manufacturing a semiconductor device or a thin film transistor, respectively, are described in US 2004/0164300 A1 and US 2003/0030108 A1 .
  • a polycrystalline silicon layer can be advantageously applied to high field-effect mobility and high-speed operation circuits and adapted for complementary metal oxide semiconductor (CMOS) circuits.
  • CMOS complementary metal oxide semiconductor
  • Polycrystalline silicon layers are widely used as semiconductor layers for TFTs. TFTs using a polycrystalline silicon layer are typically used as an active element of an active matrix liquid crystal display (AMLCD) and a switching element and a driving element of an OLED.
  • AMLCD active matrix liquid crystal display
  • OLED driving element of an OLED
  • Methods of crystallizing amorphous silicon into polycrystalline silicon include a solid phase crystallization method, an excimer laser crystallization method, a metal induced crystallization method, and a metal induced lateral crystallization method.
  • a solid phase crystallization method an amorphous silicon layer is annealed for several hours to tens of hours at a temperature of about 700°C or less, which is the deformation temperature of glass that is used as the substrate of the display device in which the TFT is used.
  • the excimer laser crystallization method local heating is carried out by irradiating an excimer laser onto an amorphous silicon layer for a very short time for crystallization.
  • metal induced crystallization method a phenomenon that the phase change from an amorphous silicon layer into a polycrystalline silicon layer is induced by metal such as nickel, palladium, aurum or aluminum by contacting the metal with the amorphous silicon layer or implanting the metal into the amorphous silicon layer is used.
  • metal induced lateral crystallization method sequential crystallization of an amorphous silicon layer is induced while silicide generated by the reaction between metal and silicon continues to propagate laterally.
  • the solid phase crystallization method requires not only a long process time but a long annealing time at a high temperature so that the substrate is disadvantageously apt to be deformed.
  • the excimer laser crystallization method requires a costly laser apparatus and causes protrusions on the polycrystallized surface, providing an inferior interface property between a semiconductor layer and a gate insulating layer.
  • the metal induced crystallization method or the metal induced lateral crystallization method causes a large amount of metal catalysts to remain in the polycrystallized silicon layer so that the leakage current of the semiconductor layer of the TFT increases.
  • Crystallization method using metal include a metal induced crystallization (MIC) method, a metal induced lateral crystallization (MILC) method, and a super grain silicon (SGS) crystallization method.
  • MIC metal induced crystallization
  • MILC metal induced lateral crystallization
  • SGS super grain silicon
  • a gettering process is performed after the amorphous silicon layer is crystallized in order to remove the metal catalysts.
  • a general gettering process is performed using impurities such as phosphorous or noble gas or using a method of forming an amorphous silicon layer on a polycrystalline silicon layer.
  • the metal catalysts within the polycrystalline silicon layer may not be sufficiently removed so that the leakage current may remain undesirably high.
  • aspects of the present invention provide a method of fabricating a TFT having good electrical characteristics by gettering metal catalysts remaining in a channel region of a semiconductor layer crystallized using the metal catalysts to reduce the amount of the metal catalysts remaining in the semiconductor layer and a method of fabricating an OLED display device having the same.
  • a method of fabricating a TFT includes: preparing a substrate; forming an amorphous silicon layer on the substrate; crystallizing the amorphous silicon layer into a polycrystalline silicon layer using a metal catalyst; patterning the polycrystalline silicon layer to form a semiconductor layer; forming a gate insulating layer on the semiconductor layer; forming a gate electrode on the gate insulating layer, forming an interlayer insulating layer over the entire surface of the substrate including the gate electrode; etching the gate insulating layer and the interlayer insulating layer to form contact holes exposing source and drain regions of the semiconductor layer; forming a metal layer, a metal silicide layer, or a double layer thereof on the interlayer insulating layer in which the contact holes are formed; and annealing the substrate such to form a metal silicide comprising a metal that is different from the metal catalyst within a region of the semiconductor layer under the contact hole the surface of the semiconductor layer to a predetermined depth thereby getter the metal catalysts
  • the method further comprises forming a thermal oxidation barrier on the metal containing layer before annealing the substrate and , after gettering the metal catalyst , removing the metal containing layer and forming source and drain electrodes in contact with the source and drain regions of the semiconductor layer on the interlayer insulating layer.
  • the layer “formed of metal layer, a metal silicide layer, or a double layer thereof” is formed of metal layer and/or a metal silicide layer.
  • the metal silicide layer may be stacked on the metal layer but alternatively the metal layer may be stacked on the metal silicide layer.
  • Said layer (“formed of metal layer, a metal silicide layer, or a double layer thereof") is preferably formed on the interlayer insulating layer in a region where the contact holes are located, thereby completely covering semiconductor layer region which are exposed by the contact holes and (at least partially) covering the interlayer insulating layer.
  • the metal layer, the metal silicide layer, or the double layer thereof comprises a metal layer having a metal or alloy thereof with a smaller diffusion coefficient than the metal catalyst, or a metal silicide layer including a silicide metal or alloy thereof with a smaller diffusion coefficient than the metal catalyst within the semiconductor layer.
  • the diffusion coefficient of the metal layer, the metal silicide layer, or the double layer thereof is not greater than 1/100 of the diffusion coefficient of the metal catalyst.
  • the metal catalyst is nickel, and the diffusion coefficient of the metal layer, the metal silicide layer, or the double layer thereof is greater than 0 and is not greater than 10 -7 cm 2 /s.
  • the metal layer, the metal silicide layer, or the double layer thereof comprises one selected from the group consisting of Sc, Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, W, Mn, Re, Ru, Os, Co, Rh, Ir, Pt, Y, Ta, La, Ce, Pr, Nd, Dy, Ho, TiN, TaN, and an alloy thereof.
  • the annealing is performed for 10 seconds to 10 hours at a temperature of 500 to 993°C.
  • the crystallizing of the amorphous silicon layer is performed using a super grain silicon (SGS) crystallization method.
  • the method further comprises: forming a thermal oxidation barrier on the metal layer, the metal silicide layer, or the double layer thereof before annealing the substrate.
  • the method further comprises: implanting n-type or p-type impurities into the regions of the semiconductor layer in contact with the metal layer, the metal silicide layer or the double layer thereof, or forming a damage region using ions or plasma.
  • the method further comprises: after forming the metal layer, the metal silicide layer or the double layer thereof and before annealing the substrate, patterning the metal layer, the metal silicide layer or the double layer thereof to form source and drain electrodes.
  • FIGS. 1A to 1D are cross-sectional views illustrating a crystallization process according to an embodiment of the present invention.
  • a buffer layer 110 is first formed on a substrate 100 such as glass or plastic, as shown in FIG. 1A .
  • the buffer layer 110 is formed of a single layer or a multiple layer of an insulating material such as a silicon oxide layer or a silicon nitride layer using a chemical vapor deposition (CVD) method or a physical vapor deposition (PVD) method.
  • the buffer layer 110 acts to prevent diffusion of moisture or impurities generated from the substrate 100 and/or acts to facilitate crystallization of an amorphous silicon layer by adjusting the heat transfer rate at the time of crystallization.
  • the amorphous silicon layer 120 is then formed on the buffer layer 110.
  • the amorphous silicon layer 120 may be formed by a CVD method or a PVD method.
  • a dehydrogenation process to the hydrogen concentration may be performed at the same time as or after the amorphous silicon layer 120 is formed.
  • the amorphous silicon layer 120 is then crystallized into a polycrystalline silicon layer.
  • a crystallization method using a metal catalyst such as MIC, MILC, or SGS is employed to crystallize the amorphous silicon layer into the polycrystalline silicon layer.
  • the MIC method uses a phenomenon that the phase change from an amorphous silicon layer into a polycrystalline silicon layer is induced by metal such as nickel (Ni), palladium (Pd), or aluminum (Al) by contacting the metal with the amorphous silicon layer or implanting the metal into the amorphous silicon layer.
  • metal such as nickel (Ni), palladium (Pd), or aluminum (Al)
  • an amorphous silicon layer is crystallized into a polycrystalline silicon layer by inducing sequential crystallization of the amorphous silicon layer while a silicide generated by the reaction between a metal catalyst and silicon continues to propagate laterally.
  • the size of the crystal grain is adjusted to be in a range of several ⁇ m to several hundreds of ⁇ m by adjusting the concentration of the metal catalyst diffusing into an amorphous silicon layer to be in a low concentration.
  • a capping layer may be formed on the amorphous silicon layer, a metal catalyst layer may be formed on the capping layer and then annealed to diffuse the metal catalysts.
  • the capping layer controls the diffusion rate of the metal catalyst.
  • the concentration of the metal catalyst can be controlled by forming the metal catalyst layer at a low concentration without forming the capping layer.
  • the SGS method may be used to control the concentration of the metal catalyst diffusing into the amorphous silicon layer at a low concentration by forming the capping layer, which will be described below.
  • FIG. 1B is a cross-sectional view illustrating a process of forming a capping layer and a metal catalyst layer on the amorphous silicon layer.
  • a capping layer 130 is formed on the amorphous silicon layer 120.
  • the capping layer 130 may be formed of silicon nitride, which enables the metal catalyst formed subsequently process to be diffused during annealing.
  • the capping layer 130 may be formed as a double layer of silicon nitride and silicon oxide.
  • the capping layer 130 may be formed by a method such as CVD or PVD to have a thickness of 1 to 2000 ⁇ . When the thickness of the capping layer 130 is smaller than 1 ⁇ , it is difficult for the capping layer 130 to suppress the amount of the metal catalyst to be diffused.
  • the thickness of the capping layer 130 is greater than 2000 ⁇ , the amount of the metal catalyst to be diffused into the amorphous silicon layer 120 is so small that the amorphous silicon layer 120 cannot be crystallized into a polycrystalline silicon layer.
  • the metal catalyst is then deposited on the capping layer 130 to form a metal catalyst layer 140.
  • any one selected from the group consisting of Ni, Pd, Ag, Au, Al, Sn, Sb, Cu, Tr, and Cd may be used as the metal catalyst.
  • the metal catalyst may be Ni.
  • the metal catalyst layer 140 is formed on the capping layer 130 at a surface density of 10 11 to 10 15 atoms/cm 2 . When the metal catalyst has a surface density less than 10 11 atoms/cm 2 , the number of seeds, i.e., crystallization nuclei, is small so that the amorphous silicon layer cannot be crystallized into the polycrystalline silicon layer by the SGS method.
  • the metal catalyst has a surface density greater than 10 15 atoms/cm 2 , the amount of the metal catalyst that diffuses into the amorphous silicon layer is large so that the crystal grain of the polycrystalline silicon layer becomes smaller and the remaining amount of the metal catalysts increases enough to cause characteristics of the semiconductor layer formed by patterning the polycrystalline silicon layer to deteriorate.
  • FIG. 1C is a cross-sectional view illustrating a process of annealing the substrate to diffuse the metal catalyst toward an interface of the amorphous silicon layer through the capping layer.
  • the substrate 100 in which the buffer layer 110, the amorphous silicon layer 120, the capping layer 130, and the metal catalyst layer 140 are formed is annealed (process 150) to move some of the metal catalyst of the metal catalyst layer 140 toward the surface of the amorphous silicon layer 120. That is, only a small amount of the metal catalyst 140b among the metal catalysts 140a and 140b that pass through the capping layer 130 diffused by the annealing process 150 is diffused into the surface of the amorphous silicon layer 120, and most of the metal catalyst 140a does not reach the amorphous silicon layer 120 or does not pass through the capping layer 130.
  • the amount of the metal catalyst reaching the surface of the amorphous silicon layer 120 is determined by the diffusion suppression capability of the capping layer 130, and the diffusion suppression capability of the capping layer 130 has a close relation to the thickness of the capping layer 130. That is, the thicker the capping layer 130 is, the less the diffusion amount is so that the size of the crystal grain increases, and the thinner the capping layer is, the more the diffusion amount is so that the size of the crystal grain decreases.
  • the annealing process 150 is performed for several seconds to several hours at a temperature of 200 to 900°C to diffuse the metal catalyst.
  • the annealing time is limited in time and temperature so that deformation of the substrate from excessive annealing does not occur, and so that the annealing process is favorable in terms of manufacturing cost and yield.
  • the annealing process 150 may be carried out by one of a furnace process, a rapid thermal annealing process, a UV process, and a laser process.
  • FIG. 1D is a cross-sectional view illustrating a process of crystallizing the amorphous silicon layer into the polycrystalline silicon layer using the diffused metal catalyst.
  • the amorphous silicon layer 120 is crystallized into a polycrystalline silicon layer 160 by the metal catalyst 140b that passes through the capping layer 130 and diffuses onto the surface of the amorphous silicon layer 120. That is, the diffused metal catalyst 140b combines with silicon of the amorphous silicon layer to form a metal silicide, and the metal silicide forms seeds, i.e., crystallization nuclei, so that during an additional annealing process, the amorphous silicon layer is crystallized into the polycrystalline silicon layer.
  • the annealing process to crystallize the amorphous silicon layer may be performed without removing the capping layer 130 and the metal catalyst layer 140 as shown in FIG. 1D .
  • the capping layer 130 and the metal catalyst layer 140 may be removed and the annealing process may be performed to form the polycrystalline silicon layer after the metal catalyst has diffused onto the amorphous silicon layer 120 to form the metal silicide, i.e., crystallization nuclei.
  • FIGS. 2A to 2E are cross-sectional views illustrating a process of fabricating a TFT according to an embodiment of the present invention.
  • a semiconductor layer 210 is formed on the substrate 100 on which the buffer layer 110 is formed by crystallizing an amorphous silicon layer into a polycrystalline silicon layer using a metal catalyst as described in the embodiment of FIGS. 1A to 1D .
  • the semiconductor layer 210 is formed by removing the capping layer (130 of FIG. 1D ) and the metal catalyst layer (140 of FIG. 1D ) and patterning the polycrystalline silicon layer (160 of FIG. 1D ). Alternatively, the patterning of the polycrystalline silicon layer may be performed in a subsequent process.
  • a gate insulating layer 220 is formed on the substrate 100 and on the semiconductor layer 210.
  • the gate insulating layer 220 may be a silicon oxide layer, a silicon nitride layer or a double layer thereof.
  • a photoresist pattern 230 is formed in a region corresponding to a channel region of the semiconductor layer 210 on the gate insulating layer 220.
  • a predetermined amount of conductive impurity ions 240 is implanted using the photoresist pattern 230 as a mask to form a source region 211, a drain region 213, and a channel region 212.
  • P-type or n-type impurities may be used as the impurity ions 240 to form the TFT, wherein the p-type impurities may be selected from the group consisting of B, Al, Ga and In, and the n-type impurities may be selected from the group consisting of P, As and Sb.
  • the photoresist pattern 230 is removed, a single layer of Al or an Al alloy such as Al-Nd, or a multiple layer of an Al alloy stacked on a Cr or Mo alloy is formed as a metal layer (not shown) for a gate electrode on the gate insulating layer 220, and the metal layer is etched by a photolithography process to form a gate electrode 250 in a region corresponding to the channel region 212 of the semiconductor layer 210.
  • interlayer insulating layer 260 is then formed over the entire surface of the substrate 100 including the gate electrode 250.
  • the interlayer insulating layer 260 may be a silicon nitride layer, a silicon oxide layer or a multiple layer thereof.
  • the interlayer insulating layer 260 and the gate insulating layer 220 are then etched to form contact holes 270 exposing source and drain regions 211 and 213 of the semiconductor layer 210.
  • a metal layer, a metal silicide layer, or a double layer thereof 280 is formed on the interlayer insulating layer 260 in which the contact holes 270 are formed.
  • a gettering process is performed using a region within the semiconductor layer 210 to be formed by a subsequent annealing process.
  • the metal layer, the metal silicide layer, or the double layer thereof 280 may include a metal layer having a metal or alloy thereof with a diffusion coefficient smaller than the diffusion coefficient of the metal catalyst that is used for crystallization, or a metal silicide layer thereof within the semiconductor layer 210.
  • the diffusion coefficient of the metal or metal silicide of the metal layer, the metal silicide layer, or the double layer thereof 280 within the semiconductor layer 210 is preferably not greater than 1/100 of the diffusion coefficient of the metal catalyst for crystallization.
  • the metal or metal silicide for gettering can be prevented from migrating out of a region 210a in contact with the metal layer, the metal silicide layer, or the double layer thereof 280 within the semiconductor 210 to diffuse into other regions within the semiconductor layer 210 and into other regions within the semiconductor layer 210.
  • Nickel is widely employed as the metal catalyst for crystallization of the semiconductor layer. Nickel has a diffusion coefficient not greater than about 10 -5 cm 2 /s within the semiconductor layer. Therefore, the diffusion coefficient of the metal or metal silicide of the metal layer, the metal silicide layer, or the double layer thereof 280 should not be greater than 1/100 of the diffusion coefficient of nickel, i.e., greater than 0 and not greater than 10 -7 cm 2 /s when the nickel is used as the metal catalyst.
  • the metal or metal silicide may include one selected from the group consisting of Sc, Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, W, Mn, Re, Ru, Os, Co, Rh, Ir, Pt, Y, Ta, La, Ce, Pr, Nd, Dy, Ho, TiN, TaN, and an alloy thereof.
  • the metal layer, the metal silicide layer, or the double layer thereof 280 may have a thickness of 30 to 2000 ⁇ .
  • the gettering efficiency of the metal catalyst for crystallization into a region 210a within the semiconductor layer 210 in contact with the metal layer, the metal silicide layer, or the double layer thereof 280 may be decreased.
  • the thickness the metal layer, the metal silicide layer, or the double layer thereof 280 exceeds 2000 ⁇ , the substrate 100 may be deformed because of thermal expansion of the metal layer, the metal silicide layer, or the double layer thereof 280 formed over the entire surface at the time of subsequent annealing for gettering.
  • a thermal oxidation barrier 290 is formed on the metal layer, the metal silicide layer, or the double layer thereof 280.
  • the thermal oxidation barrier 290 acts to prevent surface denaturation caused by oxidation of the metal layer, the metal silicide layer or the double layer thereof 280 or reaction between the metal layer, the metal silicide layer or the double layer thereof 280 and a gas such as nitrogen depending on the annealing condition at the time of subsequent annealing for gettering, and may be formed of a silicon oxide layer or a silicon nitride layer.
  • the forming of the thermal oxidation barrier 290 may be omitted when a subsequent annealing process is performed in an inactive atmosphere.
  • An annealing process is then performed to remove the metal catalyst which was used for crystallization and which is still remaining in the semiconductor layer 210, particularly, the metal catalyst remaining in the channel region 212 of the semiconductor layer 210.
  • the metal of the metal layer 280 combines with silicon of the semiconductor layer 210 from the surface of the semiconductor layer 210 in contact with the metal layer 280 (or the double layer of a metal layer and a metal silicide layer,) to form a metal silicide, or the metal silicide of the metal silicide layer (or the double layer of a metal layer and a metal silicide layer) is diffused into the region of the semiconductor layer 210.
  • the region 210a in which a metal silicide different from the metal silicide formed from the metal catalyst for crystallization is present is formed in the region of the semiconductor layer 210 in contact with the metal layer, the metal silicide layer, or the double layer thereof 280.
  • the region 210a of the semiconductor layer containing the metal silicide extends from the surface of the semiconductor layer 210 in contact with the metal layer, the metal silicide layer, or the double layer thereof 280 to a predetermined depth. A portion of the metal in the metal layer, the metal silicide layer, or the double layer thereof 280 in contact with the semiconductor layer 210 may also be converted into the metal silicide layer.
  • the metal catalyst for crystallization remaining in the channel region 212 of the semiconductor layer 210 diffuses into the region 210a within the semiconductor layer 210 in contact with the metal layer, the metal silicide layer, or the double layer thereof 280 by the annealing process, the metal catalyst precipitates in the region 210a so that it does not diffuse any more. This is because the metal catalyst for crystallization is thermodynamically more stable in the region 210a in which other metal silicides are present than in the silicon of the semiconductor layer 210. Therefore, according to this principle, the metal catalyst for crystallization remaining in the channel region 212 of the semiconductor layer 210 can be removed.
  • the annealing may be performed at a temperature of 500 to 993°C for 10 seconds to 10 hours.
  • the temperature is less than 500°C, the metal catalyst for crystallization may not diffuse i into the region 210a within the semiconductor layer 210.
  • the temperature exceeds 993°C, nickel as the metal catalyst may be present in a solid state because the eutectic point of nickel is 993°C, and the substrate may be deformed because of the high temperature.
  • the metal catalyst remaining in the channel region 212 of the semiconductor layer 210 may not be sufficiently removed, and when the annealing time exceeds 10 hours, the substrate may be deformed because of the long time annealing and the manufacturing cost and yield of the TFT may be affected. Meanwhile, when the annealing is performed at a higher temperature, the metal catalysts can be removed even in a short time.
  • n-type or p-type impurities may also be implanted into the region 210a of the semiconductor layer 210 in contact with the metal layer, the metal silicide layer, or the double layer thereof 280.
  • the n-type impurities may be phosphorus (P) and the p-type impurities may be boron (B).
  • ions or plasma may be used to form a damage region 210b within the region 210a of the semiconductor layer 210 in contact with the metal layer, the metal silicide layer, or the double layer thereof 280.
  • Source and drain electrodes 291 and 293 are then formed to be connected to the source and drain regions 211 and 213, respectively, through the contact holes 270.
  • the source and drain electrodes 291 and 293 may be formed of one selected from the group consisting of Mo, Cr, W, MoW, Al, Al-Nd, Ti, TiN, Cu, a Mo alloy, an Al alloy and a Cu alloy. Therefore, the TFT according to an embodiment of the present invention is completed.
  • FIGS. 3A to 3C are cross-sectional views illustrating a process of fabricating a TFT according to an example not forming part of the present invention. This example is formed in the same manner as the embodiment shown in FIGS. 1A to 1D and 2A to 2E except for differences described below.
  • a substrate 300 on which a buffer layer 310 is formed is first prepared.
  • An amorphous silicon layer is then formed on the buffer layer 310, which is crystallized into a polycrystalline silicon layer using a metal catalyst as described in the embodiment of FIGS. 1A to 1D .
  • the polycrystalline silicon layer is patterned to form a semiconductor layer 320. Alternatively, the patterning of the polycrystalline silicon layer may be performed in a subsequent process.
  • a gate insulating layer 330 is then formed on the substrate 300 and on the semiconductor layer 320.
  • a photoresist pattern 340 is formed in a region corresponding to a channel region of the semiconductor layer 320 on the gate insulating layer 330.
  • a predetermined amount of conductive impurity ions 345 is implanted using the photoresist pattern 340 as a mask to form a source region 321, a drain region 323, and a channel region 322.
  • the photoresist pattern 340 is removed, a metal layer (not shown) for a gate electrode is formed on the gate insulating layer 330, and the metal layer for a gate electrode is etched by a photolithography process to form a gate electrode 350 in a region corresponding to the channel region 322 of the semiconductor layer 320.
  • An interlayer insulating layer 360 is then formed over the entire surface of the substrate 300 including the gate electrode 350.
  • the interlayer insulating layer 360 and the gate insulating layer 330 are then etched to form contact holes 370 exposing the source and drain regions 321 and 323 of the semiconductor layer 320.
  • a metal layer, a metal silicide layer, or a double layer thereof 380 is then formed on the interlayer insulating layer 360 in which the contact holes 370 are formed.
  • a gettering process is performed using the region within the semiconductor layer 320 to be formed by a subsequent annealing process after the metal layer, the metal silicide layer, or the double layer thereof 380 is deposited.
  • a thermal oxidation barrier 385 may be formed on the metal layer, the metal silicide layer, or the double layer thereof 380.
  • An annealing process is then performed to remove the metal catalyst for crystallization remaining in the semiconductor layer 320, particularly, remaining in the channel region 322 of the semiconductor layer 320.
  • the metal of the metal layer combines with silicon of the semiconductor layer 320 from the surface of the semiconductor layer 320 in contact with the metal layer, the metal silicide layer, or the double layer thereof 380 to form a metal silicide, and/or a metal silicide of the metal silicide layer is diffused into the region of the semiconductor layer 320.
  • a region 320a in which a metal silicide different from the metal silicide formed from the metal catalyst for crystallization is present, is formed in the region of the semiconductor layer 320 in contact with the metal layer, the metal silicide layer, or the double layer thereof 380.
  • the region 320a of the semiconductor layer 320 containing the metal silicide may extend from the surface of the semiconductor layer 320 in contact with the metal layer, the metal silicide layer, or the double layer thereof 380 to a predetermined depth.
  • the metal catalysts for crystallization remaining in the channel region 322 of the semiconductor layer 320 diffuses into the region 320a within the semiconductor layer 320 in contact with the metal layer, the metal silicide layer, or the double layer thereof 380 by the annealing process, the metal catalyst precipitates in the region 320a so that it does not diffuse any more.
  • n-type or p-type impurities may also be implanted into the region 320a of the semiconductor layer 320 in contact with the metal layer, the metal silicide layer, or the double layer thereof 380, and ions or plasma may be used to form a damage region 320b in order to increase the gettering effect more.
  • the thermal oxidation barrier 385 is removed.
  • a material for source and drain electrodes is then deposited on the metal layer, the metal silicide layer, or the double layer thereof 380.
  • the metal layer, the metal silicide layer, or the double layer thereof 380, and the material for source and drain electrodes are patterned to form a patterned metal layer, metal silicide layer, or a double layer thereof 390, and source and drain electrodes 391 and 393.
  • the metal layer, the metal silicide layer, or the double layer thereof 380 is not removed but instead is patterned to form the patterned metal layer, metal silicide layer or the double layer thereof 390.
  • the source and drain electrodes 391 and 393 are electrically connected to the source and drain regions 321 and 323, respectively, of the semiconductor layer 320 through the patterned metal layer, the metal silicide layer, or the double layer thereof 390 in the second embodiment of the present invention. Therefore, the TFT according to the example of FIGS. 3A to 3C is completed.
  • FIGS. 4A to 4C are cross-sectional views illustrating a process of fabricating a TFT according to another example not forming part of the present invention. This example is formed in the same manner as the above-described embodiments except for differences described below.
  • a substrate 400 in which a buffer layer 410 is formed is first prepared.
  • An amorphous silicon layer is then formed on the buffer layer 410 and is crystallized into a polycrystalline silicon layer using a metal catalyst as described in the embodiment of FIGS. 1A to 1D .
  • the polycrystalline silicon layer is patterned to form a semiconductor layer 420. Alternatively, the patterning of the the polycrystalline silicon layer may be performed in a subsequent process.
  • a gate insulating layer 430 is then formed on the substrate 400 and on the semiconductor layer 420.
  • a photoresist pattern (not shown) is formed in a region corresponding to a channel region of the semiconductor layer 420 on the gate insulating layer 430, and a predetermined amount of conductive impurity ions is implanted using the photoresist pattern as a mask to form a source region 421, a drain region 423, and a channel region 422.
  • a metal layer (not shown) for a gate electrode is formed on the gate insulating layer 430, and the metal layer for a gate electrode is etched by a photolithography process to form a gate electrode 450 in a region corresponding to the channel region 422 of the semiconductor layer 420.
  • an interlayer insulating layer 460 is formed over the entire surface of the substrate 400 including the gate electrode 450.
  • the interlayer insulating layer 460 and the gate insulating layer 430 are then etched to form contact holes 470 exposing the source and drain regions 421 and 423 of the semiconductor layer 420.
  • a metal layer, a metal silicide layer, or a double layer thereof is then formed on the interlayer insulating layer 460 in which the contact holes 470 are formed, and is patterned to form a patterned metal layer, metal silicide layer, or a double layer thereof 480.
  • the metal layer, the metal silicide layer, or the double layer thereof has a thickness of 30 to 10000 ⁇ , more preferably a thickness of 2000 to 10000 ⁇ and still more preferably a thickness of 5000 to 10000 ⁇ , unlike the metal layer, the metal silicide layer, or the double layer thereof 380 of the embodiment of FIGS. 3A to 3C .
  • the metal layer, the metal silicide layer, or the double layer thereof in the present embodiment is first patterned and then annealing is performed for gettering so that the metal layer, the metal silicide layer, or the double layer thereof is not present over the entire surface of the substrate 400 at the time of annealing. Accordingly, deformation of the substrate 400 at the time of annealing, which can be caused by the thermal expansion of the metal layer, the metal silicide layer, or the double layer thereof formed over the entire surface can be avoided, so that the patterned metal layer, metal silicide layer, or double layer thereof 480 can be formed up to a thickness of 10000 ⁇ .
  • a thermal oxidation barrier 490 may be formed on the patterned metal layer, the metal silicide layer, or the double layer thereof 480.
  • An annealing process is then performed to remove the metal catalyst for crystallization remaining in the semiconductor layer 420, particularly, the metal catalyst remaining in the channel region 422 of the semiconductor layer 420.
  • a metal of the metal layer combines with silicon of the semiconductor layer 420 at the surface of the semiconductor layer 420 in contact with the metal layer pattern, the metal silicide layer pattern, or the double layer pattern thereof 480 to form a metal silicide, and/or the metal silicide of the metal silicide layer pattern is diffused into the region of the semiconductor layer 420 in contact with the patterned metal layer, metal silicide layer, or double layer thereof 480.
  • a region 420a in which a metal silicide different from the metal silicide formed from the metal catalyst for crystallization is present, is formed in the region of the semiconductor layer 420 in contact with the patterned metal layer, metal silicide layer, or the double layer thereof 480.
  • the region 420a of the semiconductor layer 420 containing the metal silicide may extend from the surface of the semiconductor layer 420 in contact with the patterned metal layer, metal silicide layer, or double layer thereof 480 to a predetermined depth.
  • the metal catalyst for crystallization remaining in the channel region 422 of the semiconductor layer 420 diffuses into the region 420a within the semiconductor layer 420 in contact with the patterned metal layer, metal silicide layer, or double layer thereof 480 by the annealing process, the metal catalyst precipitates in the region 420a so that it does not diffuse any more.
  • n-type or p-type impurities may also be implanted into the region 420a of the semiconductor layer 420 in contact with the patterned metal layer, metal silicide layer, or the double layer thereof 480, and ions or plasma may be used to form a damage region 420b in order to increase the gettering effect.
  • the thermal oxidation barrier 490 is removed. Therefore, the TFT according to the embodiment of FIGS. 4A to 4C is completed, wherein the patterned metal layer, metal silicide layer, or double layer thereof 480 becomes source and drain electrodes.
  • the patterned metal layer, metal silicide layer, or double layer thereof 480 becomes the source and drain electrodes as in the embodiment of FIGS. 4A to 4C , a separate material for source and drain electrodes does not need to be formed, so that the process can be more simplified.
  • FIG. 5 is a graph in which the off-current per unit width of the semiconductor layer of a TFT formed by a conventional gettering method using phosphorous (P) doping is compared with the off-current per unit width of the semiconductor layer of TFTs according to embodiments of the present invention.
  • Region A in the horizontal axis indicates the TFT formed by the conventional gettering method using P doping
  • regions B and C indicate TFTs formed according to embodiments of the present invention, wherein region B indicates a TFT formed using Ti and region C indicates a TFT formed using Mo.
  • the vertical axis indicates the measured off-current (A/ ⁇ m) per unit width of the semiconductor layer of the TFT.
  • TFT formed by the conventional gettering method using P doping P was doped at a dose of 2*e 14 /cm 2 into the region exposed by the contact hole in the semiconductor layer crystallized using Ni as the metal catalyst for crystallization, and then annealing was performed for one hour at 550°C.
  • a 100 ⁇ thick layer of Ti or Mo was deposited on the regions exposed by the contact holes in the respective semiconductor layers crystallized using Ni as the metal catalyst, and the annealing was performed in the same gettering conditions as the gettering conditions using P doping. The off-current of each TFT was measured after the annealing was performed.
  • Ti or Mo reacts with Si of the semiconductor layer to form Ti silicide or Mo silicide.
  • a region in which the Ti or Mo silicide is formed extends from the interface of the semiconductor layer and the Ti or Mo layer to a depth within the semiconductor layer, and the metal catalyst (for example, Ni in the particular examples described above) is gettered into the region in which the Ti or Mo silicide is formed.
  • the off-current per unit width of the semiconductor layer of the TFT formed by the conventional gettering method using P doping was measured four times. As a result, values in the range of about 4.5E -12 to 7.0E -12 A/ ⁇ m were measured. In contrast, referring to regions B and C of FIG.
  • the off-currents per unit width of the semiconductor layer of the TFT according to the embodiments of the present invention were 5.0E -13 A/ ⁇ m or less in the case of the TFT formed using Ti and 6.0E -13 A/ ⁇ m or less in the case of the TFT formed using Mo, demonstrating that the off-current per unit width of the semiconductor layer formed according to aspects of the present invention was significantly reduced over the semiconductor layer formed using the conventional method.
  • FIG. 6 is a cross-sectional view of an OLED display device including a TFT according to another embodiment of the present invention.
  • an insulating layer 610 is formed over the entire surface of the substrate 200 including the TFT of FIG. 2E .
  • the insulating layer 610 may be an inorganic layer selected from the group consisting of i a silicon oxide layer, a silicon nitride layer and spin on glass, or may be an organic layer selected from the group consisting of polyimide, benzocyclobutene series resin and acrylate.
  • the insulating layer 610 may have a stacked structure of the inorganic layers and the organic layers.
  • the insulating layer 610 is etched to form a via hole exposing the source electrode 291 or the drain electrode 293.
  • a first electrode 620 is formed to be connected to one of the source and drain electrodes 291 and 293 through the via hole.
  • the first electrode 620 may be an anode or a cathode.
  • the anode may be formed of a transparent conductive layer formed of one of indium tin oxide (ITO), indium zinc oxide (IZO) and indium tin zinc oxide (ITZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • ITZO indium tin zinc oxide
  • the cathode may be formed of Mg, Ca, Al, Ag, Ba, or an alloy thereof.
  • a pixel-defining layer 630 having an opening that exposes a portion of the surface of the first electrode 620 is formed on the first electrode 620, and an organic layer 640 including an emitting layer is formed on the exposed first electrode 620.
  • the organic layer 640 may further include at least one selected from the group consisting of a hole injection layer, a hole transport layer, a hole blocking layer, an electron blocking layer, an electron injection layer and an electron transport layer.
  • a second electrode 650 is then formed on the organic layer 640. Therefore, the OLED display device according to an embodiment of the present invention is completed.
  • a metal layer including a metal having a diffusion coefficient smaller than the metal catalyst for crystallization or an alloy thereof within the semiconductor layer, a metal silicide layer, or a double layer thereof is formed and annealed in a region of the semiconductor layer exposed by a contact hole, so that the metal catalyst remaining in the channel region of the semiconductor layer can be removed, thereby significantly reducing the off-current of the TFT.
  • the metal layer, the metal silicide layer, or the double layer thereof can be patterned to be used as source and drain electrodes, so that the process of making a TFT can be simplified.
  • metal catalysts remaining in a channel region of a semiconductor layer are removed, so that a TFT having good electrical characteristics with a reduced leakage current or the like, a method of fabricating the same, and an OLED display device having the same can be obtained.

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Claims (8)

  1. Verfahren zur Herstellung eines Dünnschichttransistors (thin film transistor - TFT), umfassend:
    Vorbereiten eines Substrates (100, 300, 400);
    Ausbilden einer amorphen Siliciumschicht (120) auf dem Substrat (100);
    Kristallisieren der amorphen Siliciumschicht (110) zu einer polykristallinen Siliciumschicht (160) unter Verwendung eines Metallkatalysators;
    Strukturieren der polykristallinen Siliciumschicht (160), um eine Halbleiterschicht (210, 320, 420) auszubilden;
    Ausbilden einer Gate-Isolierschicht (220, 330, 430) auf der Halbleiterschicht (210, 320, 420); Ausbilden einer Gate-Elektrode (250, 350, 450) auf der Gate-Isolierschicht (220, 330, 430); Ausbilden einer isolierenden Zwischenschicht (260, 360, 460), welche die Gate-Elektrode (250, 350, 450) abdeckt;
    Ätzen der Gate-Isolierschicht (220, 330, 430) und der isolierenden Zwischenschicht (260, 360, 460), um Kontaktlöcher (270, 370, 470) auszubilden, die Source- und Drainbereiche (211, 213, 321, 323, 421, 423) der Halbleiterschicht (210, 320, 420) freilegen; gekennzeichnet durch
    Ausbilden einer metallhaltigen Schicht (280, 380, 480), die aus einer Metallschicht, einer Metallsilicidschicht oder einer Doppelschicht dieser ausgebildet ist, wobei die metallhaltige Schicht (280, 380, 480) auf der isolierenden Zwischenschicht (260, 360, 460) ausgebildet wird, um einen Bereich abzudecken, in dem die Kontaktlöcher (270, 370, 470) ausgebildet sind; und
    Wärmebehandeln des Substrats (100, 300, 400) zur Ausbildung eines Metallsilicids, das ein von dem Metallkatalysator verschiedenes Metall umfasst, innerhalb eines Bereiches der Halbleiterschicht (210, 320, 420) unter dem Kontaktloch (270, 370, 470) von der Oberfläche der Halbleiterschicht (210, 320, 420) bis zu einer festgelegten Tiefe und dadurch Gettern des in einem Kanalbereich (212, 322, 422) der Halbleiterschicht (210, 320,420) vorliegenden Metallkatalysators in Bereiche der Halbleiterschicht (210, 320, 420), die in direktem Kontakt mit der metallhaltigen Schicht (280, 380, 480) stehen,
    ferner umfassend ein Ausbilden einer thermischen Oxidationssperre (290, 385, 490) auf der metallhaltigen Schicht (280, 380, 480) vor der Wärmebehandlung des Substrats (100, 300, 400) und, nach dem Gettern des Metallkatalysators, Entfernen der metallhaltigen Schicht (280, 380, 480) und Ausbilden von Source- und Drainelektroden, die mit den Source- und Drainbereichen der Halbleiterschicht auf der isolierenden Zwischenschicht in Kontakt stehen.
  2. Verfahren nach Anspruch 1,
    wobei die metallhaltige Schicht (280, 380, 480) eine Metallschicht umfasst, die ein Metall oder eine Legierung eines solchen mit einem kleineren Diffusionskoeffizienten als der Metallkatalysator (140b) aufweist,
    oder wobei die metallhaltige Schicht (280, 380, 480) eine Metallsilicidschicht umfasst, die ein Metallsilicid oder eine Legierung eines solchen mit einem kleineren Diffusionskoeffizientenals der Metallkatalysator (140b) aufweist.
  3. Verfahren nach Anspruch 2,
    wobei der Diffusionskoeffizient der metallhaltigen Schicht (280, 380, 480) nicht größer ist als 1/100 des Diffusionskoeffizienten des Metallkatalysators (140b).
  4. Verfahren nach einem der vorangehenden Ansprüche,
    wobei der Metallkatalysator (140b) Nickel ist und der Diffusionskoeffizient der metallhaltigen Schicht (280, 380, 480) höher als 0 und niedriger als 107 cm2/s ist.
  5. Verfahren nach einem der vorangehenden Ansprüche,
    wobei die metallhaltige Schicht (280, 380, 480) eines, ausgewählt aus der Gruppe bestehend aus Sc, Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, W, Mn, Re, Ru, Os, Co, Rh, Ir, Pt, Y, La, Ce, Pr, Nd, Dy, Ho, TiN, TaN und einer Legierung dieser, umfasst.
  6. Verfahren nach einem der vorangehenden Ansprüche,
    wobei der Schritt der Wärmebehandlung des Substrats (100, 300, 400) 10 Sekunden bis 10 Stunden lang bei einer Temperatur von 500 °C bis 993 °C durchgeführt wird und/oder wobei der Schritt der Kristallisierung der amorphen Siliciumschicht mithilfe eines Super-Grain-Silicon- (SGS) Kristallisationsverfahrens durchgeführt wird.
  7. Verfahren nach einem der vorangehenden Ansprüche,
    ferner umfassend:
    Implantieren n-leitender oder p-leitender Verunreinigungen in die Bereiche der Halbleiterschicht, die mit der metallhaltigen Schicht (280, 380, 480) in Kontakt stehen, oder Ausbilden eines Beschädigungsbereiches unter Verwendung von Ionen oder Plasma.
  8. Verfahren zur Herstellung einer organischen lichtemittierenden Dioden- (OLED) Anzeigevorrichtung, umfassend:
    Ausbilden einer organischen Schicht, die eine emittierende Schicht enthält, auf einer ersten Elektrode; und
    Ausbilden einer zweiten Elektrode auf der organischen Schicht,
    gekennzeichnet dadurch, dass es ferner folgende Schritte umfasst:
    Herstellen eines Dünnschichttransistors nach einem der Ansprüche 1-7;
    und Verbinden des Dünnschichttransistors mit der ersten Elektrode.
EP08162758.0A 2007-08-23 2008-08-21 Herstellungsverfahren für Dünnschichttransistor und organische lichtemittierende Diodenanzeigevorrichtung damit Active EP2028687B1 (de)

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Families Citing this family (21)

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Publication number Priority date Publication date Assignee Title
KR100875432B1 (ko) 2007-05-31 2008-12-22 삼성모바일디스플레이주식회사 다결정 실리콘층의 제조 방법, 이를 이용하여 형성된박막트랜지스터, 그의 제조방법 및 이를 포함하는유기전계발광표시장치
KR100889626B1 (ko) 2007-08-22 2009-03-20 삼성모바일디스플레이주식회사 박막트랜지스터, 그의 제조방법, 이를 구비한유기전계발광표시장치, 및 그의 제조방법
KR100889627B1 (ko) 2007-08-23 2009-03-20 삼성모바일디스플레이주식회사 박막트랜지스터, 그의 제조방법, 및 이를 구비한유기전계발광표시장치
KR100982310B1 (ko) 2008-03-27 2010-09-15 삼성모바일디스플레이주식회사 박막트랜지스터, 그의 제조방법, 및 이를 포함하는유기전계발광표시장치
KR100989136B1 (ko) 2008-04-11 2010-10-20 삼성모바일디스플레이주식회사 박막트랜지스터, 그의 제조방법, 및 이를 포함하는유기전계발광표시장치
KR101002666B1 (ko) 2008-07-14 2010-12-21 삼성모바일디스플레이주식회사 박막트랜지스터, 그의 제조방법, 및 이를 포함하는유기전계발광표시장치
KR101050467B1 (ko) * 2010-04-14 2011-07-20 삼성모바일디스플레이주식회사 다결정 실리콘층, 그 제조방법, 상기 다결정 실리층을 이용한 박막 트랜지스터 및 상기 박막 트랜지스터를 구비한 유기발광표시장치
KR101146993B1 (ko) * 2010-06-03 2012-05-22 삼성모바일디스플레이주식회사 실리콘층의 결정화 방법 및 상기 결정화 방법을 이용한 박막 트랜지스터의 형성방법
KR101108177B1 (ko) * 2010-07-07 2012-01-31 삼성모바일디스플레이주식회사 박막 트랜지스터의 ｌｄｄ 형성방법, 이를 이용한 박막 트랜지스터 및 유기 전계 발광 장치의 제조 방법
KR101733196B1 (ko) 2010-09-03 2017-05-25 삼성디스플레이 주식회사 박막 트랜지스터, 이의 제조 방법, 및 이를 구비한 표시 장치
KR20120131753A (ko) * 2011-05-26 2012-12-05 삼성디스플레이 주식회사 박막 트랜지스터, 박막 트랜지스터의 제조 방법 및 유기 발광 표시 장치
KR101809661B1 (ko) * 2011-06-03 2017-12-18 삼성디스플레이 주식회사 박막 트랜지스터, 그 제조 방법 및 이를 포함하는 유기 발광 표시 장치
KR20130007283A (ko) * 2011-06-30 2013-01-18 삼성디스플레이 주식회사 박막 트랜지스터, 이를 구비한 표시 장치, 및 그 제조 방법
KR102164941B1 (ko) * 2014-01-13 2020-10-14 삼성디스플레이 주식회사 박막 트랜지스터 기판, 이를 포함하는 표시 장치, 및 박막 트랜지스터 기판의 제조 방법
KR102239841B1 (ko) 2014-08-06 2021-04-14 삼성디스플레이 주식회사 박막 트랜지스터, 이를 구비하는 디스플레이 장치, 박막 트랜지스터의 제조방법 및 디스플레이 장치의 제조방법
CN104300006A (zh) * 2014-10-17 2015-01-21 京东方科技集团股份有限公司 薄膜晶体管及其制造方法、oled背板和显示装置
CN104538350A (zh) * 2014-12-30 2015-04-22 深圳市华星光电技术有限公司 多晶硅基板及其制造方法
TWI548100B (zh) * 2015-01-08 2016-09-01 友達光電股份有限公司 薄膜電晶體、顯示面板以及其製造方法
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WO2020133059A1 (zh) * 2018-12-27 2020-07-02 深圳市柔宇科技有限公司 一种功能器件及其制造方法
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Family Cites Families (100)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3465209A (en) * 1966-07-07 1969-09-02 Rca Corp Semiconductor devices and methods of manufacture thereof
JPS62104173A (ja) 1985-10-31 1987-05-14 Fujitsu Ltd 半導体装置
JP3122177B2 (ja) 1991-08-09 2001-01-09 旭硝子株式会社 薄膜トランジスタとその製造方法
TW232751B (en) * 1992-10-09 1994-10-21 Semiconductor Energy Res Co Ltd Semiconductor device and method for forming the same
JP2762215B2 (ja) * 1993-08-12 1998-06-04 株式会社半導体エネルギー研究所 薄膜トランジスタおよび半導体装置の作製方法
JPH07176753A (ja) 1993-12-17 1995-07-14 Semiconductor Energy Lab Co Ltd 薄膜半導体装置およびその作製方法
JP3403807B2 (ja) 1994-06-02 2003-05-06 松下電器産業株式会社 薄膜トランジスタおよび液晶表示装置
JP2738315B2 (ja) 1994-11-22 1998-04-08 日本電気株式会社 薄膜トランジスタおよびその製造方法
JPH08255907A (ja) 1995-01-18 1996-10-01 Canon Inc 絶縁ゲート型トランジスタ及びその製造方法
US5771110A (en) * 1995-07-03 1998-06-23 Sanyo Electric Co., Ltd. Thin film transistor device, display device and method of fabricating the same
JP3744980B2 (ja) * 1995-07-27 2006-02-15 株式会社半導体エネルギー研究所 半導体装置
TW374196B (en) * 1996-02-23 1999-11-11 Semiconductor Energy Lab Co Ltd Semiconductor thin film and method for manufacturing the same and semiconductor device and method for manufacturing the same
JPH1012882A (ja) 1996-06-20 1998-01-16 Toshiba Corp 薄膜トランジスタ及びその製造方法
US6746905B1 (en) * 1996-06-20 2004-06-08 Kabushiki Kaisha Toshiba Thin film transistor and manufacturing process therefor
TW324862B (en) 1996-07-03 1998-01-11 Hitachi Ltd Liquid display apparatus
JPH10150204A (ja) * 1996-09-19 1998-06-02 Toshiba Corp 半導体装置およびその製造方法
JPH10135475A (ja) * 1996-10-31 1998-05-22 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
TW386238B (en) * 1997-01-20 2000-04-01 Semiconductor Energy Lab Semiconductor device and method of manufacturing the same
JP3942683B2 (ja) 1997-02-12 2007-07-11 株式会社半導体エネルギー研究所 半導体装置作製方法
JP3544280B2 (ja) * 1997-03-27 2004-07-21 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP3717634B2 (ja) 1997-06-17 2005-11-16 株式会社半導体エネルギー研究所 半導体装置の作製方法
JPH11111992A (ja) 1997-09-30 1999-04-23 Toshiba Corp 薄膜トランジスタ、相補型薄膜トランジスタ、および薄膜トランジスタの製造方法
JPH11261075A (ja) 1998-03-13 1999-09-24 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
US6369410B1 (en) * 1997-12-15 2002-04-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the semiconductor device
KR19990075412A (ko) 1998-03-20 1999-10-15 윤종용 박막 트랜지스터 및 그 제조 방법
US6331476B1 (en) 1998-05-26 2001-12-18 Mausushita Electric Industrial Co., Ltd. Thin film transistor and producing method thereof
US6506669B1 (en) * 1998-06-30 2003-01-14 Matsushita Electric Industrial Co., Ltd. Method of fabricating a thin film transistor
JP4030193B2 (ja) * 1998-07-16 2008-01-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6346437B1 (en) * 1998-07-16 2002-02-12 Sharp Laboratories Of America, Inc. Single crystal TFT from continuous transition metal delivery method
US6559036B1 (en) * 1998-08-07 2003-05-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
JP4376331B2 (ja) 1998-08-07 2009-12-02 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6380007B1 (en) * 1998-12-28 2002-04-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of the same
JP4531177B2 (ja) 1998-12-28 2010-08-25 株式会社半導体エネルギー研究所 半導体装置の作製方法
KR100303711B1 (ko) 1999-01-28 2001-09-26 장 진 다결정/비정질 실리콘 이중 활성층을 가지는 박막트랜지스터 및
GB2354882B (en) * 1999-03-10 2004-06-02 Matsushita Electric Ind Co Ltd Thin film transistor panel and their manufacturing method
US6680487B1 (en) 1999-05-14 2004-01-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor comprising a TFT provided on a substrate having an insulating surface and method of fabricating the same
JP4270719B2 (ja) 1999-06-30 2009-06-03 株式会社東芝 半導体装置及びその製造方法
JP4437570B2 (ja) * 1999-07-12 2010-03-24 株式会社ルネサステクノロジ 半導体装置及び半導体装置の製造方法
JP2001102169A (ja) * 1999-10-01 2001-04-13 Sanyo Electric Co Ltd Ｅｌ表示装置
US20020020840A1 (en) 2000-03-10 2002-02-21 Setsuo Nakajima Semiconductor device and manufacturing method thereof
TWI301907B (en) * 2000-04-03 2008-10-11 Semiconductor Energy Lab Semiconductor device, liquid crystal display device and manfacturing method thereof
JP2001319878A (ja) * 2000-05-11 2001-11-16 Sharp Corp 半導体製造方法
JP2002093745A (ja) 2000-09-12 2002-03-29 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
KR100439345B1 (ko) * 2000-10-31 2004-07-07 피티플러스(주) 폴리실리콘 활성층을 포함하는 박막트랜지스터 및 제조 방법
US7045444B2 (en) * 2000-12-19 2006-05-16 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device that includes selectively adding a noble gas element
US6807206B2 (en) * 2001-04-16 2004-10-19 The Furukawa Electric Co., Ltd. Semiconductor laser device and drive control method for a semiconductor laser device
TW546846B (en) * 2001-05-30 2003-08-11 Matsushita Electric Ind Co Ltd Thin film transistor and method for manufacturing the same
US6743700B2 (en) * 2001-06-01 2004-06-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor film, semiconductor device and method of their production
JP3961240B2 (ja) * 2001-06-28 2007-08-22 株式会社半導体エネルギー研究所 半導体装置の作製方法
KR100662493B1 (ko) * 2001-07-10 2007-01-02 엘지.필립스 엘시디 주식회사 비정질막의 결정화방법 및 이를 이용한 액정표시소자의제조방법
US6952023B2 (en) * 2001-07-17 2005-10-04 Semiconductor Energy Laboratory Co., Ltd. Light emitting device
JP2003075870A (ja) 2001-09-06 2003-03-12 Toshiba Corp 平面表示装置およびその製造方法
JP2003100633A (ja) 2001-09-25 2003-04-04 Sharp Corp 半導体装置の製造方法および半導体装置
JP3600229B2 (ja) 2001-10-31 2004-12-15 株式会社半導体エネルギー研究所 電界効果型トランジスタの製造方法
JP2003188098A (ja) 2001-12-13 2003-07-04 Sharp Corp 半導体装置およびその製造方法
KR100452445B1 (ko) 2001-12-29 2004-10-08 엘지.필립스 엘시디 주식회사 다결정 실리콘 박막트랜지스터 제조방법
US20030155572A1 (en) * 2002-02-19 2003-08-21 Min-Koo Han Thin film transistor and method for manufacturing thereof
KR100488959B1 (ko) 2002-03-08 2005-05-11 비오이 하이디스 테크놀로지 주식회사 다결정 실리콘 박막트랜지스터의 제조 방법
KR100488958B1 (ko) 2002-03-08 2005-05-11 비오이 하이디스 테크놀로지 주식회사 다결정 실리콘 박막트랜지스터의 제조 방법
JP2003298059A (ja) 2002-03-29 2003-10-17 Advanced Lcd Technologies Development Center Co Ltd 薄膜トランジスタ
JP4115153B2 (ja) 2002-04-08 2008-07-09 シャープ株式会社 半導体装置の製造方法
JP4115158B2 (ja) * 2002-04-24 2008-07-09 シャープ株式会社 半導体装置およびその製造方法
JP2004022845A (ja) 2002-06-17 2004-01-22 Sharp Corp 薄膜トランジスタおよびその製造方法並びに表示装置
JP4115283B2 (ja) * 2003-01-07 2008-07-09 シャープ株式会社 半導体装置およびその製造方法
KR100928490B1 (ko) * 2003-06-28 2009-11-26 엘지디스플레이 주식회사 액정표시패널 및 그 제조 방법
JP2005057240A (ja) * 2003-07-23 2005-03-03 Seiko Epson Corp 薄膜半導体素子、及び薄膜半導体素子の製造方法
KR100556370B1 (ko) * 2003-08-14 2006-03-03 엘지전자 주식회사 김치 전용 냉장고의 김치 숙성 방법
KR100515357B1 (ko) 2003-08-14 2005-09-15 삼성에스디아이 주식회사 게이트와 바디가 전기적으로 연결된 박막 트랜지스터와 그제조방법
KR100501706B1 (ko) 2003-10-16 2005-07-18 삼성에스디아이 주식회사 게이트-바디콘택 박막 트랜지스터
US7202143B1 (en) * 2003-10-23 2007-04-10 The Board Of Trustees Of The University Of Arkansas Low temperature production of large-grain polycrystalline semiconductors
KR100600853B1 (ko) * 2003-11-17 2006-07-14 삼성에스디아이 주식회사 평판표시장치 및 그의 제조방법
KR100611224B1 (ko) 2003-11-22 2006-08-09 삼성에스디아이 주식회사 금속 유도 측면 결정화 방법을 이용한 박막 트랜지스터 및그의 제조 방법
KR100623247B1 (ko) * 2003-12-22 2006-09-18 삼성에스디아이 주식회사 평판표시장치 및 그의 제조방법
KR100595456B1 (ko) * 2003-12-29 2006-06-30 엘지.필립스 엘시디 주식회사 액정표시소자의 제조방법
JP4437404B2 (ja) 2004-01-08 2010-03-24 シャープ株式会社 半導体装置とその製造方法
KR100654022B1 (ko) * 2004-05-04 2006-12-04 네오폴리((주)) 금속유도측면결정화법을 이용한 박막 트랜지스터 제조방법
KR200357656Y1 (ko) 2004-05-19 2004-07-31 한국해양연구원 오탁방지장치
JP2006049823A (ja) 2004-06-28 2006-02-16 Advanced Lcd Technologies Development Center Co Ltd 半導体装置及びその製造方法
TW200601566A (en) * 2004-06-28 2006-01-01 Adv Lcd Tech Dev Ct Co Ltd Semiconductor apparatus and manufacturing method thereof
KR100656495B1 (ko) * 2004-08-13 2006-12-11 삼성에스디아이 주식회사 박막트랜지스터 및 그 제조 방법
US20060040438A1 (en) * 2004-08-17 2006-02-23 Jiong-Ping Lu Method for improving the thermal stability of silicide
KR200369779Y1 (ko) 2004-08-18 2004-12-16 서성탁 트랩을 이용한 하수관로의 악취역류차단 및 해충유입 방지장치
KR100611766B1 (ko) 2004-08-24 2006-08-10 삼성에스디아이 주식회사 박막트랜지스터 제조 방법
KR200373075Y1 (ko) 2004-10-12 2005-01-15 장한규 빨래판
KR200373076Y1 (ko) 2004-10-12 2005-01-15 황금수 톱밥제조기용 칼날고정장치 및 그 칼날
US7575959B2 (en) * 2004-11-26 2009-08-18 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
KR200384738Y1 (ko) 2005-03-02 2005-05-17 박현우 주황색의 불꽃을 내는 양초
US8088676B2 (en) * 2005-04-28 2012-01-03 The Hong Kong University Of Science And Technology Metal-induced crystallization of amorphous silicon, polycrystalline silicon thin films produced thereby and thin film transistors produced therefrom
JP5670005B2 (ja) * 2006-03-06 2015-02-18 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置及びその製造方法
TWI429028B (zh) * 2006-03-31 2014-03-01 Semiconductor Energy Lab 非揮發性半導體記憶體裝置及其製造方法
KR100770268B1 (ko) 2006-05-18 2007-10-25 삼성에스디아이 주식회사 박막트랜지스터의 제조방법
US7750403B2 (en) 2006-06-30 2010-07-06 Semiconductor Energy Laboratory Co., Ltd Semiconductor device and manufacturing method thereof
JP4481284B2 (ja) 2006-09-20 2010-06-16 株式会社半導体エネルギー研究所 半導体装置の作製方法
KR100878284B1 (ko) * 2007-03-09 2009-01-12 삼성모바일디스플레이주식회사 박막트랜지스터와 그 제조 방법 및 이를 구비한유기전계발광표시장치
KR100846985B1 (ko) * 2007-04-06 2008-07-17 삼성에스디아이 주식회사 유기 전계 발광 표시 장치 및 그 제조 방법
KR100875432B1 (ko) 2007-05-31 2008-12-22 삼성모바일디스플레이주식회사 다결정 실리콘층의 제조 방법, 이를 이용하여 형성된박막트랜지스터, 그의 제조방법 및 이를 포함하는유기전계발광표시장치
KR101383409B1 (ko) * 2007-06-08 2014-04-18 엘지디스플레이 주식회사 표시장치
KR100848341B1 (ko) 2007-06-13 2008-07-25 삼성에스디아이 주식회사 박막트랜지스터, 그의 제조방법, 및 이를 포함하는유기전계발광표시장치
KR100889627B1 (ko) 2007-08-23 2009-03-20 삼성모바일디스플레이주식회사 박막트랜지스터, 그의 제조방법, 및 이를 구비한유기전계발광표시장치
KR100982310B1 (ko) 2008-03-27 2010-09-15 삼성모바일디스플레이주식회사 박막트랜지스터, 그의 제조방법, 및 이를 포함하는유기전계발광표시장치

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
None *

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JP5197211B2 (ja) 2013-05-15
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US8283668B2 (en) 2012-10-09

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