DE69808286D1 - Emulationssytem mit zeitmultiplexverbindung - Google Patents

Emulationssytem mit zeitmultiplexverbindung

Info

Publication number
DE69808286D1
DE69808286D1 DE69808286T DE69808286T DE69808286D1 DE 69808286 D1 DE69808286 D1 DE 69808286D1 DE 69808286 T DE69808286 T DE 69808286T DE 69808286 T DE69808286 T DE 69808286T DE 69808286 D1 DE69808286 D1 DE 69808286D1
Authority
DE
Germany
Prior art keywords
emulation system
devices
time multiplex
circuit board
multiplex connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69808286T
Other languages
English (en)
Other versions
DE69808286T2 (de
Inventor
P Sample
Mikhail Bershteyn
R Butts
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Quickturn Design Systems Inc
Original Assignee
Quickturn Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Quickturn Design Systems Inc filed Critical Quickturn Design Systems Inc
Publication of DE69808286D1 publication Critical patent/DE69808286D1/de
Application granted granted Critical
Publication of DE69808286T2 publication Critical patent/DE69808286T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31717—Interconnect testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S370/00—Multiplex communications
    • Y10S370/916—Multiplexer/demultiplexer

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
DE69808286T 1997-05-30 1998-05-18 Emulationssytem mit zeitmultiplexverbindung Expired - Lifetime DE69808286T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/865,741 US5960191A (en) 1997-05-30 1997-05-30 Emulation system with time-multiplexed interconnect
PCT/US1998/010171 WO1998054664A1 (en) 1997-05-30 1998-05-18 Emulation system with time-multiplexed interconnect

Publications (2)

Publication Number Publication Date
DE69808286D1 true DE69808286D1 (de) 2002-10-31
DE69808286T2 DE69808286T2 (de) 2003-07-31

Family

ID=25346124

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69808286T Expired - Lifetime DE69808286T2 (de) 1997-05-30 1998-05-18 Emulationssytem mit zeitmultiplexverbindung

Country Status (10)

Country Link
US (4) US5960191A (de)
EP (1) EP0983562B1 (de)
JP (1) JP4424760B2 (de)
KR (1) KR20010013190A (de)
AT (1) ATE225058T1 (de)
CA (1) CA2291738A1 (de)
DE (1) DE69808286T2 (de)
IL (1) IL132983A (de)
TW (1) TW440796B (de)
WO (1) WO1998054664A1 (de)

Families Citing this family (319)

* Cited by examiner, † Cited by third party
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US6732068B2 (en) 2004-05-04
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US20030074178A1 (en) 2003-04-17
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