AU6491400A - An emulation system having a efficient emulation signal routing architecture - Google Patents

An emulation system having a efficient emulation signal routing architecture

Info

Publication number
AU6491400A
AU6491400A AU64914/00A AU6491400A AU6491400A AU 6491400 A AU6491400 A AU 6491400A AU 64914/00 A AU64914/00 A AU 64914/00A AU 6491400 A AU6491400 A AU 6491400A AU 6491400 A AU6491400 A AU 6491400A
Authority
AU
Australia
Prior art keywords
emulation
efficient
signal routing
routing architecture
emulation system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU64914/00A
Inventor
Frederic Reblewski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mentor Graphics Corp
Original Assignee
Mentor Graphics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mentor Graphics Corp filed Critical Mentor Graphics Corp
Publication of AU6491400A publication Critical patent/AU6491400A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
AU64914/00A 1999-10-22 2000-07-19 An emulation system having a efficient emulation signal routing architecture Abandoned AU6491400A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US42562199A 1999-10-22 1999-10-22
US09425621 1999-10-22
PCT/US2000/019744 WO2001031516A2 (en) 1999-10-22 2000-07-19 An emulation system having a efficient emulation signal routing architecture

Publications (1)

Publication Number Publication Date
AU6491400A true AU6491400A (en) 2001-05-08

Family

ID=23687336

Family Applications (1)

Application Number Title Priority Date Filing Date
AU64914/00A Abandoned AU6491400A (en) 1999-10-22 2000-07-19 An emulation system having a efficient emulation signal routing architecture

Country Status (4)

Country Link
EP (1) EP1226526A2 (en)
JP (1) JP2003527674A (en)
AU (1) AU6491400A (en)
WO (1) WO2001031516A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1489531A1 (en) * 2003-06-20 2004-12-22 Robert Bosch Gmbh Simulation system and computer-implemented method for simulation and verifying a control system
CN1293475C (en) * 2004-05-12 2007-01-03 曾菊阳 Method and device for implementing single-chip microcomputer simulation using instruction replacement
CN110825667B (en) * 2019-11-12 2022-03-11 飞腾信息技术有限公司 Design method and structure of low-speed IO device controller

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5761484A (en) * 1994-04-01 1998-06-02 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
US5960191A (en) * 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect

Also Published As

Publication number Publication date
WO2001031516A2 (en) 2001-05-03
WO2001031516A3 (en) 2002-01-17
JP2003527674A (en) 2003-09-16
EP1226526A2 (en) 2002-07-31

Similar Documents

Publication Publication Date Title
AU1770599A (en) A least cost routing system
AU2715099A (en) A toy construction system
AU2148500A (en) A speed trap information system
AU1294799A (en) Denta-mandibular sound-transmitting system
AU2174700A (en) Brain-body actuated system
AUPQ138199A0 (en) A search system
AU5282900A (en) Acoustic counter-sniper system
AU2362601A (en) A telecommunications system
AU2297001A (en) Telestrator system
AU1173799A (en) Speaker system
AU4282899A (en) Location system
AU6919400A (en) Ontology-driven information system
AU1290401A (en) Acoustic location system
AUPQ344999A0 (en) A grading system
AU6308699A (en) Cell-cap connection system
AU1112699A (en) Integrated signal routing circuit
AU2715199A (en) A toy construction system
AU6491400A (en) An emulation system having a efficient emulation signal routing architecture
AU5430099A (en) Environmental control system
AU1895900A (en) Speaker system
AU5060299A (en) A connecting system
AU1168999A (en) Displaced position indicating system
AUPQ298299A0 (en) Signal control system
AU6013099A (en) Information system
AU4519699A (en) A vehicle limiting system

Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase