WO2001031516A3 - An emulation system having a efficient emulation signal routing architecture - Google Patents

An emulation system having a efficient emulation signal routing architecture Download PDF

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Publication number
WO2001031516A3
WO2001031516A3 PCT/US2000/019744 US0019744W WO0131516A3 WO 2001031516 A3 WO2001031516 A3 WO 2001031516A3 US 0019744 W US0019744 W US 0019744W WO 0131516 A3 WO0131516 A3 WO 0131516A3
Authority
WO
WIPO (PCT)
Prior art keywords
emulation
logic
buffered
circuit design
signal routing
Prior art date
Application number
PCT/US2000/019744
Other languages
French (fr)
Other versions
WO2001031516A2 (en
Inventor
Frederic Reblewski
Original Assignee
Mentor Graphics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mentor Graphics Corp filed Critical Mentor Graphics Corp
Priority to JP2001534027A priority Critical patent/JP2003527674A/en
Priority to AU64914/00A priority patent/AU6491400A/en
Priority to EP00952165A priority patent/EP1226526A2/en
Publication of WO2001031516A2 publication Critical patent/WO2001031516A2/en
Publication of WO2001031516A3 publication Critical patent/WO2001031516A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Logic Circuits (AREA)

Abstract

An emulation system having an efficient I/O pin utilization architecture is disclosed. The emulation system includes a number of reconfigurable logic chips and circuit design mapping software that operates to map a circuit design onto the reconfigurable logic chips to realize and emulate the circuit design. Each logic chip includes a number of buffered I/O pins. Each buffered I/O pin has associated multiplexing circuitry that operates to time multiplex input/output of multiple emulation signals through the buffered I/O pin. The circuit design mapping software operates to interconnect allocated logic resources. All emulation signal fan outs are confined within the logic chips, and output through the buffered I/O pins in a time multiplexed manner, employing multiple signal routing timing domains. Additionally/alternatively, emulation signal routing between logic chips of the same logic board are also confined to their direct connections to provide deterministic timing delay within the logic board.
PCT/US2000/019744 1999-10-22 2000-07-19 An emulation system having a efficient emulation signal routing architecture WO2001031516A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2001534027A JP2003527674A (en) 1999-10-22 2000-07-19 Emulation system with efficient routing architecture for emulation signals
AU64914/00A AU6491400A (en) 1999-10-22 2000-07-19 An emulation system having a efficient emulation signal routing architecture
EP00952165A EP1226526A2 (en) 1999-10-22 2000-07-19 An emulation system having a efficient emulation signal routing architecture

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US42562199A 1999-10-22 1999-10-22
US09/425,621 1999-10-22

Publications (2)

Publication Number Publication Date
WO2001031516A2 WO2001031516A2 (en) 2001-05-03
WO2001031516A3 true WO2001031516A3 (en) 2002-01-17

Family

ID=23687336

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/019744 WO2001031516A2 (en) 1999-10-22 2000-07-19 An emulation system having a efficient emulation signal routing architecture

Country Status (4)

Country Link
EP (1) EP1226526A2 (en)
JP (1) JP2003527674A (en)
AU (1) AU6491400A (en)
WO (1) WO2001031516A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1489531A1 (en) * 2003-06-20 2004-12-22 Robert Bosch Gmbh Simulation system and computer-implemented method for simulation and verifying a control system
CN1293475C (en) * 2004-05-12 2007-01-03 曾菊阳 Method and device for implementing single-chip microcomputer simulation using instruction replacement
CN110825667B (en) * 2019-11-12 2022-03-11 飞腾信息技术有限公司 Design method and structure of low-speed IO device controller

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5761484A (en) * 1994-04-01 1998-06-02 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
US5960191A (en) * 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5761484A (en) * 1994-04-01 1998-06-02 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
US5960191A (en) * 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
LI J ET AL: "ROUTABILITY IMPROVEMENT USING DYNAMIC INTERCONNECT ARCHITECTURE", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,US,IEEE INC. NEW YORK, vol. 6, no. 3, 1 September 1998 (1998-09-01), pages 498 - 501, XP000782324, ISSN: 1063-8210 *

Also Published As

Publication number Publication date
JP2003527674A (en) 2003-09-16
EP1226526A2 (en) 2002-07-31
AU6491400A (en) 2001-05-08
WO2001031516A2 (en) 2001-05-03

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