JPS63191432A - Loop back circuit - Google Patents

Abstract

PURPOSE:To improve the profitability of a loop back circuit by cascading one- bit registers by the share of one frame length through separating means and thus constituting a shift register, controlling a specified separating means and dividing the shift register into two front and rear part, and interposing the partial shift registers in loop back paths for digital signals in respective directions. CONSTITUTION:A specific separating means 800 is controlled to divide the shift register consisting of registers 700 into two shift register parts. One partial shift register is interposed in a loop back path for a digital signal in one direction and the other partial shift register is put in a loop back path for a digital signal in the other direction. Consequently, this couple of shift registers delay the signals in both directions properly and the profitability of the loop back circuit is improved.

Description

[Detailed Description of the Invention] [Summary] In a digital transmission device having a bidirectional folding circuit, a shift register is configured by cascade-connecting one-bit registers for one frame length via separation means, and The shift register is divided into front and rear parts by controlling the separating means,
The configuration of the delay circuit is simplified by inserting each partial shift register into the return path of the digital signal in each direction.

(Industrial Application Field) The present invention relates to improvement of a folding circuit in a digital transmission device.

FIG. 3 is a diagram showing an example of a digital transmission device to which the present invention is applied.

In FIG. 3, a digital multiplexer 1 that couples a high-speed digital transmission line 2 and a plurality of low-speed digital transmission lines 31 to 3n is shown as a digital transmission apparatus.

The digital multiplex M1 is transmitted from the telephone terminal 41 or the data terminal 4n, and is transmitted through the low-speed digital transmission lines 31 to 3.
The low-speed digital signals transmitted via the high-speed digital transmission line 2 are multiplexed, and the high-speed digital signals transmitted via the high-speed digital transmission line 2 are separated, and each The information is transmitted to each telephone terminal 41 or data terminal 4n via paths 31 to 3n.

Further, the digital multiplexer 1 includes a plurality of folding circuits 10
．． 11 to 1n are provided for maintenance and testing. For example, the return circuit 10 returns the high-speed digital signal transmitted from the high-speed digital transmission line 2 to the high-speed digital transmission line 2 again, and also returns the multiplexed digital signal transmitted from the digital multiplexer I to the high-speed digital transmission line 2. ,
It is sent back into the digital multiplexer I.

The digital signals transmitted through the high-speed digital transmission line 2 and each of the low-speed digital transmission lines 31 to 3n each have a frame length consisting of a predetermined number of bits, but the two-way transmission on the same transmission line The frame phases of the digital signals do not necessarily match.

Therefore, for example, when a high-speed digital signal arriving from the high-speed digital transmission line 2 is sent back to the high-speed digital transmission line 2 via the return circuit 10 in the return circuit 10, the digital multiplexer 1 transmits it to the high-speed digital transmission line 2. This causes a disadvantage that the frame phase of the multiplexed digital signal is different from the frame phase of the folded signal, and the folding circuit 10 requires a delay means for adjusting the frame phase of the folded signal.

This type of delay means consists of a shift register or the like having a number of stages equal to the frame length, but as the frame length increases, the delay means also becomes larger in scale, so there is a strong desire to realize an economical folding circuit. .

[Conventional technology]

FIG. 4 is a diagram showing an example of a conventional folding circuit.

In FIG. 4, transmission data SD arriving from the device side,
It is also assumed that the received data RD arriving from the transmission path side all have a frame length of 4 bits.

In normal communication conditions, selectors 201 and 20
2 are set on the input terminal Dl side, and the transmission data SD arriving from the device side is transmitted to the transmission line side via the signal line 101, selector 201 and signal line 1゜2, and the transmission data SD arriving from the transmission line side is The received data RD is transmitted to the device side via the signal line 103, the selector 202, and the signal line 104.

Note that the signal line 101 is connected to the input terminal SD of a shift register 301 having the same number of stages (4 stages) as the frame length of the transmission data SD, and the transmission data SD arriving from the signal line 101 is also transmitted to the shift register 301. and shifted by one stage in synchronization with the clock signal CLK supplied from the device side.

The output terminals Ql to Q4 of each stage of the shift register 301 are connected to the four input terminals Dl to D4 of the selector 203.
are connected to each.

Therefore, by controlling the selector 203 with the selection signal SEL I, the transmission data SD delayed by 1 bit to 4 bits is output to the output terminal
2 is transmitted to input terminal D2.

Therefore, when the selector 202 is set to the input terminal D2 side, the transmission data SD arriving at the signal line 1 (II) is delayed by 1 bit to 4 bits by the shift register 301 and the selector 203, and then is returned to the signal line 104. .

Note that the shift register 302 and selector 204 also have the same configuration as the shift register 301 and selector 203, so by setting the selector 201 to the input terminal D2 side, the received data arriving at the signal line 103 from the transmission line side RD is also returned to the signal line 102 after being delayed by 1 to 4 bits.

[Problem that the invention seeks to solve]

As is clear from the following explanation, in a conventional folding circuit, the shift register 301 and the selector 203, and the shift register 302 and the selector 204 are independently configured for the transmission data SD and the reception data RD.
A delay circuit is provided. Note that the shift registers 301 and 302 and the selectors 203 and 204 both increase in scale as the frame lengths of the transmission data SD and reception data RD become longer, so the economical efficiency of the folding circuit becomes a problem. was there.

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, 600 is a folding means for bidirectional digital signals.

700 is a register that stores l-bit signals, and the number of registers equal to the frame length of the digital signal is connected in cascade to form a shift register.

800 is a separating means inserted between each register 700 to separate the connections between each register 700.

[Effect]

If the frame length of a bidirectional signal is n hits, and the frame of a digital signal in one direction is delayed by m bits (where m<n) from the frame of a digital signal in the other direction, then By delaying the signal by m bits, the frame phase matches that of the digital signal in the other direction. By simultaneously delaying the digital signal in the other direction by (n-m), the frame phase of the digital signal in one direction coincides with that of the digital signal in one direction.

The present invention utilizes this principle, and by controlling a predetermined separating means 800, the shift register constituted by the register 700 is divided into two sets of partial shift registers.

By inserting one of the partial shift registers configured in this manner into the return path of digital signals in one direction, and performing the other partial shift; - By inserting the register into the return path of digital signals in the other direction, a set of shift 1- The register provides a suitable delay for signals in both directions, improving the economics of the folding circuit.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a folding circuit according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures. In addition, the target transmission data SD and reception data R
The frame length of D is 4 bits.

In FIG. 2, the number of flip-flops 401 is the same as the frame length of each transmission data SD and reception data RD.
404 and selectors 211 to 214 are alternately connected in cascade.

When each selector 212 to 214 is set to the input terminal DI side, each flip-flop 4, 01 to 4
The output terminal Q of 03 is a flip-flop 402, respectively.
to 4040 input terminals to form a four-stage shift register.

Note that one of the selectors 211 to 214 specified by the selection signal 5EL3 is set on the input terminal D2 side. As a result, the flip-flops 4, 01 to 404 are separated into two sets of shift registers, with the selector specified by the selection signal S E I-3 as the boundary.

For example, when the selection signal S E L 3 specifies the selector 212, a one-stage shift register consisting of a flip-flop 401 and flip-flops 402 to 4 are selected.
It is divided into three stages of shift 1 registers consisting of 04 shift registers.

On the other hand, the selector 215 is set to one of the input terminals Do to D3 designated by the 3M selection signal S E L /I, and is connected to the signal line 101 and the signal lines 111 to 113 from the output terminal Q of each Frisopflosob 401 to 403. of,
Signal % reaching input terminal D2 of selector 202? l 12
Connect to 1.

Assuming that the transmission data SD frame is now 1 bit ahead of the reception data RDO frame, selector 2
12 is set to the input terminal D2 side by the selection signal 5EL3, and the selector 215 is set to the input terminal Di side by the selection signal 5EL4.

In this state, when the selectors 201 and 202 are set to the input terminal D2 side, the transmission data SD arriving from the signal line 101 is input to the flip-flop 401 via the selector 211, and is given a 1-bit delay. After that, it is outputted to the signal line 104 via the signal line 111, the selector 215, the signal line 121, and the selector 202.
will be returned to you.

On the other hand, the received data RD arriving from the signal line 103 is input to each input terminal D2 of the selectors 211 to 214, and the selector 21 designated by the selection signal 5EL3
2 outputs the received data RD from the output terminal X and inputs it to the flip-flop 402.

After that, the received data RD is transferred to the flip-flop 402.40.
3 and 404 to give a delay of 3 bits, the signal is output from the flip-flow knob 404 and sent back to the signal line 102 via the signal line 122 and the selector 201.

As described above, the transmission data SD is transferred to the flip-flop 401.
The received data RD is delayed by 1 bit by the flip-flops 402 to 404, then the frame phase is matched with the received data RD, and then sent back.The received data RD is delayed by 3 bits by the flip-flops 402 to 404, and then the frame phase is matched with the transmitted data SD. It will be sent back.

As is clear from the above description, according to this embodiment, a single flip-flop consisting of four flip-flops 401 to 404
The set of shift registers is divided into parts, one of which is used as a delay means when turning back the transmission data SD, and the rest is used as a delay means when the transmission data SD is turned back.
It can be used as a delay means when turning back D.

Note that FIG. 2 is only one embodiment of the present invention, and for example, the frame length of the transmission data SD and reception data RD is not limited to 4 bits, and many other modifications may be considered. , by providing the required number of flip-flops and selectors, the effects of the present invention remain the same in either case. It goes without saying that the digital transmission device to which the present invention is applied is not limited to the digital multiplexing device shown in the drawings.

〔Effect of the invention〕

As described above, according to the present invention, in the digital transmission device, a delay suitable for bidirectional digital signals is provided by one set of shift registers, and the economical efficiency of the folding circuit is improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a folding circuit according to an embodiment of the present invention, FIG. 3 is a diagram showing an example of a digital transmission device to which the present invention is applied, and FIG. The figure shows an example of a conventional folding circuit. In the figure, 1 is a digital multiplexer, 2 is a high-speed digital transmission line, 10.11 to In are return circuits, and 31 is a high-speed digital transmission line.
3n to 3n are low-speed digital transmission lines, 101 to 122 are signal lines, 201 to 215 are selectors, 301 and 3
02 is a shift register, 401 to 404 are flip-flops, 600 is a turning means, 700 is a register, 8
00 indicates separation means.

Claims (1)

[Scope of Claims] In a digital transmission device that is provided with return means (600) for each bidirectional digital signal having a predetermined frame length, the register (700) stores each 1-bit signal.
are connected in cascade in a number equal to the frame length of the digital signal to form a shift register, and separating means (700) for separating connections between the respective registers (700);
800) between each of the registers (700), controls the specified separation means (800) to divide the shift register into two sets of partial shift registers, and divides one of the partial shift registers into one set. A folding circuit characterized in that the folding circuit is inserted into a folding path of the digital signal in one direction, and the other partial shift register is inserted into a folding path of the digital signal in the other direction.