DE60031081D1 - Regionalzeitmultiplexiertes emulationssystem - Google Patents

Regionalzeitmultiplexiertes emulationssystem

Info

Publication number
DE60031081D1
DE60031081D1 DE60031081T DE60031081T DE60031081D1 DE 60031081 D1 DE60031081 D1 DE 60031081D1 DE 60031081 T DE60031081 T DE 60031081T DE 60031081 T DE60031081 T DE 60031081T DE 60031081 D1 DE60031081 D1 DE 60031081D1
Authority
DE
Germany
Prior art keywords
clock
time multiplexed
emulation system
reconfigurable logic
reconfigurable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60031081T
Other languages
English (en)
Other versions
DE60031081T2 (de
Inventor
Frederic Reblewski
Olivier Lepape
Jean Barbier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mentor Graphics Corp
Original Assignee
Mentor Graphics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=23601577&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE60031081(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Mentor Graphics Corp filed Critical Mentor Graphics Corp
Publication of DE60031081D1 publication Critical patent/DE60031081D1/de
Application granted granted Critical
Publication of DE60031081T2 publication Critical patent/DE60031081T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Logic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Debugging And Monitoring (AREA)
DE60031081T 1999-09-24 2000-02-02 Regionalzeitmultiplexiertes emulationssystem Expired - Lifetime DE60031081T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US404920 1989-09-08
US09/404,920 US6947882B1 (en) 1999-09-24 1999-09-24 Regionally time multiplexed emulation system
PCT/US2000/002890 WO2001024066A1 (en) 1999-09-24 2000-02-02 A regionally time multiplexed emulation system

Publications (2)

Publication Number Publication Date
DE60031081D1 true DE60031081D1 (de) 2006-11-16
DE60031081T2 DE60031081T2 (de) 2007-01-25

Family

ID=23601577

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60031081T Expired - Lifetime DE60031081T2 (de) 1999-09-24 2000-02-02 Regionalzeitmultiplexiertes emulationssystem

Country Status (8)

Country Link
US (2) US6947882B1 (de)
EP (1) EP1116141B1 (de)
JP (2) JP3592639B2 (de)
AT (1) ATE341792T1 (de)
AU (1) AU3222400A (de)
CA (1) CA2359048C (de)
DE (1) DE60031081T2 (de)
WO (1) WO2001024066A1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7379859B2 (en) * 2001-04-24 2008-05-27 Mentor Graphics Corporation Emulator with switching network connections
US7042248B1 (en) * 2003-06-03 2006-05-09 Altera Corporation Dedicated crossbar and barrel shifter block on programmable logic resources
US7698118B2 (en) * 2004-04-15 2010-04-13 Mentor Graphics Corporation Logic design modeling and interconnection
US7224184B1 (en) * 2004-11-05 2007-05-29 Xilinx, Inc. High bandwidth reconfigurable on-chip network for reconfigurable systems
US7353162B2 (en) * 2005-02-11 2008-04-01 S2C, Inc. Scalable reconfigurable prototyping system and method
US7768301B2 (en) * 2006-01-17 2010-08-03 Abound Logic, S.A.S. Reconfigurable integrated circuits with scalable architecture including a plurality of special function elements
US7274215B2 (en) * 2006-01-17 2007-09-25 M2000 Sa. Reconfigurable integrated circuits with scalable architecture including one or more adders
US8352242B2 (en) 2006-02-21 2013-01-08 Mentor Graphics Corporation Communication scheme between programmable sub-cores in an emulation environment
WO2007095996A1 (en) * 2006-02-23 2007-08-30 Mentor Graphics Corp. Cross-bar switching in an emulation environment
US8082526B2 (en) * 2006-03-08 2011-12-20 Altera Corporation Dedicated crossbar and barrel shifter block on programmable logic resources
KR100873956B1 (ko) * 2006-08-17 2008-12-15 삼성전자주식회사 에뮬레이션 시스템
US8229725B1 (en) 2008-09-29 2012-07-24 Xilinx, Inc. Method and apparatus for modeling processor-based circuit models
TWI450118B (zh) * 2010-11-02 2014-08-21 Global Unichip Corp 混合的電子設計系統及其可重組連接矩陣
EP2871589B1 (de) * 2013-11-08 2019-06-26 Synopsys, Inc. Verfahren und System zur Erzeugung einer Schaltungsbeschreibung für ein feldprogrammierbares Gate-Array mit mehreren Matrizen
US9904749B2 (en) * 2014-02-13 2018-02-27 Synopsys, Inc. Configurable FPGA sockets
KR20220129077A (ko) * 2020-01-31 2022-09-22 시놉시스, 인크. 하드웨어 에뮬레이션 데이터를 캡처하기 위한 시스템 및 방법

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US536319A (en) * 1895-03-26 wisse
US4642487A (en) 1984-09-26 1987-02-10 Xilinx, Inc. Special interconnect for configurable logic array
US4706216A (en) 1985-02-27 1987-11-10 Xilinx, Inc. Configurable logic element
DE68925121T2 (de) 1988-10-05 1996-06-13 Quickturn Systems Inc Verfahren zur verwendung einer elektronisch wiederkonfigurierbaren gatterfeld-logik und dadurch hergestelltes gerät
US5140193A (en) * 1990-03-27 1992-08-18 Xilinx, Inc. Programmable connector for programmable logic device
US5363319A (en) * 1990-09-29 1994-11-08 Kabushiki Kaisha Toshiba Logic simulator
JP2966071B2 (ja) 1990-09-29 1999-10-25 株式会社東芝 単位遅延多重化論理要素及びこの論理要素を用いた論理シミュレータ
AU2561192A (en) 1992-08-28 1994-03-29 Prabhakar Goel Multichip ic design using tdm
US5596742A (en) 1993-04-02 1997-01-21 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
EP0665998A4 (de) * 1993-08-03 1996-06-12 Xilinx Inc Fpga-schaltkreis mit mikroprozessor.
US5761484A (en) 1994-04-01 1998-06-02 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
US5920712A (en) 1994-05-13 1999-07-06 Quickturn Design Systems, Inc. Emulation system having multiple emulator clock cycles per emulated clock cycle
JPH0830653A (ja) 1994-07-19 1996-02-02 Hitachi Ltd 論理シミュレーション装置とその制御方法
WO1996013902A1 (en) 1994-11-01 1996-05-09 Virtual Machine Works, Inc. Programmable multiplexing input/output port
US5659716A (en) 1994-11-23 1997-08-19 Virtual Machine Works, Inc. Pipe-lined static router and scheduler for configurable logic system performing simultaneous communications and computation
US5649176A (en) 1995-08-10 1997-07-15 Virtual Machine Works, Inc. Transition analysis and circuit resynthesis method and device for digital circuit modeling
US5701441A (en) * 1995-08-18 1997-12-23 Xilinx, Inc. Computer-implemented method of optimizing a design in a time multiplexed programmable logic device
US5574388A (en) 1995-10-13 1996-11-12 Mentor Graphics Corporation Emulation system having a scalable multi-level multi-stage programmable interconnect network
US5777489A (en) 1995-10-13 1998-07-07 Mentor Graphics Corporation Field programmable gate array with integrated debugging facilities
US5854752A (en) 1996-01-19 1998-12-29 Ikos Systems, Inc. Circuit partitioning technique for use with multiplexed inter-connections
US5960191A (en) * 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US5943490A (en) * 1997-05-30 1999-08-24 Quickturn Design Systems, Inc. Distributed logic analyzer for use in a hardware logic emulation system
JPH1173440A (ja) 1997-08-28 1999-03-16 Mitsubishi Electric Corp エミュレーション装置
US6094064A (en) * 1998-07-23 2000-07-25 Altera Corporation Programmable logic device incorporating and input/output overflow bus

Also Published As

Publication number Publication date
EP1116141B1 (de) 2006-10-04
JP2005051751A (ja) 2005-02-24
ATE341792T1 (de) 2006-10-15
US6947882B1 (en) 2005-09-20
EP1116141A1 (de) 2001-07-18
DE60031081T2 (de) 2007-01-25
JP3903049B2 (ja) 2007-04-11
US7098688B2 (en) 2006-08-29
US20040075469A1 (en) 2004-04-22
JP2002538540A (ja) 2002-11-12
WO2001024066A1 (en) 2001-04-05
CA2359048A1 (en) 2001-04-05
AU3222400A (en) 2001-04-30
CA2359048C (en) 2004-06-29
JP3592639B2 (ja) 2004-11-24

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Legal Events

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