WO2001090961A3 - Enhancements to object-oriented electronic circuit design modeling and simulation environment - Google Patents

Enhancements to object-oriented electronic circuit design modeling and simulation environment Download PDF

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Publication number
WO2001090961A3
WO2001090961A3 PCT/US2001/009106 US0109106W WO0190961A3 WO 2001090961 A3 WO2001090961 A3 WO 2001090961A3 US 0109106 W US0109106 W US 0109106W WO 0190961 A3 WO0190961 A3 WO 0190961A3
Authority
WO
WIPO (PCT)
Prior art keywords
instruction
electronic circuit
enhancements
modeling
circuit design
Prior art date
Application number
PCT/US2001/009106
Other languages
French (fr)
Other versions
WO2001090961A2 (en
Inventor
Jean Francois Duboc
Frederic Mallet
Fernand Boeri
Original Assignee
Koninkl Philips Electronics Nv
Philips Electronics Na
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Philips Electronics Na filed Critical Koninkl Philips Electronics Nv
Priority to EP01920629A priority Critical patent/EP1290588A2/en
Priority to JP2001587278A priority patent/JP2003534603A/en
Publication of WO2001090961A2 publication Critical patent/WO2001090961A2/en
Publication of WO2001090961A3 publication Critical patent/WO2001090961A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

An apparatus, program product and method enhance the modeling and stimulation of electronic circuit designs on computers, particularly in the area of object-oriented modeling and simulation. Multiplexed communication ports (130) may be supported that support the propagation of values for multiple signals in response to single events directed to such ports (130), thus logically combining multiple signal paths together into a single logical path. Dynamic instruction decoder generation (160) may also be supported, such that an instruction definition that defines an instruction capable of being executed by a processing system model may be utilized in the configuration of an instruction decoder circuit component (150') for the processing system model to stimulate execution of the instruction.
PCT/US2001/009106 2000-05-24 2001-03-22 Enhancements to object-oriented electronic circuit design modeling and simulation environment WO2001090961A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP01920629A EP1290588A2 (en) 2000-05-24 2001-03-22 Enhancements to object-oriented electronic circuit design modeling and simulation environment
JP2001587278A JP2003534603A (en) 2000-05-24 2001-03-22 Method and apparatus for enhancing modeling and simulation environment of electronic circuit design using object-oriented

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US57750900A 2000-05-24 2000-05-24
US09/577,509 2000-05-24

Publications (2)

Publication Number Publication Date
WO2001090961A2 WO2001090961A2 (en) 2001-11-29
WO2001090961A3 true WO2001090961A3 (en) 2002-12-05

Family

ID=24309037

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/009106 WO2001090961A2 (en) 2000-05-24 2001-03-22 Enhancements to object-oriented electronic circuit design modeling and simulation environment

Country Status (3)

Country Link
EP (1) EP1290588A2 (en)
JP (1) JP2003534603A (en)
WO (1) WO2001090961A2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2836734B1 (en) * 2002-03-01 2004-07-02 Prosilog S A METHOD FOR EXTRACTING THE TOPOLOGY OF A SYSTEM FROM ITS TEXT DESCRIPTION
FR2843213B1 (en) * 2002-07-30 2004-12-24 Bull Sa METHOD AND SYSTEM FOR AUTOMATICALLY ESTABLISHING A GLOBAL MODEL FOR SIMULATING AN ARCHITECTURE
US10281507B2 (en) 2014-11-21 2019-05-07 Kohler Co. Generator sizing
WO2017009996A1 (en) * 2015-07-16 2017-01-19 三菱電機株式会社 Information processing device, information processing method, and program
USD811423S1 (en) 2015-11-16 2018-02-27 Kohler, Co. Display screen with graphical user interface
USD810104S1 (en) 2015-11-16 2018-02-13 Kohler, Co. Display screen with graphical user interface

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
MALLET F ET AL: "Esterel and Java in an object-oriented modelling and simulation framework for heterogeneous software and hardware systems. The SEP approach", PROCEEDINGS 25TH EUROMICRO CONFERENCE. INFORMATICS: THEORY AND PRACTICE FOR THE NEW MILLENNIUM, PROCEEDINGS OF EUROMICRO WORKSHOP, MILAN, ITALY, 8-10 SEPT. 1999, 1999, Los Alamitos, CA, USA, IEEE Comput. Soc, USA, pages 214 - 221 vol.1, XP002213241, ISBN: 0-7695-0321-7 *
MALLET F ET AL: "Hardware architecture modelling using an object-oriented method", EUROMICRO CONFERENCE, 1998. PROCEEDINGS. 24TH VASTERAS, SWEDEN 25-27 AUG. 1998, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 25 August 1998 (1998-08-25), pages 147 - 153, XP010298090, ISBN: 0-8186-8646-4 *

Also Published As

Publication number Publication date
EP1290588A2 (en) 2003-03-12
WO2001090961A2 (en) 2001-11-29
JP2003534603A (en) 2003-11-18

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