NO945097D0 - Demultiplekserkrets, multiplekserkrets, forsinkelseslinjekrets og klokkemultiplisererkrets - Google Patents

Demultiplekserkrets, multiplekserkrets, forsinkelseslinjekrets og klokkemultiplisererkrets

Info

Publication number
NO945097D0
NO945097D0 NO945097A NO945097A NO945097D0 NO 945097 D0 NO945097 D0 NO 945097D0 NO 945097 A NO945097 A NO 945097A NO 945097 A NO945097 A NO 945097A NO 945097 D0 NO945097 D0 NO 945097D0
Authority
NO
Norway
Prior art keywords
circuit
delay line
demultiplexer
multiplexer
clock multiplier
Prior art date
Application number
NO945097A
Other languages
English (en)
Other versions
NO945097L (no
Inventor
Mats Olof Joakim Hedberg
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of NO945097L publication Critical patent/NO945097L/no
Publication of NO945097D0 publication Critical patent/NO945097D0/no

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006—Changing the frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
    • H03K5/1504—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a chain of active delay devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/04—Distributors combined with modulators or demodulators
    • H04J3/047—Distributors with transistors or integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
NO945097A 1992-07-01 1994-12-30 Demultiplekserkrets, multiplekserkrets, forsinkelseslinjekrets og klokkemultiplisererkrets NO945097D0 (no)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9202032A SE515076C2 (sv) 1992-07-01 1992-07-01 Multiplexor-/demultiplexorkrets
PCT/SE1993/000531 WO1994001945A1 (en) 1992-07-01 1993-06-15 Demultiplexor circuit, multiplexor circuit, delay line circuit and clock multiplying circuit

Publications (2)

Publication Number Publication Date
NO945097L NO945097L (no) 1994-12-30
NO945097D0 true NO945097D0 (no) 1994-12-30

Family

ID=20386672

Family Applications (1)

Application Number Title Priority Date Filing Date
NO945097A NO945097D0 (no) 1992-07-01 1994-12-30 Demultiplekserkrets, multiplekserkrets, forsinkelseslinjekrets og klokkemultiplisererkrets

Country Status (12)

Country Link
US (2) US5526361A (no)
EP (1) EP0671086A1 (no)
JP (1) JPH07508626A (no)
CN (1) CN1085710A (no)
AU (1) AU679447B2 (no)
BR (1) BR9306648A (no)
CA (1) CA2139237A1 (no)
FI (1) FI946198A (no)
MX (1) MX9303891A (no)
NO (1) NO945097D0 (no)
SE (1) SE515076C2 (no)
WO (1) WO1994001945A1 (no)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9308944D0 (en) * 1993-04-30 1993-06-16 Inmos Ltd Ring oscillator
SE9303339L (sv) * 1993-10-12 1995-01-09 Ellemtel Utvecklings Ab Signalbearbetande enhet med intern klocksignal
US5475322A (en) * 1993-10-12 1995-12-12 Wang Laboratories, Inc. Clock frequency multiplying and squaring circuit and method
US5617417A (en) * 1994-09-07 1997-04-01 Stratacom, Inc. Asynchronous transfer mode communication in inverse multiplexing over multiple communication links
JPH0955667A (ja) * 1995-08-10 1997-02-25 Mitsubishi Electric Corp マルチプレクサ，及びデマルチプレクサ
US5987030A (en) 1996-09-27 1999-11-16 Cisco Technology, Inc. Transparent circuit emulation for packet switching network
AU5310798A (en) * 1996-12-18 1998-07-15 Dsc Communications A/S A method of generating a plurality of demultiplexed output signals from a serial data signal and a circuit for performing the method
US5978379A (en) 1997-01-23 1999-11-02 Gadzoox Networks, Inc. Fiber channel learning bridge, learning half bridge, and protocol
US6052646A (en) * 1998-04-15 2000-04-18 Magellan Dis, Inc. Vehicle navigation system with improved powerup performance
AU762120B2 (en) * 1998-09-08 2003-06-19 Siemens Aktiengesellschaft Circuit and method for generating clock pulses
US6879650B1 (en) * 1998-09-23 2005-04-12 Paradyne Corporation Circuit and method for detecting and correcting data clocking errors
US7430171B2 (en) 1998-11-19 2008-09-30 Broadcom Corporation Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost
US7012983B2 (en) 2000-04-28 2006-03-14 Broadcom Corporation Timing recovery and phase tracking system and method
JP3705102B2 (ja) * 2000-09-14 2005-10-12 日本電気株式会社 通信装置
US7006509B1 (en) 2000-12-22 2006-02-28 Cisco Technology, Inc. Method and system for graceful slowlink deletion and subsequent fast link addition in an IMA group
US6952434B1 (en) 2000-12-27 2005-10-04 Cisco Technology, Inc. System and method for processing control cells to prevent event missequencing and data loss in IMA groups
US7065104B1 (en) 2000-12-28 2006-06-20 Cisco Technology, Inc. Method and system for managing inverse multiplexing over ATM
US6437725B1 (en) * 2001-03-15 2002-08-20 Samsung Electronics Co., Ltd. Parallel to serial converter
US6870569B1 (en) * 2001-07-16 2005-03-22 National Semiconductor Corporation Integrated multilevel signal demultiplexor
US6653876B2 (en) * 2002-04-23 2003-11-25 Broadcom Corporation Method and apparatus for synthesizing a clock signal using a compact and low power delay locked loop (DLL)
JP3859544B2 (ja) * 2002-05-23 2006-12-20 富士通株式会社 データ受信回路
EP1554802A2 (en) * 2002-10-16 2005-07-20 Koninklijke Philips Electronics N.V. Pulse generator
JP4007313B2 (ja) * 2003-01-22 2007-11-14 株式会社村田製作所 角度センサ
ES2684379T3 (es) * 2003-03-06 2018-10-02 Trustees Of Boston University Aparato para mejorar el equilibrio y la marcha en humanos y prevenir lesiones en los pies
JP4400081B2 (ja) 2003-04-08 2010-01-20 エルピーダメモリ株式会社 半導体記憶装置
US20080309391A1 (en) * 2007-06-15 2008-12-18 Chang-Po Ma Delay circuit and related method thereof
US7782109B2 (en) * 2007-06-15 2010-08-24 Mediatek Inc. Delay circuit and related method
JP2009021870A (ja) * 2007-07-12 2009-01-29 Sony Corp 信号生成装置、フィルタ装置、信号生成方法およびフィルタ方法
US8055441B2 (en) * 2007-07-27 2011-11-08 Mitac International Corporation Supplemental powered information receiver
US8510589B2 (en) * 2008-08-29 2013-08-13 Intel Mobile Communications GmbH Apparatus and method using first and second clocks
US20120155567A1 (en) * 2010-12-20 2012-06-21 Samsung Electro-Mechanics Co., Ltd. Data transmission apparatus and transmission method thereof
EP2755350A1 (en) * 2013-01-15 2014-07-16 Alcatel-Lucent Apparatus for performing clock and/or data recovery
US11171584B1 (en) * 2020-05-11 2021-11-09 Pix Art Imaging Inc. Interpolation circuit and motor driving circuit

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3995119A (en) * 1975-05-30 1976-11-30 Gte Automatic Electric Laboratories Incorporated Digital time-division multiplexing system
US3995120A (en) * 1975-05-30 1976-11-30 Gte Automatic Electric Laboratories Incorporated Digital time-division multiplexing system
US3993957A (en) * 1976-03-08 1976-11-23 International Business Machines Corporation Clock converter circuit
JPS57186836A (en) * 1981-05-14 1982-11-17 Nec Corp Counting circuit
JPS60204121A (ja) * 1984-03-29 1985-10-15 Fujitsu Ltd 位相同期回路
CA1254957A (en) * 1986-11-07 1989-05-30 Mitel Corporation Frequency doubler
US4791628A (en) * 1987-10-16 1988-12-13 American Telephone And Telegraph Company, At&T Bell Labs High-speed demultiplexer circuit
US4789984A (en) * 1987-10-16 1988-12-06 American Telephone And Telegraph Company, At&T Bell Laboratories High-speed multiplexer circuit
US4821297A (en) * 1987-11-19 1989-04-11 American Telephone And Telegraph Company, At&T Bell Laboratories Digital phase locked loop clock recovery scheme
JPH0773219B2 (ja) * 1988-06-16 1995-08-02 富士通株式会社 並直列変換装置
US4926423A (en) * 1988-09-30 1990-05-15 The Trustees Of Columbia University In The City Of New York Time-division-multiplexed data transmission system
CA2001266C (en) * 1989-10-23 1996-08-06 John Robert Long Digital phase aligner and method for its operation
US5111455A (en) * 1990-08-24 1992-05-05 Avantek, Inc. Interleaved time-division multiplexor with phase-compensated frequency doublers
US5150364A (en) * 1990-08-24 1992-09-22 Hewlett-Packard Company Interleaved time-division demultiplexor
SE469616B (sv) * 1991-12-23 1993-08-02 Ellemtel Utvecklings Ab Anordning foer foerskjutning av fasen hos en klocksignal samt saett och anordning foer taktaatervinning hos en digital datasignal
US5521499A (en) * 1992-12-23 1996-05-28 Comstream Corporation Signal controlled phase shifter
US5412697A (en) * 1993-01-14 1995-05-02 Apple Computer, Inc. Delay line separator for data bus

Also Published As

Publication number Publication date
AU4518293A (en) 1994-01-31
FI946198A0 (fi) 1994-12-30
US5526361A (en) 1996-06-11
FI946198A (fi) 1995-01-26
CA2139237A1 (en) 1994-01-20
JPH07508626A (ja) 1995-09-21
CN1085710A (zh) 1994-04-20
WO1994001945A1 (en) 1994-01-20
SE9202032L (sv) 1994-01-02
SE9202032D0 (sv) 1992-07-01
MX9303891A (es) 1994-01-31
US5734283A (en) 1998-03-31
EP0671086A1 (en) 1995-09-13
AU679447B2 (en) 1997-07-03
SE515076C2 (sv) 2001-06-05
NO945097L (no) 1994-12-30
BR9306648A (pt) 1998-12-08

Similar Documents

Publication Publication Date Title
NO945097D0 (no) Demultiplekserkrets, multiplekserkrets, forsinkelseslinjekrets og klokkemultiplisererkrets
DE69526419D1 (de) Zeitverzögerungsschaltung
DE69308978T2 (de) Verzögerungsschaltung
DE69833595D1 (de) Synchrone Verzögerungsschaltung
BR9706700A (pt) Relógio eletrônico combinado
DE69620323T2 (de) Eingangspufferschaltung
DE69509267D1 (de) Taktschaltung
DE69735047D1 (de) Verzögerungsschaltung
DE69428822T2 (de) Invertierende Verzögerungsschaltung
DE69840993D1 (de) Synchrone Verzögerungsschaltung
DE69429583T2 (de) Synchronisierungsschaltungsanordnung
GB9524560D0 (en) Multiplexer circuit
DE69613628D1 (de) Eingangsschaltung
GB9614480D0 (en) Multiplexer circuit
DE69820925D1 (de) Takteingangsschaltung
NO952599D0 (no) Stoppeklokke og klokkesystem
DE69611768D1 (de) Multiplizierschaltung
DE69323684T2 (de) Verzögerungsschaltung
DE69816538D1 (de) Synchrone Verzögerungsschaltung
DE59607740D1 (de) Verzögerungsschaltung
GB2356091B (en) Clock adjustment using a dummy input circuit
DE69720342D1 (de) Eingangsschaltung
DE29511680U1 (de) Multiplikationsschaltung
KR970011503U (ko) 교환기의 망동기 클럭수신회로
KR980005743U (ko) 클럭 주파수 체배회로