DE68923894D1 - Halbleitersubstrat mit dielektrischer Isolierung. - Google Patents

Halbleitersubstrat mit dielektrischer Isolierung.

Info

Publication number
DE68923894D1
DE68923894D1 DE68923894T DE68923894T DE68923894D1 DE 68923894 D1 DE68923894 D1 DE 68923894D1 DE 68923894 T DE68923894 T DE 68923894T DE 68923894 T DE68923894 T DE 68923894T DE 68923894 D1 DE68923894 D1 DE 68923894D1
Authority
DE
Germany
Prior art keywords
semiconductor substrate
dielectric insulation
dielectric
insulation
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE68923894T
Other languages
English (en)
Other versions
DE68923894T2 (de
Inventor
Yoshihiro C O Patent Yamaguchi
Kiminori C O Patent D Watanabe
Akio C O Patent Divis Nakagawa
Kazuyoshi C O Patent Furukawa
Kiyoshi C O Patent Divi Fukuda
Katsujiro C O Patent D Tanzawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE68923894D1 publication Critical patent/DE68923894D1/de
Application granted granted Critical
Publication of DE68923894T2 publication Critical patent/DE68923894T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/012—Bonding, e.g. electrostatic for strain gauges
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/159—Strain gauges

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Bipolar Transistors (AREA)
DE68923894T 1988-03-31 1989-03-31 Halbleitersubstrat mit dielektrischer Isolierung. Expired - Lifetime DE68923894T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7871488 1988-03-31
JP63173701A JP2685819B2 (ja) 1988-03-31 1988-07-14 誘電体分離半導体基板とその製造方法

Publications (2)

Publication Number Publication Date
DE68923894D1 true DE68923894D1 (de) 1995-09-28
DE68923894T2 DE68923894T2 (de) 1996-04-18

Family

ID=26419764

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68923894T Expired - Lifetime DE68923894T2 (de) 1988-03-31 1989-03-31 Halbleitersubstrat mit dielektrischer Isolierung.

Country Status (5)

Country Link
US (1) US4878957A (de)
EP (1) EP0335741B1 (de)
JP (1) JP2685819B2 (de)
KR (1) KR920007333B1 (de)
DE (1) DE68923894T2 (de)

Families Citing this family (64)

* Cited by examiner, † Cited by third party
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JPH0355822A (ja) * 1989-07-25 1991-03-11 Shin Etsu Handotai Co Ltd 半導体素子形成用基板の製造方法
JPH0636414B2 (ja) * 1989-08-17 1994-05-11 信越半導体株式会社 半導体素子形成用基板の製造方法
DD290077A5 (de) * 1989-12-15 1991-05-16 Adw Der Ddr,De Verfahren zum bonden von halbleitersubstraten
US5250836A (en) * 1989-12-20 1993-10-05 Fujitsu Limited Semiconductor device having silicon-on-insulator structure
JP2777920B2 (ja) * 1989-12-20 1998-07-23 富士通株式会社 半導体装置及びその製造方法
US5241211A (en) * 1989-12-20 1993-08-31 Nec Corporation Semiconductor device
JP2712690B2 (ja) * 1990-01-16 1998-02-16 富士電機株式会社 素子分離溝を有する半導体装置の製造方法
US5362667A (en) * 1992-07-28 1994-11-08 Harris Corporation Bonded wafer processing
JPH0719737B2 (ja) * 1990-02-28 1995-03-06 信越半導体株式会社 Ｓ０１基板の製造方法
US5034343A (en) * 1990-03-08 1991-07-23 Harris Corporation Manufacturing ultra-thin wafer using a handle wafer
JPH0636413B2 (ja) * 1990-03-29 1994-05-11 信越半導体株式会社 半導体素子形成用基板の製造方法
JP3190057B2 (ja) * 1990-07-02 2001-07-16 株式会社東芝 複合集積回路装置
JPH0719738B2 (ja) * 1990-09-06 1995-03-06 信越半導体株式会社 接合ウェーハ及びその製造方法
US5172205A (en) * 1990-09-26 1992-12-15 Nissan Motor Co., Ltd. Piezoresistive semiconductor device suitable for use in a pressure sensor
JPH0775245B2 (ja) * 1990-11-16 1995-08-09 信越半導体株式会社 誘電体分離基板及びその製造方法
US5091330A (en) * 1990-12-28 1992-02-25 Motorola, Inc. Method of fabricating a dielectric isolated area
DE4114660C2 (de) * 1991-05-06 1997-09-18 Telefunken Microelectron Verfahren zur Herstellung glaspassivierter Halbleiterbauelemente
DE4115046A1 (de) * 1991-05-08 1992-11-12 Fraunhofer Ges Forschung Direktes substratbonden
US5250837A (en) * 1991-05-17 1993-10-05 Delco Electronics Corporation Method for dielectrically isolating integrated circuits using doped oxide sidewalls
US5250461A (en) * 1991-05-17 1993-10-05 Delco Electronics Corporation Method for dielectrically isolating integrated circuits using doped oxide sidewalls
CA2069038C (en) * 1991-05-22 1997-08-12 Kiyofumi Sakaguchi Method for preparing semiconductor member
JP2799254B2 (ja) * 1991-07-11 1998-09-17 三菱電機株式会社 半導体装置の製造方法
JP3017860B2 (ja) * 1991-10-01 2000-03-13 株式会社東芝 半導体基体およびその製造方法とその半導体基体を用いた半導体装置
DE69233314T2 (de) * 1991-10-11 2005-03-24 Canon K.K. Verfahren zur Herstellung von Halbleiter-Produkten
US6909146B1 (en) 1992-02-12 2005-06-21 Intersil Corporation Bonded wafer with metal silicidation
US5366924A (en) * 1992-03-16 1994-11-22 At&T Bell Laboratories Method of manufacturing an integrated circuit including planarizing a wafer
US5276338A (en) * 1992-05-15 1994-01-04 International Business Machines Corporation Bonded wafer structure having a buried insulation layer
US5369304A (en) * 1992-08-14 1994-11-29 Motorola, Inc. Conductive diffusion barrier of titanium nitride in ohmic contact with a plurality of doped layers therefor
JPH0799295A (ja) * 1993-06-07 1995-04-11 Canon Inc 半導体基体の作成方法及び半導体基体
DE4333661C1 (de) * 1993-10-01 1995-02-16 Daimler Benz Ag Halbleiterbauelement mit hoher Durchbruchsspannung
EP0661735B1 (de) * 1993-12-29 2001-03-07 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno Verfahren zur Herstellung integrierter Schaltungen, insbesondere intelligenter Leistungsanordnungen
US6104078A (en) * 1994-03-09 2000-08-15 Denso Corporation Design for a semiconductor device having elements isolated by insulating regions
JPH07297377A (ja) * 1994-04-21 1995-11-10 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPH0837286A (ja) * 1994-07-21 1996-02-06 Toshiba Microelectron Corp 半導体基板および半導体基板の製造方法
JP2755185B2 (ja) * 1994-11-07 1998-05-20 日本電気株式会社 Ｓｏｉ基板
JPH08264643A (ja) * 1995-03-23 1996-10-11 Ube Ind Ltd 複合半導体基板
JP3378135B2 (ja) * 1996-02-02 2003-02-17 三菱電機株式会社 半導体装置とその製造方法
DE19741971A1 (de) * 1997-09-23 1999-04-01 Siemens Ag Verfahren zum Herstellen Direct-Wafer-Bond Si/Si02/Si-Substrate
JP4476390B2 (ja) * 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP4521542B2 (ja) * 1999-03-30 2010-08-11 ルネサスエレクトロニクス株式会社 半導体装置および半導体基板
US6465809B1 (en) 1999-06-09 2002-10-15 Kabushiki Kaisha Toshiba Bonding type semiconductor substrate, semiconductor light emitting element, and preparation process thereof
US6476462B2 (en) * 1999-12-28 2002-11-05 Texas Instruments Incorporated MOS-type semiconductor device and method for making same
EP1386349A1 (de) * 2001-04-17 2004-02-04 California Institute Of Technology Verfahren zur verwendung eines germaniumschichttransfers zu si für photovoltaische anwendungen und dadurch hergestellte heterostruktur
US6603916B1 (en) 2001-07-26 2003-08-05 Lightwave Microsystems Corporation Lightwave circuit assembly having low deformation balanced sandwich substrate
US7153757B2 (en) * 2002-08-29 2006-12-26 Analog Devices, Inc. Method for direct bonding two silicon wafers for minimising interfacial oxide and stresses at the bond interface, and an SOI structure
US7329923B2 (en) * 2003-06-17 2008-02-12 International Business Machines Corporation High-performance CMOS devices on hybrid crystal oriented substrates
US7023055B2 (en) * 2003-10-29 2006-04-04 International Business Machines Corporation CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding
TWI220415B (en) * 2003-11-04 2004-08-21 Benq Corp Fluid eject device and method of fabricating the same
US7186622B2 (en) * 2004-07-15 2007-03-06 Infineon Technologies Ag Formation of active area using semiconductor growth process without STI integration
US7298009B2 (en) * 2005-02-01 2007-11-20 Infineon Technologies Ag Semiconductor method and device with mixed orientation substrate
CN100468029C (zh) * 2005-03-03 2009-03-11 清华大学 标准漏孔及其制作方法
WO2006103491A1 (en) * 2005-03-29 2006-10-05 S.O.I.Tec Silicon On Insulator Technologies Hybrid fully soi-type multilayer structure
US8530355B2 (en) 2005-12-23 2013-09-10 Infineon Technologies Ag Mixed orientation semiconductor device and method
US20070190795A1 (en) * 2006-02-13 2007-08-16 Haoren Zhuang Method for fabricating a semiconductor device with a high-K dielectric
US7575988B2 (en) * 2006-07-11 2009-08-18 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating a hybrid substrate
FR2903808B1 (fr) * 2006-07-11 2008-11-28 Soitec Silicon On Insulator Procede de collage direct de deux substrats utilises en electronique, optique ou opto-electronique
JP5256625B2 (ja) * 2007-03-05 2013-08-07 株式会社Ｓｕｍｃｏ 貼り合わせウェーハの評価方法
KR101548173B1 (ko) * 2008-09-18 2015-08-31 삼성전자주식회사 실리콘 다이렉트 본딩(ｓｄｂ)을 이용한 임시 웨이퍼 임시 본딩 방법, 및 그 본딩 방법을 이용한 반도체 소자 및 반도체 소자 제조 방법
US8476146B2 (en) * 2010-12-03 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing wafer distortion through a low CTE layer
JP5853389B2 (ja) * 2011-03-28 2016-02-09 ソニー株式会社 半導体装置及び半導体装置の製造方法。
JP2013115307A (ja) * 2011-11-30 2013-06-10 Sumitomo Electric Ind Ltd Ｉｉｉ族窒化物複合基板の製造方法
US20140127857A1 (en) * 2012-11-07 2014-05-08 Taiwan Semiconductor Manufacturing Company, Ltd. Carrier Wafers, Methods of Manufacture Thereof, and Packaging Methods
JP6300662B2 (ja) 2014-06-20 2018-03-28 オリンパス株式会社 半導体装置および半導体装置の製造方法
DE212019000447U1 (de) 2019-01-16 2021-10-12 Murata Manufacturing Co., Ltd. Siliziumsubstrat mit einen Hohlraum sowie Hohlraum-SOI-Substrat, welches das Siliziumsubstrat umfasst

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0161740B1 (de) * 1984-05-09 1991-06-12 Kabushiki Kaisha Toshiba Verfahren zur Herstellung eines Halbleitersubstrates
JPH0618234B2 (ja) * 1985-04-19 1994-03-09 日本電信電話株式会社 半導体基板の接合方法
NL8501773A (nl) * 1985-06-20 1987-01-16 Philips Nv Werkwijze voor het vervaardigen van halfgeleiderinrichtingen.
JPS6276645A (ja) * 1985-09-30 1987-04-08 Toshiba Corp 複合半導体結晶体構造
JPS6276646A (ja) * 1985-09-30 1987-04-08 Toshiba Corp 半導体装置の製造方法
JPS62154614A (ja) * 1985-12-27 1987-07-09 Toshiba Corp 接合型半導体基板の製造方法
NL8600216A (nl) * 1986-01-30 1987-08-17 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting.
US4774196A (en) * 1987-08-25 1988-09-27 Siliconix Incorporated Method of bonding semiconductor wafers
JPH02122148A (ja) * 1988-10-31 1990-05-09 Toto Ltd 要求熱負荷小時の設定温度かさあげ機能を有する給湯機

Also Published As

Publication number Publication date
KR890015358A (ko) 1989-10-30
JP2685819B2 (ja) 1997-12-03
EP0335741B1 (de) 1995-08-23
DE68923894T2 (de) 1996-04-18
JPH01315159A (ja) 1989-12-20
EP0335741A2 (de) 1989-10-04
EP0335741A3 (de) 1991-01-30
KR920007333B1 (ko) 1992-08-31
US4878957A (en) 1989-11-07

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Legal Events

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8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)