DE102004028925A1 - Zwischenverbindungsstruktur mit Pseudo-Durchkontakten - Google Patents

Zwischenverbindungsstruktur mit Pseudo-Durchkontakten Download PDF

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Publication number
DE102004028925A1
DE102004028925A1 DE102004028925A DE102004028925A DE102004028925A1 DE 102004028925 A1 DE102004028925 A1 DE 102004028925A1 DE 102004028925 A DE102004028925 A DE 102004028925A DE 102004028925 A DE102004028925 A DE 102004028925A DE 102004028925 A1 DE102004028925 A1 DE 102004028925A1
Authority
DE
Germany
Prior art keywords
wirings
layer
interconnect structure
dummy vias
vias
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE102004028925A
Other languages
German (de)
English (en)
Inventor
Kazuo Tomita
Keiji Hashimoto
Yasutaka Nishioka
Susumu Matsumoto
Mitsuru Sekiguchi
Akihisa Iwasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Panasonic Holdings Corp
Original Assignee
Renesas Technology Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp, Matsushita Electric Industrial Co Ltd filed Critical Renesas Technology Corp
Publication of DE102004028925A1 publication Critical patent/DE102004028925A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE102004028925A 2003-08-12 2004-06-15 Zwischenverbindungsstruktur mit Pseudo-Durchkontakten Withdrawn DE102004028925A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003292166A JP2005064226A (ja) 2003-08-12 2003-08-12 配線構造

Publications (1)

Publication Number Publication Date
DE102004028925A1 true DE102004028925A1 (de) 2005-04-28

Family

ID=34131700

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102004028925A Withdrawn DE102004028925A1 (de) 2003-08-12 2004-06-15 Zwischenverbindungsstruktur mit Pseudo-Durchkontakten

Country Status (6)

Country Link
US (2) US20050035457A1 (https=)
JP (1) JP2005064226A (https=)
KR (2) KR20050018585A (https=)
CN (1) CN1581475B (https=)
DE (1) DE102004028925A1 (https=)
TW (1) TWI315542B (https=)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005183567A (ja) * 2003-12-18 2005-07-07 Matsushita Electric Ind Co Ltd 半導体集積回路の製造方法、ヴィアホール形成用共用マスクおよび半導体集積回路
US7420277B2 (en) * 2004-03-16 2008-09-02 Taiwan Semiconductor Manufacturing Company, Ltd System for heat dissipation in semiconductor devices
JP4794135B2 (ja) * 2004-04-16 2011-10-19 富士通株式会社 半導体装置の製造方法
JP4703129B2 (ja) * 2004-05-06 2011-06-15 富士通セミコンダクター株式会社 半導体装置およびその製造方法、設計方法
JPWO2006061871A1 (ja) * 2004-12-06 2008-06-05 富士通株式会社 半導体装置
US7545045B2 (en) * 2005-03-24 2009-06-09 Taiwan Semiconductor Manufacturing Co., Ltd. Dummy via for reducing proximity effect and method of using the same
JP5230061B2 (ja) * 2005-07-25 2013-07-10 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法
CN1988146A (zh) * 2005-12-22 2007-06-27 中芯国际集成电路制造(上海)有限公司 哑元图案和机械增强低k介电材料的制造方法
US20070287279A1 (en) * 2006-06-08 2007-12-13 Daubenspeck Timothy H Methods of forming solder connections and structure thereof
JP4825060B2 (ja) * 2006-06-14 2011-11-30 富士通セミコンダクター株式会社 露光方法
JP2008016638A (ja) * 2006-07-06 2008-01-24 Sony Corp 半導体装置
JP2008124070A (ja) * 2006-11-08 2008-05-29 Rohm Co Ltd 半導体装置
US7948094B2 (en) 2007-10-22 2011-05-24 Rohm Co., Ltd. Semiconductor device
US7951704B2 (en) * 2008-05-06 2011-05-31 Spansion Llc Memory device peripheral interconnects and method of manufacturing
US8669597B2 (en) 2008-05-06 2014-03-11 Spansion Llc Memory device interconnects and method of manufacturing
US8624398B2 (en) * 2009-08-26 2014-01-07 United Microelectronics Corp. Semiconductor circuit structure
JP2012148428A (ja) * 2011-01-17 2012-08-09 Toshiba Tec Corp インクジェットヘッドの製造方法
US8847393B2 (en) * 2011-02-28 2014-09-30 Freescale Semiconductor, Inc. Vias between conductive layers to improve reliability
CN102437105B (zh) * 2011-11-28 2014-08-13 上海华力微电子有限公司 具有部分冗余通孔的集成电路制作方法及集成电路
US20130155636A1 (en) * 2011-12-16 2013-06-20 Changyok Park Dummy through-silicon via capacitor
US8883638B2 (en) * 2012-01-18 2014-11-11 United Microelectronics Corp. Method for manufacturing damascene structure involving dummy via holes
US8629559B2 (en) * 2012-02-09 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Stress reduction apparatus with an inverted cup-shaped layer
US9343411B2 (en) * 2013-01-29 2016-05-17 Intel Corporation Techniques for enhancing fracture resistance of interconnects
FR3003962B1 (fr) * 2013-03-29 2016-07-22 St Microelectronics Rousset Procede d'elaboration d'un masque de photolitographie destine a la formation de contacts, masque et circuit integre correspondants
US9659860B2 (en) 2013-08-21 2017-05-23 Intel Corporation Method and structure to contact tight pitch conductive layers with guided vias
US9054164B1 (en) 2013-12-23 2015-06-09 Intel Corporation Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches
US9831214B2 (en) * 2014-06-18 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices
US10177032B2 (en) * 2014-06-18 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaging devices, and methods of packaging semiconductor devices
KR102326120B1 (ko) 2015-06-29 2021-11-15 삼성전자주식회사 배선 구조물 및 그 형성 방법, 및 상기 배선 구조물을 갖는 반도체 장치
KR102382826B1 (ko) 2015-09-08 2022-04-04 삼성전자주식회사 반도체 장치의 제조 방법
KR102521554B1 (ko) 2015-12-07 2023-04-13 삼성전자주식회사 배선 구조물, 배선 구조물 설계 방법, 및 배선 구조물 형성 방법
US20190109090A1 (en) * 2017-08-15 2019-04-11 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnection structure lined by isolation layer
US11705395B2 (en) * 2018-06-25 2023-07-18 Intel Corporation Core fill to reduce dishing and metal pillar fill to increase metal density of interconnects
KR102866394B1 (ko) 2020-07-01 2025-09-29 삼성전자주식회사 3차원 반도체 메모리 장치
US12593668B2 (en) * 2022-06-15 2026-03-31 International Business Machines Corporation Shallow and deep contacts with stitching

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5625232A (en) * 1994-07-15 1997-04-29 Texas Instruments Incorporated Reliability of metal leads in high speed LSI semiconductors using dummy vias
JPH11307633A (ja) * 1997-11-17 1999-11-05 Sony Corp 低誘電率膜を有する半導体装置、およびその製造方法
US5880018A (en) * 1996-10-07 1999-03-09 Motorola Inc. Method for manufacturing a low dielectric constant inter-level integrated circuit structure
TW353775B (en) * 1996-11-27 1999-03-01 Tokyo Electron Ltd Production of semiconductor device
JPH10199882A (ja) 1997-01-13 1998-07-31 Nec Corp 半導体装置
JP3442630B2 (ja) 1997-11-20 2003-09-02 株式会社日立製作所 半導体装置
TW368741B (en) * 1998-02-26 1999-09-01 United Microelectronics Corp Manufacturing method for dual damascene
JPH11297817A (ja) 1998-04-09 1999-10-29 Hitachi Ltd 半導体装置の製造方法およびその設計方法ならびに半導体装置
TW396524B (en) * 1998-06-26 2000-07-01 United Microelectronics Corp A method for fabricating dual damascene
US6225207B1 (en) * 1998-10-01 2001-05-01 Applied Materials, Inc. Techniques for triple and quadruple damascene fabrication
US6150272A (en) * 1998-11-16 2000-11-21 Taiwan Semiconductor Manufacturing Company Method for making metal plug contacts and metal lines in an insulating layer by chemical/mechanical polishing that reduces polishing-induced damage
JP3700460B2 (ja) * 1999-04-05 2005-09-28 セイコーエプソン株式会社 半導体装置およびその製造方法
US6281583B1 (en) * 1999-05-12 2001-08-28 International Business Machines Corporation Planar integrated circuit interconnect
US6329280B1 (en) 1999-05-13 2001-12-11 International Business Machines Corporation Interim oxidation of silsesquioxane dielectric for dual damascene process
JP2001053143A (ja) 1999-08-09 2001-02-23 Matsushita Electric Ind Co Ltd 半導体装置の製造方法と半導体装置
JP2001077543A (ja) * 1999-09-03 2001-03-23 Fujitsu Ltd 多層配線基板
US6365504B1 (en) * 1999-10-15 2002-04-02 Tsmc-Acer Semiconductor Manufacturing Corporation Self aligned dual damascene method
JP2001168093A (ja) 1999-12-09 2001-06-22 Sharp Corp 半導体装置
JP4251739B2 (ja) * 1999-12-27 2009-04-08 株式会社ルネサステクノロジ 半導体記憶装置
US6295721B1 (en) * 1999-12-28 2001-10-02 Taiwan Semiconductor Manufacturing Company Metal fuse in copper dual damascene
JP2001196372A (ja) 2000-01-13 2001-07-19 Mitsubishi Electric Corp 半導体装置
US6295222B2 (en) * 2000-01-28 2001-09-25 Mitsubishi Kabushiki Kaisha Semiconductor memory device with two layers of bit lines
US6812130B1 (en) * 2000-02-09 2004-11-02 Infineon Technologies Ag Self-aligned dual damascene etch using a polymer
JP2001230250A (ja) 2000-02-14 2001-08-24 Hitachi Ltd 半導体装置およびその製造方法並びにマスクパターンの生成方法
JP2001298081A (ja) 2000-04-12 2001-10-26 Nec Corp 半導体装置及びその製造方法
JP3818828B2 (ja) * 2000-06-05 2006-09-06 シャープ株式会社 半導体装置の製造方法
US6319809B1 (en) * 2000-07-12 2001-11-20 Taiwan Semiconductor Manfacturing Company Method to reduce via poison in low-k Cu dual damascene by UV-treatment
JP2002118235A (ja) * 2000-10-10 2002-04-19 Mitsubishi Electric Corp 半導体装置、半導体製造方法、および半導体製造用マスク
US6468894B1 (en) * 2001-03-21 2002-10-22 Advanced Micro Devices, Inc. Metal interconnection structure with dummy vias
JP4545973B2 (ja) 2001-03-23 2010-09-15 富士通株式会社 シリコン系組成物、低誘電率膜、半導体装置および低誘電率膜の製造方法
JP2002289687A (ja) * 2001-03-27 2002-10-04 Sony Corp 半導体装置、及び、半導体装置における配線形成方法
JP2002313908A (ja) 2001-04-12 2002-10-25 Mitsubishi Electric Corp 微細パターンの形成方法及び半導体装置の製造方法並びに半導体装置
JP4523194B2 (ja) * 2001-04-13 2010-08-11 富士通セミコンダクター株式会社 半導体装置とその製造方法
US6582974B2 (en) * 2001-11-15 2003-06-24 Taiwan Semiconductor Manufacturing Co., Ltd Method for forming a dual damascene aperture while employing a peripherally localized intermediate etch stop layer
JP4198906B2 (ja) 2001-11-15 2008-12-17 株式会社ルネサステクノロジ 半導体装置および半導体装置の製造方法
US6740940B2 (en) * 2001-11-27 2004-05-25 Samsung Electronics Co., Ltd. Semiconductor memory devices having dummy active regions
US6798073B2 (en) * 2001-12-13 2004-09-28 Megic Corporation Chip structure and process for forming the same
JP3790469B2 (ja) 2001-12-21 2006-06-28 富士通株式会社 半導体装置
US6818570B2 (en) * 2002-03-04 2004-11-16 Asm Japan K.K. Method of forming silicon-containing insulation film having low dielectric constant and high mechanical strength
US6593232B1 (en) * 2002-07-05 2003-07-15 Taiwan Semiconductor Manufacturing Co., Ltd Plasma etch method with enhanced endpoint detection
US6861686B2 (en) * 2003-01-16 2005-03-01 Samsung Electronics Co., Ltd. Structure of a CMOS image sensor and method for fabricating the same

Also Published As

Publication number Publication date
JP2005064226A (ja) 2005-03-10
US20070007658A1 (en) 2007-01-11
TW200507010A (en) 2005-02-16
CN1581475B (zh) 2010-05-26
KR20050018585A (ko) 2005-02-23
KR100770486B1 (ko) 2007-10-25
US20050035457A1 (en) 2005-02-17
CN1581475A (zh) 2005-02-16
US7605085B2 (en) 2009-10-20
TWI315542B (en) 2009-10-01
KR20060108601A (ko) 2006-10-18

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