TWI315542B - Interconnecting structure - Google Patents

Interconnecting structure

Info

Publication number
TWI315542B
TWI315542B TW093106028A TW93106028A TWI315542B TW I315542 B TWI315542 B TW I315542B TW 093106028 A TW093106028 A TW 093106028A TW 93106028 A TW93106028 A TW 93106028A TW I315542 B TWI315542 B TW I315542B
Authority
TW
Taiwan
Prior art keywords
interconnecting structure
interconnecting
Prior art date
Application number
TW093106028A
Other languages
English (en)
Other versions
TW200507010A (en
Inventor
Tomita Kazuo
Hashimoto Keiji
Nishioka Yasutaka
Matsumoto Susumu
Sekiguchi Mitsuru
Iwasaki Akihisa
Original Assignee
Renesas Tech Corp
Panasonic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Tech Corp, Panasonic Corp filed Critical Renesas Tech Corp
Publication of TW200507010A publication Critical patent/TW200507010A/zh
Application granted granted Critical
Publication of TWI315542B publication Critical patent/TWI315542B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
TW093106028A 2003-08-12 2004-03-08 Interconnecting structure TWI315542B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003292166A JP2005064226A (ja) 2003-08-12 2003-08-12 配線構造

Publications (2)

Publication Number Publication Date
TW200507010A TW200507010A (en) 2005-02-16
TWI315542B true TWI315542B (en) 2009-10-01

Family

ID=34131700

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093106028A TWI315542B (en) 2003-08-12 2004-03-08 Interconnecting structure

Country Status (6)

Country Link
US (2) US20050035457A1 (zh)
JP (1) JP2005064226A (zh)
KR (2) KR20050018585A (zh)
CN (1) CN1581475B (zh)
DE (1) DE102004028925A1 (zh)
TW (1) TWI315542B (zh)

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US8624398B2 (en) * 2009-08-26 2014-01-07 United Microelectronics Corp. Semiconductor circuit structure
JP2012148428A (ja) * 2011-01-17 2012-08-09 Toshiba Tec Corp インクジェットヘッドの製造方法
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US8883638B2 (en) * 2012-01-18 2014-11-11 United Microelectronics Corp. Method for manufacturing damascene structure involving dummy via holes
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WO2015026342A1 (en) * 2013-08-21 2015-02-26 Intel Corporation Method and structure to contact tight pitch conductive layers with guided vias
US9054164B1 (en) * 2013-12-23 2015-06-09 Intel Corporation Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches
US9831214B2 (en) * 2014-06-18 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices
US10177032B2 (en) * 2014-06-18 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaging devices, and methods of packaging semiconductor devices
KR102326120B1 (ko) * 2015-06-29 2021-11-15 삼성전자주식회사 배선 구조물 및 그 형성 방법, 및 상기 배선 구조물을 갖는 반도체 장치
KR102382826B1 (ko) 2015-09-08 2022-04-04 삼성전자주식회사 반도체 장치의 제조 방법
KR102521554B1 (ko) * 2015-12-07 2023-04-13 삼성전자주식회사 배선 구조물, 배선 구조물 설계 방법, 및 배선 구조물 형성 방법
US20190109090A1 (en) * 2017-08-15 2019-04-11 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnection structure lined by isolation layer
US11705395B2 (en) * 2018-06-25 2023-07-18 Intel Corporation Core fill to reduce dishing and metal pillar fill to increase metal density of interconnects
KR20220003359A (ko) 2020-07-01 2022-01-10 삼성전자주식회사 3차원 반도체 메모리 장치

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Also Published As

Publication number Publication date
US20070007658A1 (en) 2007-01-11
DE102004028925A1 (de) 2005-04-28
KR100770486B1 (ko) 2007-10-25
TW200507010A (en) 2005-02-16
JP2005064226A (ja) 2005-03-10
US7605085B2 (en) 2009-10-20
CN1581475A (zh) 2005-02-16
CN1581475B (zh) 2010-05-26
US20050035457A1 (en) 2005-02-17
KR20050018585A (ko) 2005-02-23
KR20060108601A (ko) 2006-10-18

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees