DE10142585B4 - Halbleiteranordnung und zugehöriges Verfahren zu deren Herstellung - Google Patents

Halbleiteranordnung und zugehöriges Verfahren zu deren Herstellung Download PDF

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Publication number
DE10142585B4
DE10142585B4 DE10142585A DE10142585A DE10142585B4 DE 10142585 B4 DE10142585 B4 DE 10142585B4 DE 10142585 A DE10142585 A DE 10142585A DE 10142585 A DE10142585 A DE 10142585A DE 10142585 B4 DE10142585 B4 DE 10142585B4
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DE
Germany
Prior art keywords
chip
semiconductor
section
semiconductor chip
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE10142585A
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German (de)
English (en)
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DE10142585A1 (de
Inventor
Shunichi Abe
Tetsuya Uebayashi
Naoki Izumi
Akira Yamazaki
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Renesas Electronics Corp
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Mitsubishi Electric Corp
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Filing date
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Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE10142585A1 publication Critical patent/DE10142585A1/de
Application granted granted Critical
Publication of DE10142585B4 publication Critical patent/DE10142585B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07352—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
DE10142585A 2001-02-08 2001-08-31 Halbleiteranordnung und zugehöriges Verfahren zu deren Herstellung Expired - Fee Related DE10142585B4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001032362A JP4637380B2 (ja) 2001-02-08 2001-02-08 半導体装置
JP2001-032362 2001-02-08

Publications (2)

Publication Number Publication Date
DE10142585A1 DE10142585A1 (de) 2002-09-05
DE10142585B4 true DE10142585B4 (de) 2007-08-09

Family

ID=18896308

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10142585A Expired - Fee Related DE10142585B4 (de) 2001-02-08 2001-08-31 Halbleiteranordnung und zugehöriges Verfahren zu deren Herstellung

Country Status (4)

Country Link
US (2) US6737736B2 (https=)
JP (1) JP4637380B2 (https=)
KR (1) KR100445501B1 (https=)
DE (1) DE10142585B4 (https=)

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US6843421B2 (en) * 2001-08-13 2005-01-18 Matrix Semiconductor, Inc. Molded memory module and method of making the module absent a substrate support
US6731011B2 (en) * 2002-02-19 2004-05-04 Matrix Semiconductor, Inc. Memory module having interconnected and stacked integrated circuits
JP2004071899A (ja) * 2002-08-07 2004-03-04 Sanyo Electric Co Ltd 回路装置およびその製造方法
US6667543B1 (en) * 2002-10-29 2003-12-23 Motorola, Inc. Optical sensor package
US6879028B2 (en) * 2003-02-21 2005-04-12 Freescale Semiconductor, Inc. Multi-die semiconductor package
FR2854495B1 (fr) * 2003-04-29 2005-12-02 St Microelectronics Sa Procede de fabrication d'un boitier semi-conducteur et boitier semi-conducteur a grille.
JP2006019652A (ja) * 2004-07-05 2006-01-19 Toshiba Corp 半導体装置
US20060056233A1 (en) * 2004-09-10 2006-03-16 Parkinson Ward D Using a phase change memory as a replacement for a buffered flash memory
JP4602223B2 (ja) * 2005-10-24 2010-12-22 株式会社東芝 半導体装置とそれを用いた半導体パッケージ
JP5217291B2 (ja) * 2006-08-04 2013-06-19 大日本印刷株式会社 樹脂封止型半導体装置とその製造方法、半導体装置用基材、および積層型樹脂封止型半導体装置
JP4918391B2 (ja) * 2007-04-16 2012-04-18 オンセミコンダクター・トレーディング・リミテッド 半導体装置
JP2010129848A (ja) * 2008-11-28 2010-06-10 Sanyo Electric Co Ltd 半導体装置
US8110440B2 (en) * 2009-05-18 2012-02-07 Stats Chippac, Ltd. Semiconductor device and method of forming overlapping semiconductor die with coplanar vertical interconnect structure
WO2011155165A1 (ja) * 2010-06-11 2011-12-15 パナソニック株式会社 樹脂封止型半導体装置及びその製造方法
DE102010047128A1 (de) * 2010-09-30 2012-04-05 Infineon Technologies Ag Hallsensoranordnung zum redundanten Messen eines Magnetfeldes
CN107845619B (zh) * 2011-07-22 2022-01-18 超大规模集成电路技术有限责任公司 堆叠式管芯半导体封装体
US9184114B2 (en) * 2012-09-07 2015-11-10 Eoplex Limited Lead carrier with print-formed terminal pads
JP2014207821A (ja) * 2013-04-15 2014-10-30 矢崎総業株式会社 電子部品及び電子部品の組付構造
US9275944B2 (en) * 2013-08-29 2016-03-01 Infineon Technologies Ag Semiconductor package with multi-level die block
US8952509B1 (en) * 2013-09-19 2015-02-10 Alpha & Omega Semiconductor, Inc. Stacked multi-chip bottom source semiconductor device and preparation method thereof
DE102014213217A1 (de) * 2014-07-08 2016-01-14 Continental Teves Ag & Co. Ohg Körperschallentkopplung an mit Geberfeldern arbeitenden Sensoren
JP6846225B2 (ja) * 2017-02-06 2021-03-24 ラピスセミコンダクタ株式会社 検査回路、半導体記憶素子、半導体装置、および接続検査方法
JP6780675B2 (ja) * 2017-07-24 2020-11-04 株式会社デンソー 半導体装置及び半導体装置の製造方法
WO2019021766A1 (ja) * 2017-07-24 2019-01-31 株式会社デンソー 半導体装置及び半導体装置の製造方法
JP7167721B2 (ja) * 2019-01-10 2022-11-09 株式会社デンソー 半導体装置およびその製造方法
CN118471867B (zh) * 2024-07-13 2024-09-24 中北大学 一种半导体封装测试装置及其测试方法

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JPH0521703A (ja) * 1991-07-11 1993-01-29 Mitsubishi Electric Corp 半導体装置
JPH05218295A (ja) * 1992-02-04 1993-08-27 Fujitsu Ltd 半導体装置
JP2000156464A (ja) * 1998-11-20 2000-06-06 Hitachi Ltd 半導体装置の製造方法
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JP2000269409A (ja) * 1999-03-16 2000-09-29 Nec Corp 半導体装置

Also Published As

Publication number Publication date
JP2002237565A (ja) 2002-08-23
US6965154B2 (en) 2005-11-15
DE10142585A1 (de) 2002-09-05
KR20020066366A (ko) 2002-08-16
US20040178490A1 (en) 2004-09-16
US6737736B2 (en) 2004-05-18
KR100445501B1 (ko) 2004-08-21
US20020105061A1 (en) 2002-08-08
JP4637380B2 (ja) 2011-02-23

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