CN1838328A - 擦除存储器阵列上存储单元的方法 - Google Patents
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- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
- G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
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- G11C2216/18—Flash erasure of all the cells in an array, sector or block simultaneously
Abstract
本发明提供了一种擦除存储器阵列上存储单元的方法,该方法包括向存储单元阵列的单元集合的比特施加擦除脉冲,并仅在被擦除的单元集合的一个子群上执行擦除校验操作,以检查存储单元阈电压(Vt)是否已经降低至一擦除校验(EV)电压水平。
Description
技术领域
本发明涉及对非易失存储器(NVM)阵列存储单元的操作,例如,编程和擦除,特别涉及减少对这些阵列的擦除脉冲和擦除校验操作的方法。
背景技术
目前,非易失存储器产品集成了对存储单元进行电子编程和擦除的能力。主要表现为,擦除操作不是在每个单元上逐一执行,而是在单元子群上执行,就像在编程操作期间正常执行一样。这意味着,直到最后(最慢)的单元完成擦除,擦除条件才施加于整个子群,即,校验是否超出预定的水平(擦除校验)。
集成了在擦除期间进行隧道增强热孔注入的存储器产品,如在NROM(氮化物只读存储器)技术中,要求晶体管结点高偏压以通过带到带隧道效应产生注入孔,如图1所示。必须控制电荷注入以保证适当的设备操作,因此步进和校验算法常被采用。在一个典型的算法中,以一特定的偏压注入电荷,其后进行一校验操作,以探测单元是否达到预设状态。如果未达到预设状态,就通过一更高的偏压启动更强的电荷注入,反之亦然。对隧道增强热孔注入来说,常要在存储器单元两面同时分别执行这一流程,其结果是更长的擦除时间和更低的执行效率。
在设备的使用寿命期间,特别是经过密集的循环(连续编程和擦除操作)之后,用以擦除NROM和类似NROM单元的电压就应增加。例如,图2是现有技术的一个典型实施例,表示循环之前和之后的NROM单元的擦除曲线。该曲线显示了擦除操作的退化,其中,每个循环之后,都要施加更高的电压来擦除单元。
图3是循环对擦除电压的不利影响的另一个实施例。特别地,图3表示出现有技术中基于NROM的存储器产品的擦除电压和步进计数,其为在一个设备上进行编程/擦除操作(循环计数)数量的函数。漏压(Vppd)增加至一特定电压值(如图中所示特定产品的最大允许电压7.1V),同时,脉冲数量也增加。在达到最大允许电压之后,电压水平变得稳定。
由于在产品测试初期就设定了初始擦除电压,在擦除操作中会逐步累积,这在产品使用周期的中后期就转化为低下的效率。
在现有技术中,曾经提出并尝试过很多措施来提高以孔注入为基础的擦除流程的效率。其中一种措施,以一高于最后一个脉冲的水平施加一额外的擦除脉冲,以保证完全擦除,提高可靠性。多个专利文件中均提及采用附加脉冲的方法,例如,美国专利6700818、美国专利申请20050117395和20050058005,这些专利或申请均已转让给本申请的受让人,本申请将参考其内容。
另一种措施是在两个连续的步骤之间采用大电压跨度。但这种方法可能导致操作可控性降低。还有一种措施是采用多种电压增幅。因为经常同时在多个单元上同时执行电荷注入,这种措施的原理是,可集成大电压跨度直至第一个单元集合体到达其目标,继以一个更小的电压跨度直至单元集合完成。
还有一种措施是在学习阶段中,据一先前的单元群或同样单元群的擦除操作确定一优先步电压水平,该电压水平施加在阵列的其余单元上,以便更快。另一种措施是,在产品分类时的第一个脉冲水平进行拨号。但是这种措施不能确保较短的脉冲计数时间开销。
另一种措施则采用多种校验水平。这样脉冲电压可以较快至一最终脉冲水平,但是这种措施要求更复杂的设计和更长的校验时间。另一种措施要求在脉冲应用/校验操作时,单元的两面交互进行。这种办法可使擦除效率双倍提高,但是可控性会降低。
另一种措施通过减少能量消耗采用增强的擦除并行机制。还有一种措施,如果足够多的单元擦除失败,则停止擦除校验。施加附加一个擦除脉冲之后,在第一次失效的地址继续进行擦除校验。但是,在上述所有现有技术中,擦除群中的所有单元必须通过几个擦除校验,包括在完成擦除操作之前,并联字线切换时间开销的损失。
发明内容
本发明提供一种擦除存储器阵列上的存储单元的比特和减少此类阵列的擦除脉冲及擦除校验操作的方法。本发明将在下文中详述,其涉及一种NVM阵列存储单元,特别涉及一种单比特、双比特、多比特和多电平NROM单元,其中擦除动作通常包括将比特的阈电压水平调整至一目标阈值,本发明不限于NROM阵列。
在一个实施例中,为减少擦除操作的总体时间,需要减少校验和切换时间,但不限于此。通过缩短孔注入脉冲间的校验操作,可以减少上述现有技术中的时问损失,从而充分提高产品执行效率。
按本发明的一个实施例提供的方法,可擦除存储器阵列上的存储单元,该方法包括向存储单元阵列的单元集合的所有比特施加擦除脉冲,并仅对被擦除的单元集合的一个子群执行擦除校验操作,以检查该存储单元的阈电压(Vt)是否降低至擦除校验(EV)电压水平,如果是,就对单元集合停止擦除操作,而不论是否对单元集合的其余部分进行了检查。
按本发明的一个实施例,只有单元集合的子群被校验完成了擦除,该单元集合才可被校验完成了擦除。
按本发明的一个实施例,对该子群进行擦除校验使其电平低于目标擦除校验电压水平更低,以保证即使没有对全部单元进行校验,整个单元集合仍被擦除。
按本发明的一个实施例,该方法可进一步包括将校验时间开销最小化。
按本发明的一个实施例,可在将该子群聚束至少量字线之后执行擦除校验操作,以进一步减少切换时间开销。
按本发明的另一个实施例,在读电平和擦除校验电平之间,或在读电平和擦除校验及编程校验电平之间,可增加一个设定的电平差。
按本发明的另一个实施例,该方法可进一步包括,向单元集合的两个或两个以上的子群施加擦除脉冲,但并不对所有的子群执行校验操作。
按本发明的一个实施例,该方法可进一步包括,保证一定量的比特达到设定电平,而且单元集合通过擦除校验的概率很高,而只需对单元的一个子群实际执行擦除校验。
按本发明的一个实施例,该方法可进一步包括,在完成擦除校验之后,另外施加擦除脉冲。
按本发明的一个实施例,完成擦除校验的该单元集合的子群可以在包括单元集合本身的单元集合的任何一个子群之间,有规律地、周期性地或随机地从一个擦除操作向另一个擦除操作改变。
附图说明
结合附图和下文的详细说明,可更好地理解本发明。
图1是现有技术中通过隧道效应增强热孔注入擦除NROM单元的简图;
图2是现有技术中典型的NROM单元在循环前后的擦除曲线,显示出擦除操作的退化;
图3是现有技术中以NROM为基础的存储器产品的擦除电压和步计数简图,该擦除电压和步计数是在装置上执行编程/擦除操作(循环计数)的数量的函数;
图4A和4B是按本发明的实施例,被分区为子部分的存储器阵列上的单元集合的实施例的简化示意图;
图4C是按照本发明的一个实施例,擦除非易失存储单元阵列上存储单元的比特的方法的简化流程图;
图5是按照本发明的一个实施例,阈电压在NROM阵列的子群上分布的简化图,该阈电压是子群规模的函数;
图6A是通过现有技术中,用传统方法擦除和编程单元的阈电压的统计分布简图;
图6B是按照本发明的一个实施例,擦除单元的阈电压的统计分布简图;
图7A是按照本发明的一个实施例,被编程擦除的单元集合的示意简图,图中余量损失因单元集合的子群之间的不匹配而引起;
图7B是按照本发明的一个实施例,补偿因单元集合的子群之间的不匹配而引起的余量损失的流程图;
图8是按照本发明的一个实施例,被编程的NROM单元的两个子群之间的阈电压分布的
实施例的简化图。
具体实施方式
为对单元集合分区而使用了一些术语,参照图4A和4B可以更好理解这些术语,前述两图是按照本发明的一个实施例,在被分区成子部分的存储器阵列上的单元集合的实施例。图4A是在被分区成子部分12(本案中通过DQ)的存储器阵列上的单元集合10的一个实施例,和一个将被擦除校验(而不是对整个单元集合)的子群14,包括所有子部分12上的单元,下文将对此详述。子部分12和子群14可为任何形式。图4B是将单元集合10分区成子部分。在此例中,通过字线将单元集合10分区成子单元16。
参考图4C,该图是按照本发明的一个实施例,擦除非易失存储单元阵列上存储单元的比特的方法。
可选择一个擦除脉冲来擦除单元的比特,包括选择(拨入)一个负的栅压(Vg或Vcvpn-来自电荷激励的电压)和一个正的漏压(Vppd)(步骤401)。电压值的典型范围如下,Vg从-3V到-7V,Vppd从3V到7V,但不限于此,其持续时间为100-1000微秒。其后则可向单元集合施加擦除脉冲(步骤402)。
按本发明的一个实施例,不是对整个单元集合,而是对单元集合的一个被擦除的子群进行擦除校验操作(步骤403)。通过擦除校验操作检查存储单元阈电压(Vt)是否低于擦除校验(EV)电压水平。该单元集合的子群在典型意义上可包括存储单元集合的所有子部分中的单元,其通过应用体系结构来定义,例如连接到不同的读出放大器(参照子部分DQ)的物理阵列切片。
如果被擦除的单元集合的被校验的子群上的子部分单元均未通过擦除校验,就通过一个强(例如,大)增量设定一个新的Vppd电平(拨入)(步骤404)。如果有子部分通过擦除校验,就通过一个弱(例如,相对较小的)增量设定一个新的Vppd电平(步骤405)。直到来自子群的所有单元通过擦除校验(通过EV),才可向单元集合的子部分施加擦除脉冲,该子群属于被校验的子群(步骤406)。一旦子群中的所有单元均通过擦除校验,就结束擦除操作,而不再检查单元集合的其他子群(步骤407)。当然也可对剩余的子群进行检查以确认其已确实被擦除(步骤408)。尽管如此,单元集合仍可能接收到一个比最后一个脉冲的电平更高的擦除脉冲以确保完全擦除,提高可靠性,例如,在美国专利6700818和美国专利申请20050117395及20050058005中即是如此。正常情况下,应按单元集合的子部分来向单元集施加该额外脉冲,例如,基于使得DQ通过擦除校验的(或者那些实际通过校验的单元)擦除脉冲电平,而向不同的DQ施加脉冲。
这样校验操作的数量就可减少,且可更快完成擦除操作。此外,如果子群限制在包括被擦除的单元集合的全部字线中的少数几个字线上,切换时间开销(从0V到校验栅压,然后返回)也可大幅减少。
进行擦除校验的单元集合的子群可在包括单元集合本身的所有子群之间,从一个擦除操作到另一个擦除操作,有规律地、周期性地或随机地轮替。
这种部分校验方案依赖于被擦除地单元集合的均匀性方能成功。例如,参照图5,该图是在一个NROM阵列的子群的阈电压分布,其为子群规模的函数。图中是一个基本一致的实施例,其中所有的单元和单元之间的变化实际上是随机的,其分布为高斯分布。这就可以把子群的擦除速度(要求能擦除该子群中最慢的单元)和整个单元集合的擦除速度关联起来。也就是说,可以在这样一个单元子群上进行擦除校验,而无需在全部单元上进行擦除校验。但是,因为擦除校验并没有在所有单元上执行,在执行擦除校验的子群和其他单元之间存在某种不匹配现象,其详如下。
参照图6A和6B。图6A是通过现有技术中的传统方法进行擦除和编程的单元的阈电压的统计分布。被擦除单元具有高斯分布,其中所有单元均低于擦除校验电平(曲线A)。类似地,被编程单元可以具有高斯分布,其中所有单元均高于编程校验电平(曲线B)。
相反,图6B是按照本发明提供的方法擦除的单元的阈电压统计分布图(曲线C)。如上所述,因为没有在所有的单元上执行擦除校验,在执行过擦除校验的子群和其他单元之间存在某些不匹配。不匹配的原因是单元阈电压分布的统计特性。如果被擦除的比特数量增加,阈电压分布就会变得更宽(如,曲线C就比曲线A宽)。这意味着,单个比特超出其周围子群的分布的可能性增加。该不匹配可使得某些单元不能达到擦除校验电平(曲线C的右半部分在擦除校验电平之上)。
参考图7A和7B。为解决这种不匹配,在产品操作窗口中,要在擦除电平和读电平之间设定一个额外的差值。编程校验电平则任意改变,但其与读电平之间的差值不能减小。可额外或选择采用附加脉冲机制(如在美国专利6700818,和美国专利申请20050117395及20050058005中,或背景技术部分中提及的其他技术),并将其设定为一个更强的值,以确保所有单元均低于擦除校验电平,即,完全擦除。如前所述,另一种选择是把子群聚束成更少的字线以进一步减少切换时间开销。
如果在存储器阵列中存在固定的差异,可以通过将擦除操作分区成子群来处理,以将其在单元擦除中最小化。相应地,阵列集上的单元的动态将更为一致(如,在循环后保持不变)。但是,既然不匹配的子群需要被单独校验,额外的分区就需要额外的擦除校验操作。尽管如此,也不必对所有单元进行校验。
由于本发明提供的擦除校验方案是基于统计学规律的,因此可以忽略概率分布的“噪声边缘”以提高精度。参考图8,该图是同一阵列的被编程的NROM单元上具有同样历史记录的两个子群的阈电压分布图。该分布的叠加程度很高,但仍存在具有最低阈电压的单元,这些单元决定可正确读出单元内容的读操作的最高参考电平,其电压偏差为200mV(在5.45V和5.65V)。但是,如果应用了某电平,其使得至少八个比特不能被正确读出(在此情形下,被读出的被编程比特被擦除了),两个子群之间的电平差即为50mV(5.65V和5.75V)。当然,使用八比特作为触发机制,仅仅是一个实施例,本发明不限于此。相应地,本发明的擦除校验机制可使得数量为X的比特(X>1;例如,一般是X=8)通过一个预设电平,从而大幅度减小噪声分布散乱,并使得整个单元集合完全被擦除(通过擦除校验)的可能性极大,即使实际上只在单元子群上进行过校验。
虽然前面结合一些特定实施例对本发明进行了阐述,但很明显,本领域的技术人员在此还可以有很多其他选择、修正和变化。相应地,本发明包含所有这类选择、修正和变化。
Claims (11)
1、一种擦除存储器阵列上存储单元的方法,该方法包括:
对存储器阵列上的单元集合的比特施加擦除脉冲,并仅对被擦除的单元集合的一个子群进行擦除校验操作,以检查存储单元阈电压(Vt)是否降低至擦除校验(EV)电压水平,如果是,则停止向单元集合施加擦除脉冲。
2、根据权利要求1所述的方法,其中,仅在对该子群进行擦除校验后才完成整个单元集合的擦除校验。
3、根据权利要求1所述的方法,其中,对该子群进行擦除校验使其电平低于目标擦除校验电压水平,以保证即使没有对全部单元进行校验,整个单元集合仍被擦除。
4、根据权利要求1所述的方法,其中,还包括将校验时间开销最小化。
5、根据权利要求1所述的方法,其中,在将所述子群聚束至少量字线后执行擦除校验操作,以进一步减少切换时间开销。
6、根据权利要求1所述的方法,其中,还包括在读电平和擦除校验电平间增加一设定差值。
7、根据权利要求1所述的方法,其中,还包括在读电平和擦除校验电平及编程校验电平间增加一设定差值。
8、根据权利要求1所述的方法,其中,还包括向所述单元集合的两个或两个以上子群施加擦除脉冲,但不对所有所述子群执行擦除校验操作。
9、根据权利要求1所述的方法,其中,还包括确保一定数量的比特通过一设定电平,并使得整个单元集合通过擦除校验的可能性提高,即使只对单元的一个子群进行实际上的校验。
10、根据权利要求1所述的方法,其中,还包括在完成擦除校验后施加额外擦除脉冲。
11、根据权利要求1所述的方法,其中,该被擦除校验的单元集合的子群可以在包括单元集合的子群之间,从一个擦除操作到另一擦除操作,有规律地、周期性地或随机地轮替。
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- 2006-01-18 EP EP06100526A patent/EP1684308A1/en not_active Withdrawn
- 2006-01-18 EP EP06100507A patent/EP1686592A3/en not_active Withdrawn
- 2006-01-18 CN CNA2006100059975A patent/CN1838323A/zh active Pending
- 2006-01-18 EP EP06100524A patent/EP1684307A1/en not_active Withdrawn
- 2006-01-18 CN CNA2006100059960A patent/CN1838328A/zh active Pending
- 2006-01-19 US US11/335,316 patent/US20060181934A1/en not_active Abandoned
- 2006-01-19 CN CNA2006100054168A patent/CN1822233A/zh active Pending
- 2006-01-19 US US11/335,321 patent/US7468926B2/en not_active Expired - Fee Related
- 2006-01-19 JP JP2006010819A patent/JP2006228407A/ja active Pending
- 2006-01-19 JP JP2006010811A patent/JP2006228406A/ja active Pending
- 2006-01-19 JP JP2006010810A patent/JP2006228405A/ja active Pending
- 2006-01-19 US US11/335,318 patent/US7369440B2/en active Active
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN102385918A (zh) * | 2010-08-26 | 2012-03-21 | 三星电子株式会社 | 非易失性存储器件、其操作方法以及包括其的存储系统 |
CN102385918B (zh) * | 2010-08-26 | 2017-04-12 | 三星电子株式会社 | 非易失性存储器件、其操作方法以及包括其的存储系统 |
CN110838329A (zh) * | 2018-08-17 | 2020-02-25 | 北京兆易创新科技股份有限公司 | 一种存储器的擦除方法和系统 |
CN110838329B (zh) * | 2018-08-17 | 2022-04-01 | 北京兆易创新科技股份有限公司 | 一种存储器的擦除方法和系统 |
Also Published As
Publication number | Publication date |
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JP2006228407A (ja) | 2006-08-31 |
CN1822233A (zh) | 2006-08-23 |
US20060158940A1 (en) | 2006-07-20 |
EP1684308A1 (en) | 2006-07-26 |
US7468926B2 (en) | 2008-12-23 |
EP1686592A3 (en) | 2007-04-25 |
JP2006228405A (ja) | 2006-08-31 |
CN1838323A (zh) | 2006-09-27 |
JP2006228406A (ja) | 2006-08-31 |
US20060181934A1 (en) | 2006-08-17 |
US7369440B2 (en) | 2008-05-06 |
EP1686592A2 (en) | 2006-08-02 |
EP1684307A1 (en) | 2006-07-26 |
US20060158938A1 (en) | 2006-07-20 |
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