ITRM20010556A1 - Decodificatore per decodificare i comandi di commutazione a modo di test di circuiti integrati. - Google Patents
Decodificatore per decodificare i comandi di commutazione a modo di test di circuiti integrati.Info
- Publication number
- ITRM20010556A1 ITRM20010556A1 IT2001RM000556A ITRM20010556A ITRM20010556A1 IT RM20010556 A1 ITRM20010556 A1 IT RM20010556A1 IT 2001RM000556 A IT2001RM000556 A IT 2001RM000556A IT RM20010556 A ITRM20010556 A IT RM20010556A IT RM20010556 A1 ITRM20010556 A1 IT RM20010556A1
- Authority
- IT
- Italy
- Prior art keywords
- decoder
- integrated circuit
- test mode
- circuit test
- switching commands
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/46—Test trigger logic
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Semiconductor Memories (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT2001RM000556A ITRM20010556A1 (it) | 2001-09-12 | 2001-09-12 | Decodificatore per decodificare i comandi di commutazione a modo di test di circuiti integrati. |
US10/192,334 US6785162B2 (en) | 2001-09-12 | 2002-07-10 | Test mode decoder in a flash memory |
US10/880,894 US6977410B2 (en) | 2001-09-12 | 2004-06-30 | Test mode decoder in a flash memory |
US11/216,263 US20050280072A1 (en) | 2001-09-12 | 2005-08-31 | Test mode decoder in a flash memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT2001RM000556A ITRM20010556A1 (it) | 2001-09-12 | 2001-09-12 | Decodificatore per decodificare i comandi di commutazione a modo di test di circuiti integrati. |
Publications (2)
Publication Number | Publication Date |
---|---|
ITRM20010556A0 ITRM20010556A0 (it) | 2001-09-12 |
ITRM20010556A1 true ITRM20010556A1 (it) | 2003-03-12 |
Family
ID=11455777
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT2001RM000556A ITRM20010556A1 (it) | 2001-09-12 | 2001-09-12 | Decodificatore per decodificare i comandi di commutazione a modo di test di circuiti integrati. |
Country Status (2)
Country | Link |
---|---|
US (3) | US6785162B2 (it) |
IT (1) | ITRM20010556A1 (it) |
Families Citing this family (19)
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US5710906A (en) * | 1995-07-07 | 1998-01-20 | Opti Inc. | Predictive snooping of cache memory for master-initiated accesses |
US6877000B2 (en) * | 2001-08-22 | 2005-04-05 | International Business Machines Corporation | Tool for converting SQL queries into portable ODBC |
ITRM20010556A1 (it) * | 2001-09-12 | 2003-03-12 | Micron Technology Inc | Decodificatore per decodificare i comandi di commutazione a modo di test di circuiti integrati. |
US7178004B2 (en) | 2003-01-31 | 2007-02-13 | Yan Polansky | Memory array programming circuit and a method for using the circuit |
US6856556B1 (en) * | 2003-04-03 | 2005-02-15 | Siliconsystems, Inc. | Storage subsystem with embedded circuit for protecting against anomalies in power signal from host |
US7447847B2 (en) * | 2004-07-19 | 2008-11-04 | Micron Technology, Inc. | Memory device trims |
DE602004032455D1 (de) * | 2004-12-15 | 2011-06-09 | St Microelectronics Srl | Ein nichtflüchtiger Speicher mit Unterstützung von hochparallelem Test auf Waferebene |
EP1684308A1 (en) * | 2005-01-19 | 2006-07-26 | Saifun Semiconductors Ltd. | Methods for preventing fixed pattern programming |
ITMI20050799A1 (it) * | 2005-05-03 | 2006-11-04 | Atmel Corp | Metodo e sistema di configurazione dei parametri per una memoria flash |
KR101100891B1 (ko) * | 2005-05-23 | 2012-01-02 | 삼성전자주식회사 | 박막트랜지스터 기판 및 이를 포함한 디스플레이장치 |
US7808818B2 (en) | 2006-01-12 | 2010-10-05 | Saifun Semiconductors Ltd. | Secondary injection for NROM |
US8607111B2 (en) * | 2006-08-30 | 2013-12-10 | Micron Technology, Inc. | Sub-instruction repeats for algorithmic pattern generators |
US7646645B2 (en) * | 2007-04-13 | 2010-01-12 | Atmel Corporation | Method and apparatus for testing the functionality of a page decoder |
KR101571763B1 (ko) * | 2008-07-07 | 2015-12-07 | 삼성전자주식회사 | 적응적 제어 스킴을 가지는 메모리 장치 및 그 동작 방법 |
US8144517B2 (en) * | 2008-02-22 | 2012-03-27 | Samsung Electronics Co., Ltd. | Multilayered nonvolatile memory with adaptive control |
US7733712B1 (en) | 2008-05-20 | 2010-06-08 | Siliconsystems, Inc. | Storage subsystem with embedded circuit for protecting against anomalies in power signal from host |
KR102106588B1 (ko) * | 2013-10-28 | 2020-05-04 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 그것을 포함하는 데이터 저장 장치 |
US9859286B2 (en) | 2014-12-23 | 2018-01-02 | International Business Machines Corporation | Low-drive current FinFET structure for improving circuit density of ratioed logic in SRAM devices |
US10547325B2 (en) * | 2018-08-16 | 2020-01-28 | Intel Corporation Intel IP Corporation | Area efficient decompression acceleration |
Family Cites Families (40)
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US4460982A (en) * | 1982-05-20 | 1984-07-17 | Intel Corporation | Intelligent electrically programmable and electrically erasable ROM |
US4571704A (en) * | 1984-02-17 | 1986-02-18 | Hughes Aircraft Company | Nonvolatile latch |
US4858185A (en) * | 1988-01-28 | 1989-08-15 | National Semiconductor Corporation | Zero power, electrically alterable, nonvolatile latch |
US5031142A (en) * | 1989-02-10 | 1991-07-09 | Intel Corporation | Reset circuit for redundant memory using CAM cells |
JP2829156B2 (ja) * | 1991-07-25 | 1998-11-25 | 株式会社東芝 | 不揮発性半導体記憶装置の冗長回路 |
US5411908A (en) * | 1992-05-28 | 1995-05-02 | Texas Instruments Incorporated | Flash EEPROM array with P-tank insulated from substrate by deep N-tank |
US5526364A (en) * | 1995-02-10 | 1996-06-11 | Micron Quantum Devices, Inc. | Apparatus for entering and executing test mode operations for memory |
US5627784A (en) * | 1995-07-28 | 1997-05-06 | Micron Quantum Devices, Inc. | Memory system having non-volatile data storage structure for memory control parameters and method |
US5619453A (en) * | 1995-07-28 | 1997-04-08 | Micron Quantum Devices, Inc. | Memory system having programmable flow control register |
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US5675540A (en) * | 1996-01-22 | 1997-10-07 | Micron Quantum Devices, Inc. | Non-volatile memory system having internal data verification test mode |
US5661690A (en) * | 1996-02-27 | 1997-08-26 | Micron Quantum Devices, Inc. | Circuit and method for performing tests on memory array cells using external sense amplifier reference current |
US6392948B1 (en) * | 1996-08-29 | 2002-05-21 | Micron Technology, Inc. | Semiconductor device with self refresh test mode |
US5734661A (en) * | 1996-09-20 | 1998-03-31 | Micron Technology, Inc. | Method and apparatus for providing external access to internal integrated circuit test circuits |
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US5991904A (en) * | 1997-02-28 | 1999-11-23 | Micron Technology, Inc. | Method and apparatus for rapidly testing memory devices |
US5822258A (en) * | 1997-05-05 | 1998-10-13 | Micron Technology, Inc. | Circuit and method for testing a memory device with a cell plate generator having a variable current |
US6003149A (en) * | 1997-08-22 | 1999-12-14 | Micron Technology, Inc. | Test method and apparatus for writing a memory array with a reduced number of cycles |
US6161204A (en) * | 1998-02-17 | 2000-12-12 | Micron Technology, Inc. | Method and apparatus for testing SRAM memory cells |
US6058056A (en) * | 1998-04-30 | 2000-05-02 | Micron Technology, Inc. | Data compression circuit and method for testing memory devices |
US6163863A (en) * | 1998-05-22 | 2000-12-19 | Micron Technology, Inc. | Method and circuit for compressing test data in a memory device |
US6178532B1 (en) * | 1998-06-11 | 2001-01-23 | Micron Technology, Inc. | On-chip circuit and method for testing memory devices |
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US6331950B1 (en) * | 1999-10-19 | 2001-12-18 | Fujitsu Limited | Write protect input implementation for a simultaneous operation flash memory device |
US6628142B1 (en) * | 2000-08-30 | 2003-09-30 | Micron Technology, Inc. | Enhanced protection for input buffers of low-voltage flash memories |
ITRM20010298A1 (it) * | 2001-05-31 | 2002-12-02 | Micron Technology Inc | Interfaccia di comando di utilizzatore con decodificatore programmabile. |
ITRM20010105A1 (it) * | 2001-02-27 | 2002-08-27 | Micron Technology Inc | Circuito a fusibile per una cella di memoria flash. |
US6614689B2 (en) * | 2001-08-13 | 2003-09-02 | Micron Technology, Inc. | Non-volatile memory having a control mini-array |
US6754108B2 (en) * | 2001-08-30 | 2004-06-22 | Micron Technology, Inc. | DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators |
ITRM20010530A1 (it) * | 2001-08-31 | 2003-02-28 | Micron Technology Inc | Marcatura di settore di memoria flash per consecutiva cancellazione in settore o banco. |
ITRM20010529A1 (it) * | 2001-08-31 | 2003-02-28 | Micron Technology Inc | Interfaccia di utilizzatore di comando per memoria a ripartizione multipla. |
ITRM20010556A1 (it) * | 2001-09-12 | 2003-03-12 | Micron Technology Inc | Decodificatore per decodificare i comandi di commutazione a modo di test di circuiti integrati. |
DE10148403A1 (de) * | 2001-09-29 | 2003-04-17 | Fev Motorentech Gmbh | Verfahren zur Steuerung eines elektromagnetischen Ventiltriebs durch Änderung der Stromrichtung bei der Bestromung der Elektromagneten |
US6678205B2 (en) * | 2001-12-26 | 2004-01-13 | Micron Technology, Inc. | Multi-mode synchronous memory device and method of operating and testing same |
-
2001
- 2001-09-12 IT IT2001RM000556A patent/ITRM20010556A1/it unknown
-
2002
- 2002-07-10 US US10/192,334 patent/US6785162B2/en not_active Expired - Lifetime
-
2004
- 2004-06-30 US US10/880,894 patent/US6977410B2/en not_active Expired - Fee Related
-
2005
- 2005-08-31 US US11/216,263 patent/US20050280072A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
ITRM20010556A0 (it) | 2001-09-12 |
US20050280072A1 (en) | 2005-12-22 |
US20030048673A1 (en) | 2003-03-13 |
US6977410B2 (en) | 2005-12-20 |
US6785162B2 (en) | 2004-08-31 |
US20040246773A1 (en) | 2004-12-09 |
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