DE602004032455D1 - Ein nichtflüchtiger Speicher mit Unterstützung von hochparallelem Test auf Waferebene - Google Patents

Ein nichtflüchtiger Speicher mit Unterstützung von hochparallelem Test auf Waferebene

Info

Publication number
DE602004032455D1
DE602004032455D1 DE602004032455T DE602004032455T DE602004032455D1 DE 602004032455 D1 DE602004032455 D1 DE 602004032455D1 DE 602004032455 T DE602004032455 T DE 602004032455T DE 602004032455 T DE602004032455 T DE 602004032455T DE 602004032455 D1 DE602004032455 D1 DE 602004032455D1
Authority
DE
Germany
Prior art keywords
nonvolatile memory
level test
highly parallel
memory supported
parallel wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004032455T
Other languages
English (en)
Inventor
Guido Lomazzi
Ilaria Renna
Marco Maccarrone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
SK Hynix Inc
Original Assignee
STMicroelectronics SRL
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL, Hynix Semiconductor Inc filed Critical STMicroelectronics SRL
Publication of DE602004032455D1 publication Critical patent/DE602004032455D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G11C29/16—Implementation of control logic, e.g. test mode decoders using microprogrammed units, e.g. state machines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46—Test trigger logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G11C2029/2602—Concurrent test
DE602004032455T 2004-12-15 2004-12-15 Ein nichtflüchtiger Speicher mit Unterstützung von hochparallelem Test auf Waferebene Active DE602004032455D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP04106609A EP1672647B1 (de) 2004-12-15 2004-12-15 Ein nichtflüchtiger Speicher mit Unterstützung von hochparallelem Test auf Waferebene

Publications (1)

Publication Number Publication Date
DE602004032455D1 true DE602004032455D1 (de) 2011-06-09

Family

ID=34930062

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004032455T Active DE602004032455D1 (de) 2004-12-15 2004-12-15 Ein nichtflüchtiger Speicher mit Unterstützung von hochparallelem Test auf Waferebene

Country Status (3)

Country Link
US (1) US20060161825A1 (de)
EP (1) EP1672647B1 (de)
DE (1) DE602004032455D1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1402434B1 (it) * 2010-06-10 2013-09-04 St Microelectronics Srl Struttura di rilevamento dell'allineamento di una sonda atta a testare circuiti integrati
US9036427B2 (en) * 2013-06-12 2015-05-19 Arm Limited Apparatus and a method for erasing data stored in a memory device
CN112530511B (zh) * 2020-12-29 2023-06-23 芯天下技术股份有限公司 非易失型芯片内部单步测试方法、装置、存储介质、终端
CN113436671B (zh) * 2021-06-30 2023-09-08 芯天下技术股份有限公司 Spi nor flash测试平台、测试方法、测试装置和电子设备

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62140299A (ja) * 1985-12-13 1987-06-23 Advantest Corp パタ−ン発生装置
JP2716906B2 (ja) * 1992-03-27 1998-02-18 株式会社東芝 不揮発性半導体記憶装置
DE4308441A1 (de) * 1993-03-17 1994-09-22 Thomson Brandt Gmbh Verfahren und Vorrichtung zur Fernbedienung
US5440516A (en) * 1994-01-27 1995-08-08 Sgs-Thomson Microelectronics, Inc. Testing circuitry of internal peripheral blocks in a semiconductor memory device and method of testing the same
US6005814A (en) * 1998-04-03 1999-12-21 Cypress Semiconductor Corporation Test mode entrance through clocked addresses
US6429479B1 (en) * 2000-03-09 2002-08-06 Advanced Micro Devices, Inc. Nand flash memory with specified gate oxide thickness
KR100347069B1 (ko) * 2000-07-13 2002-08-03 삼성전자 주식회사 테스트기능을 가진 불휘발성 반도체메모리장치
JP2002033363A (ja) * 2000-07-19 2002-01-31 Hitachi Ltd 半導体ウエハ、半導体チップ、および半導体装置の製造方法
US20020174394A1 (en) * 2001-05-16 2002-11-21 Ledford James S. External control of algorithm execution in a built-in self-test circuit and method therefor
US6433628B1 (en) * 2001-05-17 2002-08-13 Agere Systems Guardian Corp. Wafer testable integrated circuit
ITRM20010556A1 (it) * 2001-09-12 2003-03-12 Micron Technology Inc Decodificatore per decodificare i comandi di commutazione a modo di test di circuiti integrati.
JP2003157699A (ja) * 2001-11-20 2003-05-30 Oki Electric Ind Co Ltd 半導体記憶装置
JP2003233999A (ja) * 2002-02-07 2003-08-22 Hitachi Ltd 半導体集積回路及び半導体集積回路の製造方法

Also Published As

Publication number Publication date
EP1672647A1 (de) 2006-06-21
EP1672647B1 (de) 2011-04-27
US20060161825A1 (en) 2006-07-20

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