CN111092083A - 包含铁电材料的凹陷晶体管 - Google Patents

包含铁电材料的凹陷晶体管 Download PDF

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CN111092083A
CN111092083A CN201911294882.6A CN201911294882A CN111092083A CN 111092083 A CN111092083 A CN 111092083A CN 201911294882 A CN201911294882 A CN 201911294882A CN 111092083 A CN111092083 A CN 111092083A
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conductive
ferroelectric
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insulating
conductive structure
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D·V·N·拉马斯瓦米
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Micron Technology Inc
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Abstract

本申请涉及包含铁电材料的凹陷晶体管。一些实施例含括晶体管构造，其具有内衬在基底内的凹槽中的第一绝缘结构。第一导电结构内衬在所述第一绝缘结构的内部中，且铁电结构内衬在所述第一导电结构的内部中。第二导电结构位于所述铁电结构的下部区域内，且所述第二导电结构具有在所述第一导电结构的最上表面下方的最上表面。第二绝缘结构位于所述第二导电结构上方且位于所述铁电结构内。一对源极/漏极区域相邻于所述第一绝缘结构的上部区域且位于所述第一绝缘结构的彼此对置侧上。

Description

包含铁电材料的凹陷晶体管
本申请为发明名称为“包含铁电材料的凹陷晶体管”、申请号为201580054326.5、申请日为2015年7月8日的中国发明专利申请的分案申请。
技术领域
本申请涉及包含铁电材料的凹陷晶体管。
背景技术
存储器是一种类型的集成电路，且用于计算机系统中以存储数据。可将存储器制造成一或多个个别存储器单元阵列。可使用数字线(其也可称为位线、数据线、感测线或数据/感测线)及访问线(其也可称为字线)而使存储器单元被写入或被读取。数字线可沿着阵列的列导电性地互连存储器单元，且访问线可沿着阵列的行导电性地互连存储器单元。可透过数字线与访问线的组合唯一地寻址每一存储器单元。
存储器单元可为易失性或非易失性。非易失性存储器单元可长期(含括计算机断电时)存储数据。易失性存储器具耗散性且因此需要被刷新/重新写入，在许多例项中，每秒刷新/重新写入多次。然而，存储器单元经配置以在至少两种不同可选状态中保存或存储记忆。在二进制系统中，将所述状态视为“0”或“1”。在其它系统中，至少一些个别存储器单元可经配置以存储信息的多于两种层次或状态。
场效晶体管是一种可用于存储器单元中的类型的电子组件。这些晶体管包括其间具有半导体沟道区域的一对导电源极/漏极区域。导电栅极相邻于沟道区域且通过薄栅极绝缘体与沟道区域分离。将合适电压施加于栅极允许电流从源极/漏极区域中的一者流动通过沟道区域到另一者。当从栅极移除电压时，大大防止电流流动通过沟道区域。场效晶体管还可含括额外结构(例如可逆可编程电荷存储区域)作为栅极构造的部分。另外或替代地，除场效晶体管外的晶体管(例如双极晶体管)可用于存储器单元中。晶体管可用于许多类型的存储器中。此外，晶体管可用于及形成于除存储器外的阵列中。
一种类型的晶体管是铁电场效晶体管(FeFET)，其中栅极构造的至少某个部分包括铁电材料。此材料以两个稳定极化状态为特征。场效晶体管中的这些不同状态可以晶体管的不同阈值电压(Vt)为特征或以选定操作电压的不同沟道导电性为特征。可通过施加合适编程电压而改变铁电材料的极化状态，且其导致高沟道电导或低沟道电导中的一者。在移除编程栅极电压之后(至少一段时间)，由铁电极化状态引起的高电导及低电导保持不变。可通过施加不干扰铁电极化的小漏极电压而读取沟道的状态。
附图说明
图1是实例性实施例的凹陷FeFET的图解横截面视图。
具体实施方式
常规FeFET可发生的问题是：在完全切换铁电材料的极化状态之前，界面氧化物可遭遇分解。此可导致难以使铁电材料循环及/或可导致难以完全切换铁电材料。在本文所呈现的一些实施例中，提出凹陷FeFET。这些凹陷装置可减轻或防止与常规FeFET相关联的界面氧化物分解问题。
参考图1，实例性实施例的晶体管构造10展示为并入到基底12中。
基底12可包括半导体材料，且在一些实施例中可包括单晶硅，主要由单晶硅组成，或由单晶硅组成。在一些实施例中，基底12可被视为包括半导体衬底。术语“半导体衬底”意指包括半导体材料(其含括(但不限于)块状半导体材料，例如半导体晶片)(单独或组合地包括其它材料)及半导体材料层(单独地或组合地包括其它材料)的任何构造。术语“衬底”指代任何支撑结构，其含括(但不限于)上文所描述的半导体衬底。在一些实施例中，基底12可对应于包含与集成电路制造相关联的一或多种材料的半导体衬底。一些材料可位于基底12的所展示区域下方及/或可横向地相邻于基底12的所展示区域；且可对应于(例如)耐火金属材料、防蚀材料、扩散材料、绝缘体材料等中的一或多者。
半导体基底展示为包括p型掺杂区域及n型掺杂区域(其中n型掺杂区域特别展示为重掺杂“n+”区域)。
凹槽14延伸到基底12中。所述凹槽延伸到深度“D”。此深度可为任何合适尺寸；且在一些实施例中可在从约
Figure BDA0002320242210000021
到约
Figure BDA0002320242210000022
的范围内。所述凹槽具有宽度“W1”。此宽度可为任何合适尺寸；且在一些实施例中可在从约14nm到约20nm的范围内。
绝缘材料16内衬在凹槽中。所述绝缘材料经配置为具有开口向上容器形状的结构17。绝缘材料16可称为第一绝缘材料以区分其与构造10的其它绝缘材料，且结构17可称为第一绝缘结构。绝缘结构17可为同质的(如所展示)或可包括多种离散材料(例如，层板)。在一些实施例中，结构17可包括一或多种氧化物，主要由一或多种氧化物组成，或由一或多种氧化物组成。在一些实施例中，结构17可包括二氧化硅及氮化硅中的一或两者，主要由二氧化硅及氮化硅中的一或两者组成，或由二氧化硅及氮化硅中的一或两者组成。
绝缘材料16具有厚度“T1”。此厚度可为任何合适尺寸；且在一些实施例中可在从约
Figure BDA0002320242210000031
到约
Figure BDA0002320242210000032
的范围内。
导电材料18内衬在绝缘结构17的内部中，且经配置为具有开口向上容器形状的导电结构19。在所展示实施例中，导电结构19嵌套在容器形状的绝缘结构17的下部区域30内，且未沿着绝缘结构17的上部区域32。
导电材料18可称为第一导电材料以区分其与构造10的其它导电材料，且结构19可称为第一导电结构。
导电结构19可为同质的(如所展示)或可包括多种离散材料。在一些实施例中，导电结构19可包括以下一或多者，主要由以下一或多者组成，或由以下一或多者组成：各种金属(例如，钨、钛等)、包含金属的组合物(例如，金属氮化物、金属碳化物、金属硅化物等)及导电性掺杂半导体材料(例如，导电性掺杂硅、导电性掺杂锗等)。例如，在一些实施例中，导电结构19可包括氮化钛及氮化钽中的一或两者，主要由氮化钛及氮化钽中的一或两者组成，或由氮化钛及氮化钽中的一或两者组成。
导电材料18具有厚度“T2”。此厚度可为任何合适尺寸；且在一些实施例中可在从约
Figure BDA0002320242210000033
到约
Figure BDA0002320242210000034
的范围内。
铁电材料20位于容器形状的结构17及19内。所述铁电材料经配置为开口向上的容器形状的铁电结构21。在所展示实施例中，铁电结构21具有在绝缘结构17的下部区域30内的下部区域34，且具有在所述绝缘结构的上部区域32内的上部区域36。铁电结构21的上部区域36位于导电结构19上方且直接抵靠绝缘材料16。所述铁电结构的下部区域34嵌套在容器形状的导电结构19内。
铁电结构21可为同质的(如所展示)或可包括多种离散材料。在一些实施例中，铁电结构21可包括一或多种金属氧化物，主要由一或多种金属氧化物组成，或由一或多种金属氧化物组成。例如，在一些实施例中，铁电结构21可包括以下一或多者，主要由以下一或多者组成，或由以下一或多者组成：铝、氧化铝、铌、氧化铌、锆、氧化锆、铪、氧化铪、钛酸铅锆及钛酸钡锶。在一些实施例中，铁电材料20可在其内具有掺杂物，包括硅、铝、镧、钇、铒、钙、镁、锶及稀土元素中的一或多者。在一些实施例中可利用的铁电材料的两个特定实例是HfxSiyOz及HfxZryOz。
铁电材料20具有厚度“T3”。此厚度可为任何合适尺寸；且在一些实施例中可在从约
Figure BDA0002320242210000041
到约
Figure BDA0002320242210000042
的范围内。
导电材料22位于容器形状的铁电结构21的下部区域34内。导电材料22经配置为部分填充铁电结构21的容器形状的导电结构23。材料22可称为第二导电材料，且结构23可称为第二导电结构。
导电结构23可为同质的(如所展示)或可包括多种离散材料。在一些实施例中，导电结构23可包括以下一或多者，主要由以下一或多者组成，或由以下一或多者组成：各种金属(例如，钨、钛等)、包含金属的组合物(例如，金属氮化物、金属碳化物、金属硅化物等)及导电性掺杂半导体材料(例如，导电性掺杂硅、导电性掺杂锗等)。例如，在一些实施例中，导电结构23可包括氮化钛及钨中的一或两者，主要由氮化钛及钨中的一或两者组成，或由氮化钛及钨中的一或两者组成。
第二导电结构23具有最上表面50，其位于第一导电结构19的最上表面52下方。
第二导电结构23具有横跨最上表面50的宽度“W2”。此宽度可为任何合适尺寸；且在一些实施例中，可在从约
Figure BDA0002320242210000043
到约
Figure BDA0002320242210000044
的范围内。
绝缘材料24位于容器形状的铁电结构21内且位于导电材料22上方。绝缘材料24经配置为绝缘结构25。在一些实施例中，绝缘材料24可称为第二绝缘材料，且结构25可称为第二绝缘结构。
绝缘结构25可为同质的(如所展示)或可包括多种离散材料。在一些实施例中，结构25可包括二氧化硅及氮化硅中的一或两者，主要由二氧化硅及氮化硅中的一或两者组成，或由二氧化硅及氮化硅中的一或两者组成。
基底12的n型掺杂区域形成一对源极区域60/漏极区域62，其位于第一绝缘结构17的彼此对置侧上。沟道区域63位于基底12的p型掺杂部分内，且从源极区域60/漏极区域62中的一者延伸到另一者。沟道区域沿着绝缘结构17的外围。
尽管源极/漏极区域展示为n型掺杂区域且沟道区域展示为p型掺杂区域，但在其它实施例中，可利用其它掺杂方案。此外，尽管沟道区域展示为包括与基底12的其余部分相同的半导体材料，但在其它实施例中，至少一些沟道区域可包括不同于基底的其它区域的组合物。在一些实施例中，构成沟道区域63的材料可称为沟道材料。此沟道材料在一些实施例中可包括基底12的单晶硅，或在其它实施例中可包括其它半导体材料。所述沟道材料可以不同于基底12的其它区域的方式被掺杂，且可(例如)具有提供在其内的阈值电压掺杂物。
在所展示实施例中，导电结构19的最上表面52位于大致相同于源极区域60/漏极区域62的最下表面的层级处，且据此，导电结构19与源极区域60/漏极区域62存在少量(如果存在)垂直重叠。在其它实施例中，导电结构19可至少部分沿着绝缘结构17的所说明上部区域32延伸，使得导电结构19与源极/漏极区域存在垂直重叠。
晶体管构造10可用作MFMIS(金属-铁电-金属-绝缘体-衬底)装置。具体来说，导电结构23可对应于所述装置的控制栅极，且导电结构19可对应于所述装置的浮动栅极。晶体管构造10的配置的优点是：浮动栅极的面积大于控制栅极的面积，因为控制栅极位于容器形状的浮动栅极内，且凹陷在浮动栅极的最上表面52下方。此可实现相对于常规装置改良横跨铁电材料20及绝缘材料16的电场分布。在一些实施例中，可横跨铁电材料20而产生足够电场以能够在即使横跨绝缘材料16的电场保持低于分解电压时切换铁电材料的极性。
所说明晶体管构造可为用于集成电路(例如，存储器阵列)中的多个基本上相同构造中的一者。控制栅极可为从相对于图1的横截面的页面向内及向外延伸的导电字线的部分，其中此字线表示可横跨晶体管构造阵列延伸的多个字线。位线(未展示)可基本上正交于字线延伸。可通过沿着字线将晶体管构造的各种材料(例如，导电材料18、导电性掺杂源极区域60/漏极区域62及(也可能)铁电材料20)分割成离散片段而沿着字线的方向使晶体管构造彼此电隔离。
源极区域60/漏极区域62可电连接到集成电路的其它组件。例如，源极/漏极区域中的一者可电耦合到位线(未展示)且另一者可电耦合到电荷存储装置(例如，电容器)或存储器单元(例如，相变存储器单元、导电桥接RAM单元、另一类型的RRAM单元、磁性RAM单元等)。
可利用任何合适制造序列来形成图1中所展示的构造。实例性制造序列可使用屏蔽、蚀刻、植入及沉积的各种组合来形成构造的各种材料及结构。例如，可利用基底12上方的图案化屏蔽及到基底中的合适蚀刻来形成凹槽14。随后，可利用沉积、蚀刻及(可能)屏蔽的各种组合来使各种材料16、18、20、22及24形成在凹槽内。可在形成凹槽之后提供阈值电压植入物(如果需要)。源极区域60/漏极区域62的n型掺杂在一些实施例中可在形成凹槽之前导通，及/或在其它实施例中可在形成凹槽之后导通。
可将上文所讨论的电子装置并入到电子系统中。这些电子系统可用于(例如)存储器模块、装置驱动器、电力模块、通信调制解调器、处理器模块及专用模块中，且可含括多层多芯片模块。电子系统可为广范围的系统中的任何一者，例如时钟、电视机、蜂窝电话、个人计算机、汽车、工业控制系统、飞机等。
除非另外指定，否则可使用现已知或待开发的任何合适方法(含括(例如)原子层沉积(ALD)、化学气相沉积(CVD)、物理气相沉积(PVD)等)来形成本文所描述的各种材料、物质、组合物等。
术语“介电”及“电绝缘”中的任一者可用来描述具有电绝缘性质的材料。在本发明中，两个术语被视为同义。在一些例项中利用术语“介电”及在其它例项中利用术语“电绝缘”可提供语言变动以简化权利要求书内的先行基础，且不用来指示任何显著化学或电性差异。
图式中的各种实施例的特定定向仅用于说明目的，且在一些应用中，可使实施例相对于所展示定向旋转。本文所提供的具体实施方式及权利要求书涉及具有各种特征之间的所描述关系的任何结构，不论所述结构是否处于图式的特定定向或相对于此定向旋转。
随附插图的横截面视图仅展示横截面的平面内的特征，且未展示横截面的平面后方的材料以简化图式。
当上文提及结构“位于另一结构上”或“抵靠另一结构”时，所述结构可直接位于所述另一结构上或还可存在介入结构。相比之下，当提及结构“直接位于另一结构上”或“直接抵靠另一结构”时，不存在介入结构。当提及结构“连接”或“耦合”到另一结构时，所述结构可直接连接或耦合到所述另一结构，或可存在介入结构。相比之下，当提及结构“直接连接”或“直接耦合”到另一结构时，不存在介入结构。
在实例性实施例中，一种晶体管构造含括内衬在基底内的凹槽中的第一绝缘结构。第一绝缘结构内衬在所述第一绝缘结构的内部中，且铁电结构内衬在所述第一导电结构的内部中。第二导电结构位于所述铁电结构的下部区域内，且所述第二导电结构具有在所述第一导电结构的最上表面下方的最上表面。第二绝缘结构位于所述第二导电结构上方且位于所述铁电结构内。一对源极/漏极区域相邻于所述第一绝缘结构的上部区域且位于所述第一绝缘结构的彼此对置侧上。
在实例性实施例中，一种晶体管构造含括基底内的开口向上的容器形状的第一绝缘结构。开口向上的容器形状的第一导电结构嵌套在所述容器形状的第一绝缘结构的下部区域内。开口向上的容器形状的铁电结构位于所述第一绝缘结构内且位于所述第一导电结构上方。第二导电结构位于所述容器形状的铁电结构的下部区域内。所述第二导电结构具有在所述第一导电结构的最上表面下方的最上表面。第二绝缘结构位于所述第二导电结构上方且位于所述容器形状的铁电结构内。一对源极/漏极区域相邻于所述容器形状的第一绝缘结构的上部区域且位于所述第一绝缘结构的彼此对置侧上。沟道材料沿着所述容器形状的第一绝缘结构的外部区域且从所述源极/漏极区域中的一者延伸到另一者。
在实施性实施例中，一种晶体管构造含括半导体基底，所述半导体基底具有在其内延伸的凹槽。第一绝缘材料内衬在所述凹槽中且经配置为具有开口向上容器形状的第一绝缘结构。第一导电材料位于所述第一绝缘结构内。所述第一导电材料沿着所述第一绝缘结构的所述开口向上容器形状的下部区域且未沿着所述第一绝缘结构的所述开口向上容器形状的上部区域。所述第一导电材料经配置为具有开口向上容器形状的第一导电结构且嵌套在所述第一绝缘结构的所述开口向上容器形状的所述下部区域内。铁电材料位于所述第一绝缘结构及所述第一导电结构内。所述铁电材料经配置为具有开口向上容器形状的铁电结构。所述铁电结构容器形状的上部区域位于所述第一导电结构上方且直接抵靠所述第一绝缘结构，且所述铁电结构的下部区域嵌套在所述第一导电结构的所述开口向上容器形状内。第二导电材料位于所述铁电结构的所述开口向上容器形状的下部区域内。所述第二导电材料经配置为具有在所述第一导电结构的最上表面下方的最上表面的第二导电结构。第二绝缘材料位于所述第二导电材料上方且位于所述铁电结构的所述开口向上容器形状内。一对源极/漏极区域相邻于所述第一绝缘结构的所述开口向上容器形状的所述上部区域且位于所述第一绝缘结构的彼此对置侧上。

Claims (20)

1.一种集成构造，其包括：
第一导电结构，其包括相对的侧壁结构和位于所述相对的侧壁结构之间的开口，所述开口从所述第一导电结构的最上表面延伸并且具有内部基底；
铁电材料，其内衬在所述开口的内部，所述铁电材料具有位于其中的凹槽；
第二导电结构，其位于所述凹槽的下部区域内；具有在所述第一导电结构的最上表面下方的最上表面；及
一对源极/漏极区域，其位于所述第一导电结构的彼此对置侧上。
2.根据权利要求1所述的集成构造，其中所述第一导电结构包括金属。
3.根据权利要求1所述的集成构造，其中所述第一导电结构包括金属氮化物。
4.根据权利要求1所述的集成构造，其中所述第一导电结构包括氮化钛及氮化钽中的一者或两者。
5.根据权利要求1所述的集成构造，其中所述铁电结构包括金属氧化物。
6.根据权利要求5所述的集成构造，其中所述铁电结构含括铝、钡、钙、铒、铪、镧、铅、镁、铌、锶、钛、钇及锆中的一者或多者。
7.根据权利要求1所述的集成构造，其中所述第二导电结构包括金属。
8.根据权利要求1所述的集成构造，其中所述第二导电结构包括钨及氮化钛中的一者或两者。
9.根据权利要求1所述的集成构造，其中所述基底包括单晶硅；其中所述源极/漏极区域是所述基底的所述单晶硅的n型掺杂区域；且其中所述源极/漏极区域之间的沟道区域是所述基底的所述单晶硅的p型掺杂区域。
10.一种集成构造，其包括：
第一导电材料，其具有包括相对的侧壁、上表面和基底表面的外周长；
铁电材料，其抵靠所述基底表面并且抵靠所述相对的侧壁；
第二导电材料，延着所述基底表面和所述相对的侧壁、并且通过所述铁电材料与所述第一导电结构分隔开；及
含硅基底材料，其具有从上表面延伸的开口，所述第一导电材料、所述铁电材料和所述第二导电材料中的每一者被沉积在所述开口内。
11.根据权利要求10所述的集成构造，其还包括位于所述第二导电材料和所述含硅基底材料之间的绝缘结构。
12.根据权利要求11所述的集成构造，其中所述绝缘结构包括竖直向上延伸越过所述第二导电材料的上部区域。
13.根据权利要求12所述的集成构造，其中所述铁电材料与所述绝缘结构的所述上部区域直接接触。
14.根据权利要求12所述的集成构造，其中所述绝缘结构是第一绝缘结构，并且还包括第二绝缘结构，所述第二绝缘结构竖直在所述第一导电材料上方并且与所述第一导电材料直接接触。
15.根据权利要求14所述的集成构造，其中所述第二绝缘结构是均质的。
16.根据权利要求14所述的集成构造，其中所述第二绝缘结构包括多个离散材料。
17.一种集成构造，其包括：
半导体基底，其具有在其中延伸的凹槽；
第一绝缘材料，其内衬于所述凹槽；
浮动栅极，其在所述第一绝缘材料内部地向内的所述凹槽内，所述浮动栅极具有内部侧壁和内部基底表面；
铁电材料，延着所述内部侧壁并且延着所述内部基底表面而内衬；及
控制栅极，其在所述凹槽内并且与所述铁电材料直接物理接触。
18.根据权利要求17所述的集成构造，其还包括在所述控制栅极之上并且与所述控制栅极直接物理接触的绝缘结构。
19.根据权利要求18所述的集成构造，其中所述绝缘结构具有相对的侧壁，所述相对的侧壁与所述铁电材料直接物理接触。
20.根据权利要求17所述的集成构造，其中所述铁电结构含括铝、钡、钙、铒、铪、镧、铅、镁、铌、锶、钛、钇及锆中的一者或多者。
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