CN107768427A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN107768427A
CN107768427A CN201710840090.9A CN201710840090A CN107768427A CN 107768427 A CN107768427 A CN 107768427A CN 201710840090 A CN201710840090 A CN 201710840090A CN 107768427 A CN107768427 A CN 107768427A
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type
layer
semiconductor device
buffer layer
negative electrode
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增冈史仁
中村胜光
西井昭人
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

本发明涉及一种半导体装置。在n－型漂移层(1)的顶面设置有p型正极层(2)。在n－型漂移层(1)的底面设置有n型负极层(3)。在n－型漂移层(1)与n型负极层(3)之间设置有n型缓冲层(4)。n型缓冲层(4)的峰值浓度高于n－型漂移层(1)，低于n型负极层(3)。n－型漂移层(1)与n型缓冲层(4)的连接部分处的载流子浓度的梯度为20～2000cm‑4。

Description

半导体装置
本申请是基于申请日2013.6.12(进入国家阶段日2015.12.11)的中国国家申请号201380077391.0(PCT/JP2013/066228)申请(半导体装置)的分案申请，以下引用其内容。
技术领域
本发明涉及一种在高耐压功率模块(≥600V)中使用的二极管等半导体装置。
背景技术
在20世纪50年代的半导体初期以后，针对Si基p-i-n二极管中的高频振荡现象(例如参照非专利文献1)和击穿现象(例如参照非专利文献2)进行了各种研究。近年来，在高速动作化得到发展的功率器件中，会导致周边电路的误动作和器件自身的浪涌击穿，这些现象再次受到了关注(例如参照非专利文献3)。
已知在快速恢复二极管中，这些现象在高Vcc、高配线电感(Ls)、低动作温度、以及低电流密度(JA)等硬恢复条件下变得显著(例如参照非专利文献5、11)。在快速恢复二极管中，通过采用厚的n－型漂移层或厚的n型缓冲层、以及应用寿命控制技术等(例如参照非专利文献5～7)所谓的“软恢复化”，解决了上述课题。但是，在这些方法中，存在EMI(Electromagnetic Compatibility)噪声、击穿耐量、以及总损耗之间的折衷关系，难于以高水平同时兼顾。
另一方面，通过以RFC二极管(例如参照非专利文献10～14)为代表的、在背面形成p+型层的二极管(例如参照非专利文献4、8、9)，显著地提高了二极管的主要特性。但是，作为进一步的开发课题，遗留有下述课题，即，通过降低泄漏电流而使动作温度范围向高温侧扩展、通过降低高电流密度区域的VF(二极管的导通时的压降)而提高最大切断电流密度、以及通过增强缓冲构造而提高雪崩耐量。
另外，提出了在n－型漂移层与n型负极层之间设置了具有两者中间的杂质浓度的n型缓冲层的二极管(例如参照专利文献1、2)。虽然专利文献1中未记载n型缓冲层的浓度梯度的具体数值，但从专利文献1的图3能够估计出浓度梯度为8×103cm-4。另外，专利文献2的n型缓冲层是非专利文献10中记载的结构，其浓度梯度为1×105cm-4。
专利文献1：日本特开2007－158320号公报
专利文献2：日本特开2010－283132号公报
非专利文献1：W.T.READ,JR,“A Proposed High-Frequency,Negative-Resistance Diode,”The Bell system technical journal,pp.401-446(March 1958)
非专利文献2：H.Egawa,“Avalanche Characteristics and Failure Mechanismof High Voltage Diodes,”IEEE Trans.Electron Devices,vol.ED-13,No.11,pp.754-758(1966)
非专利文献3：R.Siemieniec,P.Mourick,J.Lutz,M.Netzel,“Analysis ofPlasma Extraction Transit Time Oscillations in Bipolar Power Devices,”Proc.ISPSD’04,pp.249-252,Kitakyushu,Japan(2004)
非专利文献4：K.Satoh,K.Morishita,Y.Yamaguchi,N.Hirano,H.Iwamoto andA.Kawakami,“A Newly Structured High Voltage Diode Highlighting OscillationFree Function in Recovery Process,”Proc.ISPSD’2000,pp.249-252,Toulouse,France(2000)
非专利文献5：M.T.Rahimo and N.Y.A.Shammas,“Optimization of the ReverseRecovery Behavior of Fast Power Diodes Using Injection Efficiency AndLifetime Control Techniques,”Proc.EPE’97,pp.2.099-2.104,Trondheim,Norway(1997)
非专利文献6：M.Nemoto,T.Naito,A.Nishihara,K.Ueno,“MBBL diode:a novelsoft recovery diode,”Proc.ISPSD’04,pp.433-436,Kitakyushu,Japan
非专利文献7：H.Fujii,M.Inoue,K.Hatade and Y.Tomomatsu,“A Novel BufferStructure and lifetime control Technique with Poly-Si for Thin Wafer Diode,”Proc.ISPSD’09,pp.140-143,Barcelona,Spain(2009)
非专利文献8：A.Kopta and M.Rahimo,“The Field Charge Extraction(FCE)Diode A Novel Technology for Soft Recovery High Voltage Diodes,”Proc.ISPSD’05,pp.83-86,Santa Barbara,California,USA(2005)
非专利文献9：H.P.Felsl,M.Pfaffenlehner,H.Schulze,J.Biermann,Th.Gutt,H.-J.Schulze,M.Chen and J.Luts,“The CIBH Diode-Great Improvement forRuggedness and Softness of High Voltage Diodes,”Proc.ISPSD’08,pp.173-176,Orlando,Florida,USA(2008)
非专利文献10：K.Nakamura,Y.Hisamoto,T.Matsumura,T.Minato andJ.Moritani,“The Second Stage of a Thin Wafer IGBT Low Loss 1200V LPT-CSTBTTMwith a Backside Doping Optimization Process,”Proc.ISPSD’06,pp.133-136,Naples,Italy(2006)
非专利文献11：K.Nakamura,H.Iwanaga,H.Okabe,S.Saito and K.Hatade,“Evaluation of Oscillatory Phenomena in Reverse Operation for High VoltageDiodes,”Proc.ISPSD’09,pp.156-159,Barcelona,Spain(2009)
非专利文献12：K.Nakamura,F.Masuoka,A.Nishii,K.Sadamatsu,S.Kitajima andK.Hatade,“Advanced RFC Technology with New Cathode Structure of FieldLimiting Rings for High Voltage Planar Diode,”Proc.ISPSD’10,pp.133-136,Hiroshima,Japan(2010)
非专利文献13：A.Nishii,K.Nakamura,F.Masuoka and T.Terashima,“Relaxation of Current Filament due to RFC Technology and Ballast Resistorfor Robust FWD Operation,”Proc.ISPSD’11,pp.96-99,San Diego,California,USA(2011)
非专利文献14：F.Masuoka,K.Nakamura,A.Nishii and T.Terashima,“GreatImpact of RFC Technology on Fast Recovery Diode towards 600V for Low Loss andHigh Dynamic Ruggedness,”Proc.ISPSD’12,pp.373-376,Bruges,Belgium(2012)
发明内容
在现有的半导体装置中，n－型漂移层与n型缓冲层的连接部分处的载流子浓度的梯度是陡峭的，为8×103cm-4或1×105cm-4，因此，由于连接部分的电场强度的增高而产生阶跃(snap off)。此外，存在以阶跃作为触发而产生高频振荡的问题。
另外，通过使用重金属扩散、电子或离子的照射实现的寿命控制方法，对现有的二极管的VF和恢复损耗EREC的折衷特性进行了调整。但是，根据电子或离子照射时的与被照射体之间的照射角度、温度等的不同，VF、EREC的波动较大。另外，由于芯片通电动作时的自发热，因而晶格缺陷发生变化，电气特性发生变动。此外，由于由晶格缺陷产生的泄漏电流较大，所以在高温动作时发生热失控。因此，需要确立一种不依赖于寿命控制方法的、VF-EREC折衷特性的控制方法。
功率器件在各种用途中得到使用，对IGBT、二极管等也要求雪崩耐量。但是，在具有寄生双极型晶体管构造的半导体装置中，与不具有这种构造的半导体装置相比，雪崩耐量减少。另外，如果以VF-EREC特性的改善为目标而使n－型漂移层的厚度变薄，则雪崩耐量显著降低。另外，在具有寄生双极型晶体管构造的半导体装置中，与不具有这种构造的半导体装置相比，最大可控电流密度降低。
本发明就是为了解决上述课题而提出的，第1目的是得到一种能够实现高振荡耐量的半导体装置。第2目的是得到一种能够不依赖于寿命控制方法而改善VF-EREC折衷特性、提高雪崩耐量和最大可控电流密度的半导体装置。
本发明所涉及的半导体装置的特征在于，具备：n型漂移层；p型正极层，其设置在所述n型漂移层的顶面；负极层，其设置在所述n型漂移层的底面；以及n型缓冲层，其设置在所述n型漂移层与所述负极层之间，所述n型缓冲层的峰值浓度高于所述n型漂移层，低于所述负极层，所述n型漂移层与所述n型缓冲层的连接部分处的载流子浓度的梯度为20～2000cm-4。
发明的效果
根据本发明，能够实现高振荡耐量。
附图说明
图1是表示本发明的实施方式1所涉及的半导体装置的俯视图。
图2是表示本发明的实施方式1所涉及的半导体装置的仰视图。
图3是沿图1及图2的I-II的剖视图。
图4是表示相对于深度的载流子浓度的图。
图5是表示相对于载流子浓度梯度的VF、EREC、Vsnap-off、JA(break)的图。
图6是表示本发明的实施方式2所涉及的半导体装置的剖视图。
图7是表示本发明的实施方式3所涉及的半导体装置的剖视图。
图8是表示对比例所涉及的半导体装置的剖视图。
图9是表示用于模拟的n型缓冲层的峰值浓度和扩散深度的图。
图10是表示对比例和实施方式3中的耐压波形的缓冲层厚度依赖性的模拟结果的图。
图11是表示对比例和实施方式3中的活跃恢复(snappy recovery)波形的Vcc依赖性的模拟结果的图。
图12是表示对比例和实施方式3中的活跃恢复波形的Vcc依赖性的模拟结果的图。
图13是表示本发明的实施方式4所涉及的半导体装置的后视图。
图14是沿图13的I-II的剖视图。
图15是沿图13的III-IV的剖视图。
图16是表示本发明的实施方式4所涉及的半导体装置的变形例1的仰视图。
图17是表示本发明的实施方式4所涉及的半导体装置的变形例2的仰视图。
图18是表示本发明的实施方式5所涉及的半导体装置的剖视图。
图19是表示本发明的实施方式6所涉及的半导体装置的剖视图。
图20是表示本发明的实施方式7所涉及的半导体装置的剖视图。
图21是表示本发明的实施方式8所涉及的半导体装置的剖视图。
图22是表示本发明的实施方式9所涉及的半导体装置的剖视图。
图23是表示本发明的实施方式10所涉及的半导体装置的剖视图。
图24是表示本发明的实施方式11所涉及的半导体装置的剖视图。
图25是表示本发明的实施方式12所涉及的半导体装置的剖视图。
图26是表示本发明的实施方式13所涉及的半导体装置的剖视图。
具体实施方式
参照附图，对本发明的实施方式所涉及的半导体装置进行说明。对相同或相对应的结构要素标注相同标号，有时省略重复的说明。
实施方式1
图1以及图2分别是表示本发明的实施方式1所涉及的半导体装置的俯视图以及仰视图。图3是沿图1及图2的I-II的剖视图。在n－型漂移层1的顶面设置有p型正极层2。在n－型漂移层1的底面设置有n型负极层3。
在n－型漂移层1与n型负极层3之间设置有n型缓冲层4。n型缓冲层4的杂质的峰值浓度高于n－型漂移层1，低于n型负极层3。正极电极5与p型正极层2欧姆接触，负极电极6与n型负极层3欧姆接触。
图4是表示相对于深度的载流子浓度的图。将n型缓冲层4的深度设为Dbuffer，将n型漂移层与n型缓冲层的连接部分处的载流子浓度的梯度设为浓度梯度将n型缓冲层4中的有效剂量设为φeff[cm-2]，将n－型漂移层1的载流子浓度设为n0[cm-3]。它们之间的关系用下面的公式表示。
公式1
图5是表示相对于载流子浓度梯度的VF、EREC、Vsnap-off、JA(break)的图。VF是导通状态下的压降，EREC是恢复损耗，Vsnap-off是恢复时的过冲电压，JA(break)是最大可控电流密度。基于该数据，为了降低VF、EREC、Vsnap-off、提高JA(break)，将浓度梯度设为20～2000cm-4。此外，在现有技术中，浓度梯度为105cm-4左右，比本实施方式陡峭。
如本实施方式所示，将n－型漂移层1与n型缓冲层4的连接部分的载流子浓度缓且宽地进行了分布的深缓冲构造称为CPL(Controlling Plasma Layer)缓冲构造。利用该CPL缓冲构造，能够抑制恢复时的该边界部分处的电场强度的增高。其结果，能够防止由负极侧的电场强度的增高而产生的阶跃、以及以该阶跃作为触发而产生的高频振荡，因此能够实现高振荡耐量。
另外，将n型缓冲层4的有效剂量φeff设定为比n－型漂移层1的有效剂量高的1×1012～5×1012cm-2。由此，n型缓冲层4的总剂量变为与n－型漂移层1的总剂量同等程度，因此能够利用n－型漂移层1和n型缓冲层4这两者保持耐压。因此，与不存在n型缓冲层4的情况相比，能够使保持同等耐压所需的n－型漂移层1的厚度变薄，能够减少总损耗。
此外，n－型漂移层1的载流子浓度n0依赖于耐压等级而决定。作为一个例子，在600～6500V等级的情况下，载流子浓度n0为1×1012～1×1015cm-3。n型负极层3的表面浓度为1×1019～5×1020cm3，扩散深度为0.5～2μm。n型缓冲层4的厚度Dbuffer如上述公式所示，是n0、φeff的函数。
另外，n型缓冲层4的峰值浓度与n－型漂移层1的峰值浓度之比为1×10-4～1×10-1。n型缓冲层4与n－型漂移层1的深度之比为0.1～10。
实施方式2
图6是表示本发明的实施方式2所涉及的半导体装置的剖视图。实施方式1是二极管，但本实施方式是IGBT(Insulated Gate Bipolar Transistor)。
p型正极层2是p型基极层，其峰值浓度为1.0×1016～1.0×1018cm-3。在p型正极层2上的晶片表面部局部地形成有p+型扩散层7和n+型发射极层8。n+型发射极层8的峰值浓度为1.0×1018～1.0×1021cm-3，深度为0.2～1.0μm。
在p型正极层2与n－型漂移层1之间形成有n+型层9。n+型层9的峰值浓度为1.0×1015～1.0×1017cm-3，深度比p型正极层2深0.5～1.0μm。
以贯穿n+型发射极层8、p型正极层2以及n+型层9的方式设置有沟槽栅极10。在沟槽栅极10上设置有层间绝缘膜11。正极电极5是发射极电极，与p+型扩散层7连接。代替n型负极层3而设置有p型集电极层12。负极电极6是集电极电极，与p型集电极层12欧姆接触。
n型缓冲层4的峰值浓度高于n－型漂移层1，低于p型集电极层12。并且，与实施方式1同样地，将n－型漂移层1与n型缓冲层4的连接部分处的载流子浓度的梯度设为20～2000cm-4。并且，将n型缓冲层4的有效剂量φeff设定为比n－型漂移层1的有效剂量高的1×1012～5×1012cm-2。由此，在IGBT的情况下也能够得到与实施方式1相同的效果。
实施方式3
图7是表示本发明的实施方式3所涉及的半导体装置的剖视图。代替实施方式1的单层的n型负极层3，将n型负极层3与p型负极层13横向并排而交替地配置。负极电极6欧姆接触于n型负极层3和p型负极层13。因此，p型负极层13通过负极电极6与n型负极层3短路。n型负极层3的峰值浓度高于p型负极层13。
在n－型漂移层1的深度tn－、n型负极层3的宽度Wn、p型负极层13的宽度Wp之间，下述关系成立。
2tn－≥(Wn+Wp)≥tn－/10
与对比例对比，说明本实施方式的效果。具体地说，说明在设计为耐压1700V的本实施方式与对比例的二极管中，n型缓冲层4的峰值浓度和扩散深度相对于Vrrm、阶跃耐量、以及恢复耐量的依赖性。图8是表示对比例所涉及的半导体装置的剖视图。在对比例中，不存在n型缓冲层4，n型负极层3为单层。
在此，将非专利文献14的图4的恢复条件相对于峰值电压Vsnap-off的容许程度称为阶跃耐量。阶跃耐量越高，越能够容许高施加电压、低电流、低温、快速电流切断等所谓的硬恢复条件下的动作。另外，将非专利文献14的图7中表示的由施加电压Vcc和最大切断电流密度JA(break)构成的安全动作区域称为恢复耐量。恢复耐量越高，越能够容许高施加电压、大电流密度条件下的恢复动作。
图9是表示用于模拟的n型缓冲层的峰值浓度和扩散深度的图。如该图所示，将剂量固定为3.75×1012cm-2，设定以三角形近似法所设定的峰值浓度和扩散深度，模拟出接近高斯分布的n型缓冲层4。另外，与n型缓冲层4的厚度无关，将n－型漂移层1的厚度设为恒定。
图10是表示对比例和实施方式3中的耐压波形的缓冲层厚度依赖性的模拟结果的图。各个二极管均设计为耐压1700V。图11、12是表示对比例和实施方式3中的活跃恢复(snappy recovery)波形的Vcc依赖性的模拟结果的图。n型缓冲层4的峰值浓度为5×1016cm-3，n型缓冲层4的厚度在图11中为1.5μm，在图12中为50μm。
在对比例中，由主结部处的电场强度的增高造成的碰撞电离所产生的电子利用n－型漂移层1中的高电场而向负极侧移动。由此，电子的浓度超过缓冲层中的载流子浓度，从而根据泊松方程的关系，n型缓冲层4中的电场的梯度逆转，在主结的基础上，在负极侧电场强度也增高。因此，在对比例中，n型缓冲层4越厚，负微分电阻NDR的特性从JR＝10A/cm2左右起越表现得显著。在JR＝100～1000A/cm2附近，在主结和负极侧两者处产生碰撞电离，从主结侧和负极侧两者向n－型漂移层1中供给电子和空穴，达到二次击穿。
另一方面，在本实施方式中，耐压波形中没有显现出NDR特性，在n型缓冲层4较薄的情况下，在耐压波形的JR＝1A/cm2附近出现2次击穿。该小电流区域中的二次击穿导致二极管的恢复SOA中的最大切断电流密度的降低、雪崩耐量的降低，因此要求使二次击穿的发生点大电流化。另一方面，在表现出NDR特性的二极管构造中，在恢复时负极侧的电场上升，由此发生电压浪涌和阶跃，容易以其作为触发而发生高频振荡(参照图11、12)。因此，二极管的耐压波形需要接近直线型的线，而不表现出由NDR特性、二次击穿产生的S形曲线。从图10可以看出，优选使n型缓冲层4较厚。
但是，如果使n－型漂移层1的厚度恒定，仅仅使n型缓冲层4变厚，则导通状态下的电阻成分变大，导致VF的增加(恶化)。因此，在本实施方式中，将n－型漂移层1与n型缓冲层4的连接部分处的载流子浓度的梯度设为20～2000cm-4。通过如上述所示使连接部分处的浓度变化变缓，从而能够防止耐压波形的二次击穿以及NDR，抑制VF的增加，并且抑制恢复时的连接部分处的电场强度的增高。其结果，能够防止由负极侧的电场强度的增高而产生的阶跃、以及以该阶跃作为触发而产生的高频振荡，因此能够实现高振荡耐量。
另外，将由(Wn+Wp)表示的宽度称为RFC单元间距(cell pitch)。如果使RFC单元间距变窄，则VF增加，EREC减少。即，VF-EREC折衷曲线向高速侧偏移。因此，在将本实施方式应用于要装入逆变器的续流二极管的情况下，通过与用途相匹配地调整RFC单元间距，从而能够调整VF-EREC折衷特性。但是，如果将RFC单元间距设定得过窄，则阶跃耐量降低，相反，如果设定得过宽，则恢复耐量降低。
另外，将由(Wp/(Wn+Wp))表示的比率称为RFC单元短路率(cell short rate)。如果使RFC单元短路率变小，则VF增加，EREC减少。即，VF-EREC折衷曲线向高速侧偏移。因此，在将本实施方式应用于要装入逆变器的续流二极管的情况下，通过与用途相匹配地调整RFC单元短路率，从而能够调整VF-EREC折衷特性。但是，如果将RFC单元短路率设定得过小，则阶跃耐量降低，交叉点(cross point)增加，相反，如果设定得过大，则恢复耐量降低。
如上述所示，在本实施方式中，通过调整RFC单元间距或RFC单元短路率，从而能够控制VF-EREC折衷特性而不依赖于寿命控制方法。
另外，如果减少p型负极层13的剂量，则阶跃耐量降低，但能够抑制EREC和泄漏电流。如果增加P型负极层13的剂量，则得到相反的结果。与此相对，在本实施方式中，能够确保阶跃耐量和恢复耐量，能够扩大p型负极层13的剂量的设定容许范围。
在单纯的p-n结中，VF的温度依赖性基本为正，如果温度上升，则电流变得容易流动。在将功率芯片并联连接而得到的大容量的功率模块中，如果芯片的温度分布产生不均匀，则发生诸如在发热量大的芯片中进一步流过电流而发热这样的正反馈，有可能引起模块的损坏。因此，室温的VF曲线与高温的VF曲线相交叉的电流值(交叉点)优选较低。在本实施方式中，能够降低正极和负极的有效的剂量，降低来自双方的载流子注入效率，因此能够实现低电流值的交叉点。
另外，也可以使负极电极6与n型负极层3欧姆接触，与p型负极层13肖特基接触。负极电极6与p型负极层13之间的肖特基势垒差较大，由此，变为与对寄生的pnp晶体管附加了电阻成分相同的状态，能够抑制由寄生的pnp晶体管动作产生的器件纵向的电流。其结果，能够实现高恢复SOA和高雪崩耐量。
实施方式4
图13是表示本发明的实施方式4所涉及的半导体装置的后视图。图14是沿图13的I-II的剖视图。代替实施方式3的单层的n型缓冲层4，将n型缓冲层4与n型缓冲层14横向并排而交替地配置。在n－型漂移层1与n型负极层3之间设置有n型缓冲层4，在n－型漂移层1与p型负极层13之间设置有n型缓冲层14。n型缓冲层4、14的峰值浓度高于n－型漂移层1，低于n型负极层3。n型缓冲层4的峰值浓度高于n型缓冲层14。其他结构与实施方式3相同。
图15是沿图13的III-IV的剖视图。设置有p型正极层2的区域是活性区域，与其相比外侧的区域是终端区域。在终端区域的正极侧设置有通常的p型保护环层15，在终端区域的最外周部设置有n型沟道截断层16。p型保护环层15的峰值浓度高于p型正极层2，n型沟道截断层16的峰值浓度高于n－型漂移层1。
终端区域的负极构造从向活性区域侧与p型正极层2的最外周部分离了距离WGR：10～500μm的位置开始。终端区域的负极构造是n型层17和p型层18的两层构造。
在本实施方式中，通过提高n型负极层3上的n型缓冲层4的剂量，从而提高导通状态下的来自负极侧的电子的注入效率。另外，在施加L负载电路中的感应电动势而使装置达到雪崩状态时，耗尽层难以到达p型负极层13，耐压波形的NDR(二次击穿)得到抑制。其结果，能够实现低VF和高雪崩耐量。将雪崩状态的容许程度称为雪崩耐量。
另外，n型负极层3和p型负极层13为条带图案。由此，能够简单地设计反映出设想的n型负极层3与p型负极层13之比的图案。
图16是表示本发明的实施方式4所涉及的半导体装置的变形例1的仰视图。如上述所示，即使终端区域的负极为n型，也能够得到与上述相同的效果。
图17是表示本发明的实施方式4所涉及的半导体装置的变形例2的仰视图。n型负极层3为点图案。由此，能够实现对角部也进行了考虑的图案设计，能够实现均匀的器件动作。其结果，能够实现高恢复SOA。此外，p型负极层13为点图案也能够得到相同的效果。
实施方式5
图18是表示本发明的实施方式5所涉及的半导体装置的剖视图。n型缓冲层4的深度比n型缓冲层14深。其他结构与实施方式4相同。在此情况下，也能够得到与实施方式4相同的效果。
实施方式6
图19是表示本发明的实施方式6所涉及的半导体装置的剖视图。代替实施方式4的单层的p型正极层2，将p型正极层2与p型正极层19横向并排而交替地配置。正极电极5与p型正极层2、19欧姆接触。因此，p型正极层19通过正极电极5与p型正极层2短路。p型正极层19的峰值浓度低于p型正极层2。p型正极层2与p型正极层19的峰值浓度比为0.5～500。
通过设置低浓度的p型正极层19，从而导通状态下的正极侧的注入效率得到抑制，因此导通状态的正极侧的载流子浓度降低，能够抑制振荡的触发、即负极侧的电场强度的上升。另外，在导通状态下n－型漂移层1内的载流子少，因此能够抑制在恢复时载流子集中于终端区域与活性区域的边界部而导致击穿的现象。其结果，能够实现高恢复SOA、高振荡耐量、低VF、低交叉点、高浪涌电流耐量。
实施方式7
图20是表示本发明的实施方式7所涉及的半导体装置的剖视图。p型正极层19仅设置在p型正极层2的顶面的一部分。p型正极层19的深度相对于p型正极层2的深度之比为0.1～0.9。在此情况下，也能够得到与实施方式6相同的效果。
实施方式8
图21是表示本发明的实施方式8所涉及的半导体装置的剖视图。在终端区域的n－型漂移层1的底面，仅设置有单层的n型层17。负极电极6与n型层17接触而电连接。n型层17具有1×1015～1×1016cm-3的峰值浓度。由此，n型缓冲层14相对于负极电极6的接触电阻变大。因此，能够抑制在导通状态下来自终端区域的负极侧的电子的注入，提高恢复SOA。
实施方式9
图22是表示本发明的实施方式9所涉及的半导体装置的剖视图。n型缓冲层4为单层，并且终端区域的负极构造也为n型层17单层。由此，与实施方式8相比，能够进一步简化结构。
实施方式10
图23是表示本发明的实施方式10所涉及的半导体装置的剖视图。在终端区域的最外周部设置有n型沟道截断缓冲层20。在n型沟道截断缓冲层20中设置有n型沟道截断层21以及p型沟道截断层22。n型沟道截断缓冲层20的峰值浓度高于n－型漂移层1。n型沟道截断层21的峰值浓度高于n型沟道截断缓冲层20以及p型沟道截断层22。由此，能够实现高恢复SOA。
实施方式11
图24是表示本发明的实施方式11所涉及的半导体装置的剖视图。代替通常的p型保护环层15，设置有LNFLR(Linearly-Narrowed Field Limiting Ring)构造23。LNFLR构造23是从活性区域朝向终端区域周期性地并排的多个p型层。该多个p型层朝向终端区域具有线性的浓度梯度。
在活性区域的p型正极层2与LNFLR构造23之间设置有RESURF(Reduced SurfaceField)构造24。RESURF构造24具有在活性区域端形成的深的p层、以及扩散深度与LNFLR构造23的扩散层相同的p层。RESURF构造24的剂量为2×1012/m2，宽度为5～100μm。通过设置RESURF构造24，从而能够缓和恢复时的电场峰值。
实施方式12
图25是表示本发明的实施方式12所涉及的半导体装置的剖视图。代替实施方式11的RESURF构造24，在本实施方式中，设置有VLD(Variation of Lateral Doping)构造25。VLD构造25具有在活性区域端形成的深的p层、以及为了连接该深的p层与LNFLR扩散层的深度而具有梯度的p层。
实施方式13
图26是表示本发明的实施方式13所涉及的半导体装置的剖视图。在活性区域中设置有IGBT，在终端区域中设置有LNFLR构造23。在此情况下，也能够得到与实施方式11相同的效果。
此外，本发明的半导体装置不限于由硅形成，也可以由带隙大于硅的宽带隙半导体形成。宽带隙半导体例如是碳化硅、氮化镓类材料、或者金刚石。由这样的宽带隙半导体形成的半导体装置的耐电压性、容许电流密度高，因此能够实现小型化。通过使用该小型化的装置，由此，组装有该装置的半导体模块也能够实现小型化。另外，元件的耐热性高，因此能够将散热器的散热片小型化，将水冷部风冷化，因而能够进一步使半导体模块小型化。另外，元件的功率损耗低、效率高，因此能够使半导体模块高效化。
另外，在上述实施方式中，以1200V或1700V等级的低/中耐压等级为例进行了说明。但是，无论耐压等级如何，都能够得到上述的效果。
标号的说明
1 n－型漂移层，2、19 p型正极层，3 n型负极层，4、14 n型缓冲层，6 负极电极，12p型集电极层，13 p型负极层，17 n型层，20 n型沟道截断缓冲层，21 n型沟道截断层，22 p型沟道截断层，23 LNFLR构造，24 RESURF构造，25 VLD构造。

Claims (3)

1.一种半导体装置，其特征在于，具备：
n型漂移层；
p型基极层，其设置在所述n型漂移层的顶面；
n型发射极层，其局部地设置于所述p型基极层上；
沟槽栅极，其以贯穿所述n型发射极层以及所述p型基极层的方式设置；
p型集电极层，其设置于所述n型漂移层的底面；以及
n型缓冲层，其设置在所述n型漂移层与所述p型集电极层之间，
所述n型缓冲层的峰值浓度高于所述n型漂移层，低于所述p型集电极层，
所述n型缓冲层的载流子浓度从所述n型漂移层侧朝向所述p型集电极层侧以深度的指数函数增加，
所述n型漂移层与所述n型缓冲层的连接部分处的所述n型缓冲层的所述载流子浓度的梯度为20～2000cm-4。
2.根据权利要求1所述的半导体装置，其特征在于，
所述n型缓冲层的有效剂量为1×1012～5×1012cm-2，高于所述n型漂移层。
3.根据权利要求1或2所述的半导体装置，其特征在于，
所述半导体装置还具备：
LNFLR构造，其设置在终端区域，该LNFLR是线性缩小场限环；以及
RESURF构造，其设置在所述p型基极层的外端部，该RESURF是降低表面场。
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