JP2017135339A - 半導体装置 - Google Patents
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Abstract
【解決手段】ドリフト層11における厚み方向の中間位置に、ドリフト層11よりもN型不純物濃度が高くされた中間FS層25を形成する。中間FS層25の形成位置を、ドリフト層11のうち、半導体基板10の表面側から半導体基板10の厚みの15%以上かつ35%以下の深さとなる位置とする。これにより、半導体装置にIGBT領域1aが形成される場合、スイッチングのオフ時におけるコレクタ電圧波形の振動を抑制する。又、半導体装置にダイオード1bが形成される場合、リカバリ動作時におけるリカバリ波形振動を抑制する。
【選択図】図2
Description
本発明の第1実施形態にかかる半導体装置について説明する。本実施形態にかかる半導体装置は、基板厚み方向に電流を流す縦型半導体素子としてIGBTとFWDとが1つの基板に備えられたRC−IGBT構造により構成されている。この半導体装置は、例えば、インバータ、DC/DCコンバータ等の電源回路に使用されるパワースイッチング素子として利用されると好適である。具体的には、本実施形態にかかる半導体装置は、以下のように構成されている。
本発明は上記した実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において適宜変更が可能である。
1b ダイオード領域
10 半導体基板
11 ドリフト層
12 ベース層
20 FS層
21 コレクタ層
22 カソード層
25 中間FS層
Claims (7)
- 縦型半導体素子を有する半導体装置であって、
半導体基板(10)によって構成され、第1導電型不純物濃度が前記半導体基板の第1導電型不純物濃度とされた第1導電型のドリフト層(1)と、
前記ドリフト層の裏面側に形成された第1導電型または第2導電型の半導体層(21、22)と、
前記半導体基板の表面側に形成された第2導電型領域(12、15)と、
前記半導体基板の表面側に形成され、前記第2導電型領域に接続させられた上部電極(19)と、
前記半導体基板の裏面側に形成され、前記半導体層と接続させられた下部電極(23)とを備え、
さらに、前記ドリフト層のうち、前記半導体基板の表面側から前記半導体基板の厚みの15%以上かつ35%以下の深さとなる位置に、該ドリフト層よりも第1不純物濃度が高くされた中間フィールドストップ層(25)を備えている半導体装置。 - 前記中間フィールドストップ層は、第1導電型不純物濃度が前記ドリフト層の2倍以上かつ7倍以下の濃度である請求項1に記載の半導体装置。
- 前記中間フィールドストップ層は、第1導電型不純物濃度が前記ドリフト層の濃度の6倍以下の濃度である請求項2に記載の半導体装置。
- 前記縦型半導体素子が形成された領域をセル領域(1)とし、該セル領域を囲む外周部分を外周領域(2)として、
前記中間フィールドストップ層は、前記セル領域に形成されており、前記外周領域のうちの少なくとも外周側には形成されていない請求項1ないし3のいずれか1つに記載の半導体装置。 - 前記縦型半導体素子はIGBTであり、
前記半導体層を第2導電型のコレクタ層(21)とし、
前記第2導電型領域をベース層(12)として、
前記セル領域において、前記ベース層よりも深く形成されたトレンチ(13)の表面にゲート絶縁膜(16)を介してゲート電極(17)が形成されたトレンチゲート構造と、
前記ベース層の表層部に前記トレンチの側面に沿って形成された第1導電型のエミッタ領域(14)と、を有し、
前記上部電極が前記ベース層および前記エミッタ領域に接続されていると共に、前記下部電極が前記コレクタ層に接続されている請求項1ないし4ののいずれか1つに記載の半導体装置。 - 前記縦型半導体素子はIGBTおよびフリーホイールダイオードであり、
前記半導体層は、前記セル領域のうち前記IGBTが形成されたIGBT領域(1a)と前記フリーホイールダイオードが形成されたダイオード領域(1b)の双方に形成され、
前記IGBT形成領域では、
前記半導体層を第2導電型のコレクタ層(21)とし、前記第2導電型領域をベース層(12)として、
前記ベース層よりも深く形成されたトレンチ(13)の表面にゲート絶縁膜(16)を介してゲート電極(17)が形成されたトレンチゲート構造と、
前記ベース層の表層部に前記トレンチの側面に沿って形成された第1導電型のエミッタ領域(14)と、を有し、
前記上部電極が前記ベース層および前記エミッタ領域に接続されていると共に、前記下部電極が前記コレクタ層に接続されており、
前記ダイオード領域では、
前記半導体層を第1導電型のカソード層(22)とし、前記第2導電型領域をアノードとして、
前記上部電極が前記アノードに接続され、前記下部電極が前記カソード層に接続されている請求項1ないし4のいずれか1つに記載の半導体装置。 - 前記縦型半導体素子はダイオードであり、
前記半導体層を第1導電型のカソード層(22)とし、前記第2導電型領域をアノードとして、
前記上部電極が前記アノードに接続され、前記下部電極が前記カソード層に接続されている請求項1ないし4のいずれか1つに記載の半導体装置。
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Cited By (9)
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WO2019098271A1 (ja) * | 2017-11-16 | 2019-05-23 | 富士電機株式会社 | 半導体装置 |
JP2019134069A (ja) * | 2018-01-31 | 2019-08-08 | 三菱電機株式会社 | 半導体装置、電力変換装置及び半導体装置の製造方法 |
WO2020012605A1 (ja) * | 2018-07-12 | 2020-01-16 | 三菱電機株式会社 | 半導体装置及び半導体装置の製造方法 |
JP2021028930A (ja) * | 2019-08-09 | 2021-02-25 | 富士電機株式会社 | 半導体装置 |
JPWO2020149354A1 (ja) * | 2019-01-18 | 2021-09-09 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
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JP6652515B2 (ja) * | 2017-02-09 | 2020-02-26 | 株式会社東芝 | 半導体装置 |
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