JP2022035157A - 半導体装置および半導体装置の製造方法 - Google Patents
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Abstract
Description
図1は、実施の形態1に係る半導体装置を示す平面図であり、絶縁ゲート型バイポーラトランジスタ(IGBT:Insulated Gate Bipolar Transistor)である半導体装置を示す。
図16を用いて実施の形態1の変形例に係る半導体装置の構成を説明する。図16は実施の形態1の変形例に係る半導体装置を示す図である。なお、実施の形態1の変形例において、実施の形態1で説明したものと同一の構成要素については同一符号を付して説明は省略する。
図18を用いて実施の形態2に係る半導体装置の構成を説明する。図18は実施の形態2に係る半導体装置を示す図である。なお、実施の形態2において、実施の形態1で説明したものと同一の構成要素については同一符号を付して説明は省略する。
2 n型キャリア蓄積層
3 n型バッファ層
4 層間絶縁膜
5 バリアメタル
6 エミッタ電極
7 コレクタ電極
10 セル領域
11 アクティブトレンチゲート
11a ゲートトレンチ電極
11b ゲートトレンチ絶縁膜
11c アクティブトレンチゲートの底面
11d アクティブトレンチゲートの側壁
12 ダミートレンチゲート
12a ダミートレンチ電極
12b ダミートレンチ絶縁膜
13 n+型エミッタ層
14 p+型コンタクト層
15 p型ベース層
16 p型コレクタ層
19 コンタクトホール
20 高抵抗層
21 ダイオードトレンチゲート
21a ダイオードトレンチ電極
21b ダイオードトレンチ絶縁膜
21c ダイオードトレンチゲートの底面
21d ダイオードトレンチゲートの側壁
24 p+型コンタクト層
25 p型アノード層
26 n+型カソード層
27 アノード電極
28 カソード電極
30 終端領域
31 p型終端ウェル層
40 パッド領域
41 制御パッド
Claims (19)
- 第1主面と前記第1主面に対向する第2主面との間に第1導電型のドリフト層を有する半導体基板と、
前記ドリフト層と前記第2主面との間に前記ドリフト層に接して設けられ、前記ドリフト層より抵抗率が小さく、前記ドリフト層より高い不純物濃度を有する第1導電型の第1バッファ層と、
前記第1バッファ層と前記第2主面との間に設けられ、抵抗率が前記ドリフト層より大きい高抵抗層と、
を備えた半導体装置。 - 前記第2主面と前記高抵抗層との間に設けられ、前記ドリフト層より高い不純物濃度を有する第1導電型の第2バッファ層を備えた請求項1に記載の半導体装置。
- 前記高抵抗層よりも第2主面側に第2導電型のコレクタ層を備えた請求項1または2に記載の半導体装置。
- 前記ドリフト層の前記第1主面側に接して設けられた第2導電型のアノード層と、前記高抵抗層よりも第2主面側に設けられた第1導電型のカソード層と、
を備えた請求項1または2に記載の半導体装置。 - 前記高抵抗層の前記第2主面から前記第1主面に向かう方向の厚みは3μm以上の厚みである請求項1から4のいずれか1項に記載の半導体装置。
- 前記高抵抗層の抵抗率は、10Ωcm~1000Ωcmである請求項1から5のいずれか1項に記載の半導体装置。
- 前記第1バッファ層の前記第2主面から前記第1主面に向かう深さにおける抵抗率を示した抵抗率分布曲線は、複数の抵抗率のボトムを有する請求項1から6のいずれか1項に記載の半導体装置。
- 前記第1バッファ層の第1導電型不純物はプロトンである請求項1から7のいずれか1項に記載の半導体装置。
- 前記第2バッファ層の第1導電型不純物はリンまたはヒ素である請求項2から8のいずれか1項に記載の半導体装置。
- 第1主面と前記第1主面に対向する第2主面との間に第1導電型のドリフト層を有する半導体基板を用意する工程と、
前記半導体基板に前記第2主面から前記第1主面に向かう深さ方向へ第1導電型不純物の注入を行う第1注入工程と、
前記第1導電型不純物を熱処理にて拡散させて前記ドリフト層よりも低い抵抗率である第1バッファ層を形成し、前記第1バッファ層と前記第2主面との間には前記第1導電型不純物を拡散させず前記ドリフト層より高い抵抗率である高抵抗層を形成する熱処理工程と、
を備えた半導体装置の製造方法。 - 前記第1バッファ層に注入される第1導電型不純物はプロトンである請求項10に記載の半導体装置の製造方法。
- 前記第1注入工程で、加速エネルギーが500KeV以上であって、前記プロトンの注入量が7×1012cm-2未満である請求項11に記載の半導体装置の製造方法。
- 前記第1注入工程で、加速エネルギーが1000KeV以上であって、前記プロトンの注入量が5×1013cm-2未満である請求項12に記載の半導体装置の製造方法。
- 前記第1注入工程で、加速エネルギーが1500KeV以上であって、前記プロトンの注入量が1×1014cm-2未満である請求項13に記載の半導体装置の製造方法。
- 前記第1注入工程で、加速エネルギーが2000KeV以上であって、前記プロトンの注入量が3×1015cm-2未満である請求項14に記載の半導体装置の製造方法。
- 前記第2主面と前記高抵抗層との間に第1導電型不純物の注入により第2バッファ層を形成する第2注入工程を備えた請求項11から15のいずれか1項に記載の半導体装置の製造方法。
- 前記第2バッファ層に注入される第1導電型不純物はリンまたはヒ素である請求項11から16のいずれか1項に記載の半導体装置の製造方法。
- 前記第2注入工程で、前記第2バッファ層に注入される第1導電型不純物がリンであり、加速エネルギーが1000KeV以下であって、前記リンの注入量が1×1012cm-2以上 1×1013cm-2以下である請求項11から17のいずれか1項に記載の半導体装置の製造方法。
- 前記熱処理工程の熱処理温度は350℃以上450℃以下である請求項11から18のいずれか1項に記載の半導体装置の製造方法。
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