CN111066148B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN111066148B
CN111066148B CN201780094516.9A CN201780094516A CN111066148B CN 111066148 B CN111066148 B CN 111066148B CN 201780094516 A CN201780094516 A CN 201780094516A CN 111066148 B CN111066148 B CN 111066148B
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大佐贺毅
阿多保夫
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Mitsubishi Electric Corp
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Abstract

半导体装置(10)在N—型漂移层(1)的上表面侧具有P型阱层(2)、N型发射极层(3)、栅极绝缘膜(4)以及栅极电极(5a、5b)，在N—型漂移层(1)的下表面侧具有N型缓冲层(6)、P型集电极层(7)、N++型层(8)。N++型层(8)在N型缓冲层(6)内局部地形成。N++型层(8)的杂质浓度高于N型缓冲层(6)的杂质浓度，并且N++型层(8)具有大于或等于P型集电极层(7)的杂质浓度的杂质浓度。

Description

半导体装置
技术领域
本发明涉及半导体装置，特别涉及轻穿通型的绝缘栅双极型晶体管(InsulatedGate Bipolar Transistor：IGBT)。
背景技术
作为用于逆变器等电力转换装置的半导体装置，广泛使用IGBT。近年来，电力转换装置的大容量化以及高电流密度化的要求提高，对IGBT的元件构造进行了改良。例如，在下述专利文献1中公开了在IGBT的P型集电极层和N型缓冲层的边界部分形成有杂质浓度比N型缓冲层高的N++型区域的构造。通过该构造，能够降低IGBT的通断动作时的电力损耗。
专利文献1：日本特开平9-307104号公报
发明内容
通常，为了增大逆变器的额定电流，使多个IGBT元件并联连接。在该情况下，如果存在各IGBT元件的导通电压的波动，则流过各IGBT元件的电流产生偏差，电流集中于特定的IGBT元件，该IGBT元件有可能损坏。因此，并联连接的多个IGBT元件需要特性的波动小。
特别地，在并联连接的多个IGBT元件具有导通电压随着温度的上升而下降的特性(即，导通电压具有负的温度系数)的情况下，在各IGBT元件的温度产生波动时容易引起电流集中，这成为逆变器的大容量化的障碍。
在为了抑制电流集中，使IGBT元件的导通电压具有正的温度系数的情况下，通常需要降低P型集电极层的杂质浓度，抑制来自下表面侧(集电极层侧)的空穴的注入。但是，如果降低P型集电极层的杂质浓度，则产生在短路动作时可切断电流值降低这样的问题。
本发明是为了解决上述课题而提出的，目的在于提供一种能够抑制在并联连接时电流向特定的元件集中的半导体装置。
本发明涉及的半导体装置具有：N—型漂移层；P型阱层，其形成于所述N—型漂移层的上表面侧的表层部；N型发射极层，其形成于所述P型阱层的表层部；栅极电极，它们在形成有所述N—型漂移层、所述P型阱层以及所述N型发射极层的半导体层的上表面侧形成；N型缓冲层，其形成于所述N—型漂移层的下表面侧；P型集电极层，其形成于所述N型缓冲层的下表面侧；以及N++型层，其局部地形成于所述N型缓冲层内，杂质浓度高于所述N型缓冲层的杂质浓度，并且具有大于或等于所述P型集电极层的杂质浓度的杂质浓度。
发明的效果
根据本发明，通过N++型层，抑制了从半导体装置的下表面侧注入的空穴的量，由此交叉点电流值变低。因此，在并联连接了多个半导体装置的状态下，即使特定的半导体装置由于电流集中而发热，也会向流过该半导体装置的电流施加负反馈，因此能够防止因电流集中而引起的损坏。另外，通过使N++型层的杂质浓度大于或等于P型集电极层的杂质浓度，从而即使形成N++型层时的杂质的注入量产生波动，也能够使半导体装置的导通电压稳定。
本发明的目的、特征、方案以及优点通过下面的详细说明和附图变得更加明确。
附图说明
图1是表示实施方式1涉及的半导体装置的构造的剖面图。
图2是用于说明交叉点电流值的定义的图。
图3是表示实施方式1涉及的半导体装置的杂质浓度分布的一个例子的图。
图4是表示实施方式1涉及的半导体装置的杂质浓度分布的一个例子的图。
图5是表示半导体装置的交叉点电流值与短路动作时的半导体装置的背面附近的电场强度之间的关系的图。
图6是表示实施方式2涉及的半导体装置的构造的剖面图。
图7是表示将本发明应用于平面栅型IGBT的情况下的结构的剖面图。
具体实施方式
＜实施方式1＞
图1是表示本发明的实施方式1涉及的半导体装置10的构造的剖面图。该半导体装置10是轻穿通型的沟槽栅型IGBT。
半导体装置10具有例如由硅衬底等半导体层构成的N—型漂移层1，在N—型漂移层1的表层部形成有P型阱层2。在P型阱层2的表层部局部地形成有N型发射极层3。这里，对于形成有N—型漂移层1、P型阱层2以及N型发射极层3的半导体层，将形成有P型阱层2以及N型发射极层3这一侧的面定义为“上表面”，将其相反侧的面定义为“下表面”或者“背面”。
在形成有N—型漂移层1、P型阱层2以及N型发射极层3的半导体层的上表面侧，隔着栅极绝缘膜4形成有栅极电极5a、5b。由于本实施方式的半导体装置10是沟槽栅型IGBT，所以在该半导体层形成有贯穿P型阱层2的多个沟槽，在各沟槽内隔着栅极绝缘膜4形成有栅极电极5a或者5b。即，栅极电极5a、5b具有从P型阱层2的上表面到达至N—型漂移层1的深度。在N—型漂移层1的下表面侧形成有N型缓冲层6。并且，在N型缓冲层6的下表面侧形成有P型集电极层7。
栅极电极5a形成于贯穿N型发射极层3的沟槽内。即，栅极电极5a以跨N型发射极层3、N型发射极层3之下的P型阱层2和P型阱层2之下的N—型漂移层1而与它们隔着栅极绝缘膜4相对的方式延伸。如果对栅极电极5a施加大于或等于阈值电压的电压，则在N型发射极层3之下的P型阱层2形成使N型发射极层3与N—型漂移层1之间导通的沟道，IGBT单元成为导通状态。
另一方面，栅极电极5b形成于将P型阱层2的没有N型发射极层3的部分贯穿的沟槽内。即，栅极电极5b并非是隔着栅极绝缘膜4与N型发射极层3相对。因此，配置有栅极电极5b的单元不作为IGBT起作用。下面，将配置有栅极电极5b的单元(不具有N型发射极层3的单元)称为“哑单元”，将栅极电极5b称为“哑栅极电极”。
这里，作为用于定量地对IGBT元件的导通电压的温度系数的正负进行评价的指标，定义了“交叉点电流值”(ICP)。交叉点电流值被定义为在常温时(例如25℃)和高温时(例如150℃)导通电压相同的电流值。
在图2中示出常温时(25℃)以及高温时(150℃)的IGBT的导通电压VCE(集电极-发射极间电压)与集电极电流IC之间的关系。如图2所示，在集电极电流IC等于交叉点电流值ICP时，导通电压VCE在常温时和高温时相等。在集电极电流IC大于交叉点电流值ICP时，导通电压VCE在高温时比常温时高，在集电极电流IC小于交叉点电流值ICP时，导通电压VCE在高温时比常温时低。
在本实施方式中，将半导体装置10的交叉点电流值设定为低于额定电流的值。在该情况下，在并联连接了多个半导体装置10的状态下，如果特定的半导体装置10因电流集中而发热，则向流过该半导体装置10的电流施加负反馈，因此能够防止因电流集中而引起的损坏。通过抑制从半导体装置10的下表面侧(P型集电极层7侧)注入的空穴，从而能够降低交叉点电流值。
下面，说明半导体装置10的形成方法。首先，在由硅衬底等构成的N—型漂移层1的上表面侧形成P型阱层2、N型发射极层3、栅极绝缘膜4、栅极电极5a以及哑栅极电极5b等。上述形成方法只要与公知技术相同即可，因此省略详细的说明。
然后，在N—型漂移层1的下表面侧离子注入例如P(磷)，由此形成N型缓冲层6。接着，通过使用照相制版技术实现的选择性离子注入将P追加注入至N型缓冲层6的下表面侧，由此在N型缓冲层6的一部分形成N++型层8。然后，通过在N—型漂移层1的下表面侧离子注入例如B(硼)，从而形成P型集电极层7。
形成N++型层8的P的离子注入时的加速能量低于形成N型缓冲层6的P的离子注入时的加速能量，并且高于形成P型集电极层7的B的离子注入时的加速能量。由此，N++型层8形成于N型缓冲层6与P型集电极层7的边界附近。另外，用于形成N++型层8的P的注入量(剂量)与用于形成P型集电极层7的B的注入量相等或者比其多。即，使N++型层8的杂质浓度大于或等于P型集电极层7的杂质浓度。
在图3以及图4中示出半导体装置10的杂质浓度分布的一个例子。图3示出沿着图1的A1-A2线的剖面、即没有形成N++型层8的区域处的N—型漂移层1、N型缓冲层6以及P型集电极层7的剖面的杂质浓度分布。图4示出沿着图1的B1-B2线的剖面、即形成了N++型层8的区域处的N—型漂移层1、N型缓冲层6以及P型集电极层7的剖面的杂质浓度分布。在该例中，如图4所示，使N++型层8的杂质浓度大于P型集电极层7的杂质浓度。
在形成了N型缓冲层6、P型集电极层7、N++型层8之后，通过对N—型漂移层1的下表面侧实施激光退火等激活处理，从而使N型缓冲层6、P型集电极层7以及N++型层8层激活。其结果，得到图1所示的半导体装置10。
如本实施方式所示，通过在N型缓冲层6内局部地形成N++型层8，从而能够抑制在半导体装置10的导通动作时从P型集电极层7侧注入的空穴的量，降低半导体装置10的交叉点电流值。通过使半导体装置10的交叉点电流值低于额定电流，从而在并联连接了多个半导体装置10时，即使特定的半导体装置10因电流集中而发热，也会向流过该半导体装置10的电流施加负反馈，防止因电流集中而引起的损坏。另外，由于抑制了半导体装置10的芯片温度的不均衡，所以并联连接时的芯片温度更稳定。另外，通过使N++型层8的杂质浓度大于或等于P型集电极层7的杂质浓度，从而即使形成N++型层8时的P的注入量产生波动，也能够使半导体装置10的导通电压稳定。
图5是表示半导体装置10的交叉点电流值(将常温设定为25℃，高温设定为150℃)和常温下的短路动作时的半导体装置10的背面附近(N型缓冲层6的附近)的电场强度之间的关系的模拟结果。在图5中，为了比较，还示出了以往构造(与图1相比省略了N++型层8的构造)的模拟结果。如果半导体装置10的背面侧的电场强度增大，则有可能无法切断短路电流、芯片损坏，但就本实施方式涉及的半导体装置10而言，通过在背面侧设置有N++型层8，从而与以往构造相比，能够一边抑制背面侧的电场强度的增大一边降低交叉点电流值。
另外，通过使形成N++型层8的P的离子注入时的加速能量高于形成P型集电极层7的B的离子注入时的加速能量，从而使P型集电极层7形成于半导体装置10的整个背面。由此，能够将P型集电极层7与例如由Al(铝)形成的背面电极(集电极(collector)电极(electrode))之间的连接设为低电阻的欧姆结，能够抑制导通电压的增加。
＜实施方式2＞
图6是表示实施方式2涉及的半导体装置10的构造的剖面图。在图6中，对于与图1所示的要素相同的要素标注与图1相同的标号。
如图6所示，就实施方式2的半导体装置10而言，N++型层8未形成于具有N型发射极层3的IGBT单元，而仅形成于不具有N型发射极层3的哑单元(具有哑栅极电极5b的单元)。由此，N++型层8以避开N型发射极层3的正下方的区域的方式配置。
在半导体装置10的导通动作时，在N型发射极层3的正下方的区域电子电流变多，但通过以避开N型发射极层3的正下方的区域的方式配置N++型层8，从而抑制半导体装置10的短路动作时的背面附近的电场强度。由此，得到半导体装置10的短路动作时的可切断电流变大的效果。
在图6中，虽然仅在哑单元内形成了N++型层8，但也可以是N++型层8以不到达至N型发射极层3的正下方的区域的程度延伸至哑单元的外侧。
另外，在上述说明中，作为N—型漂移层1的材料的例子，举出了硅，但不限定于此，例如也可以将碳化硅、氮化镓类材料、金刚石等宽带隙半导体作为N—型漂移层1的材料。
另外，在图1以及图6中，示出了将本发明应用于沟槽栅型IGBT的例子，但本发明不限定于向沟槽栅型IGBT的应用，也能够应用于平面栅型IGBT。例如，在图7中示出将上述的实施方式2应用于平面栅型IGBT的情况下的结构。即，在图7中，在具有N型发射极层3的IGBT单元未形成N++型层8，仅在不具有N型发射极层3的哑单元(具有哑栅极电极5b的单元)形成N++型层8。此外，在图7中，对于与图6所示的要素相同的要素标注与图6相同的标号。
在图7中，栅极电极5a以及哑栅极电极5b在形成有N—型漂移层1、P型阱层2以及N型发射极层3的半导体层的上表面之上平面状地形成。其中的栅极电极5a以跨N型发射极层3、与该N型发射极层3相邻的P型阱层2、与该P型阱层2相邻的N—型漂移层1而与它们隔着栅极绝缘膜4相对的方式延伸。另一方面，哑栅极电极5b跨P型阱层2的没有N型发射极层3的部分和与其相邻的N—型漂移层1而形成。即，哑栅极电极5b并非是隔着栅极绝缘膜4与N型发射极层3相对。
通常，沟槽栅型IGBT具有集成度高、能够高电流密度化的优点，但由于例如半导体装置的封装尺寸有富余、与高集成化相比更重视芯片的散热性等理由，有时使用平面栅型IGBT。即使在将本发明应用于平面栅型IGBT的情况下，也会得到与应用于沟槽栅型IGBT的情况相同的效果。
在图7中示出了将实施方式2应用于平面栅型IGBT的例子，但是实施方式1当然也能够应用于平面栅型IGBT。即，在将本发明应用于平面栅型IGBT的情况下，也可以将N++型层8的一部分形成于具有N型发射极层3的IGBT单元。
此外，本发明在其发明范围内能够自由地对各实施方式进行组合，或者适当地对各实施方式进行变形、省略。
虽然详细地说明了本发明，但上述说明在所有方面都是例示，本发明并不限定于此。可以理解为在不脱离本发明的范围的情况下能够想到未例示的无数变形例。
标号的说明
10半导体装置，1N—型漂移层，2P型阱层，3N型发射极层，4栅极绝缘膜，5a栅极电极，5b哑栅极电极，6N型缓冲层，7P型集电极层，8N++型层。

Claims (2)

1.一种半导体装置(10)，其特征在于，具有：
N—型漂移层(1)；
P型阱层(2)，其形成于所述N—型漂移层(1)的上表面侧的表层部；
N型发射极层(3)，其形成于所述P型阱层(2)的表层部；
栅极电极(5a、5b)，它们在形成有所述N—型漂移层(1)、所述P型阱层(2)以及所述N型发射极层(3)的半导体层的上表面侧形成；
N型缓冲层(6)，其形成于所述N—型漂移层(1)的下表面侧；
P型集电极层(7)，其形成于所述N型缓冲层(6)的下表面侧；以及
N++型层(8)，其局部地形成于所述N型缓冲层(6)内，杂质浓度高于所述N型缓冲层(6)的杂质浓度，并且具有大于或等于所述P型集电极层(7)的杂质浓度的杂质浓度，
所述N++型层(8)以避开所述N型发射极层(3)的正下方的区域的方式配置。
2.一种半导体装置(10)，其特征在于，具有：
N—型漂移层(1)；
P型阱层(2)，其形成于所述N—型漂移层(1)的上表面侧的表层部；
N型发射极层(3)，其形成于所述P型阱层(2)的表层部；
栅极电极(5a、5b)，它们在形成有所述N—型漂移层(1)、所述P型阱层(2)以及所述N型发射极层(3)的半导体层的上表面侧形成；
N型缓冲层(6)，其形成于所述N—型漂移层(1)的下表面侧；
P型集电极层(7)，其形成于所述N型缓冲层(6)的下表面侧；以及
N++型层(8)，其局部地形成于所述N型缓冲层(6)内，杂质浓度高于所述N型缓冲层(6)的杂质浓度，并且具有大于或等于所述P型集电极层(7)的杂质浓度的杂质浓度，
所述半导体装置(10)包含：
单元，其具有隔着绝缘膜与所述栅极电极(5a)相对的所述N型发射极层(3)；以及
哑单元，其不具有隔着绝缘膜与所述栅极电极(5b)相对的所述N型发射极层(3)，
所述N++型层(8)仅形成于所述哑单元内。
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