JP2019134069A - 半導体装置、電力変換装置及び半導体装置の製造方法 - Google Patents
半導体装置、電力変換装置及び半導体装置の製造方法 Download PDFInfo
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Abstract
Description
図1は、実施の形態1に係る半導体装置を示す断面図である。この半導体装置はCSTBTである。n−型半導体基板1は、トランジスタ構造が形成されるMOS領域と、耐圧を保持するためにMOS領域の外周に配置された外周領域と、両者の間に配置された配線領域とを有する。
本実施の形態は、上述した実施の形態1にかかる半導体装置を電力変換装置に適用したものである。電力変換装置は、例えば、インバータ装置、コンバータ装置、サーボアンプ、電源ユニットなどである。本発明は特定の電力変換装置に限定されるものではないが、以下、三相のインバータに本発明を適用した場合について説明する。
Claims (12)
- n型半導体基板と、
前記n型半導体基板の表面に形成されたp型ベース層と、
前記p型ベース層の上に形成されたn型エミッタ層と、
前記p型ベース層及び前記n型エミッタ層を貫通するトレンチゲートと、
前記n型半導体基板と前記p型ベース層の間に形成され、前記n型半導体基板より濃度が高いn型キャリア蓄積層と、
前記n型半導体基板の裏面に形成されたp型コレクタ層とを備え、
前記n型キャリア蓄積層は、ピーク濃度の位置から前記p型ベース層に向かう濃度勾配よりも、前記ピーク濃度の位置から前記n型半導体基板の裏面側に向かう濃度勾配の方が大きく、不純物としてプロトンが注入されていることを特徴とする半導体装置。 - 前記n型キャリア蓄積層の深さは前記トレンチゲートよりも浅いことを特徴とする請求項1に記載の半導体装置。
- 前記n型半導体基板は、前記p型ベース層、前記n型エミッタ層、前記トレンチゲートが形成されたMOS領域と、耐圧を保持するために前記MOS領域の外周に配置された外周領域とを有し、
前記n型キャリア蓄積層は前記MOS領域に形成され、前記外周領域には形成されていないことを特徴とする請求項1又は2に記載の半導体装置。 - 前記n型半導体基板はワイドバンドギャップ半導体によって形成されていることを特徴とする請求項1〜3の何れか1項に記載の半導体装置。
- 請求項1〜4の何れか1項に記載の半導体装置を有し、入力される電力を変換して出力する主変換回路と、
前記主変換回路を制御する制御信号を前記主変換回路に出力する制御回路とを備えることを特徴とする電力変換装置。 - n型半導体基板の表面にp型ベース層を形成する工程と、
前記p型ベース層の上にn型エミッタ層を形成する工程と、
前記p型ベース層及び前記n型エミッタ層を貫通するトレンチゲートを形成する工程と、
プロトンを注入することにより、前記n型半導体基板と前記p型ベース層の間に、前記n型半導体基板より濃度が高いn型キャリア蓄積層を形成する工程と、
前記n型半導体基板の裏面にp型コレクタ層を形成する工程とを備え、
前記n型キャリア蓄積層は、ピーク濃度の位置から前記p型ベース層に向かう濃度勾配よりも、前記ピーク濃度の位置から前記n型半導体基板に向かう濃度勾配の方が大きいことを特徴とする半導体装置の製造方法。 - 前記n型キャリア蓄積層の深さを前記トレンチゲートよりも浅くすることを特徴とする請求項6に記載の半導体装置の製造方法。
- 前記n型半導体基板は、前記p型ベース層、前記n型エミッタ層、前記トレンチゲートが形成されたMOS領域と、耐圧を保持するために前記MOS領域の外周に配置された外周領域とを有し、
前記n型キャリア蓄積層を前記MOS領域に形成し、前記外周領域には形成しないことを特徴とする請求項6又は7に記載の半導体装置の製造方法。 - 前記外周領域において前記n型半導体基板の前記表面にポリイミドを形成し、前記ポリイミドをマスクにして前記MOS領域に前記プロトンを注入することを特徴とする請求項8に記載の半導体装置の製造方法。
- 前記プロトンを600〜1100keVで注入し、
前記ポリイミドの膜厚は3um以上であることを特徴とする請求項9に記載の半導体装置の製造方法。 - 前記プロトンのドナー化を350〜450℃の熱処理で実施することを特徴とする請求項6〜10の何れか1項に記載の半導体装置の製造方法。
- 前記p型ベース層及び前記トレンチゲートの形成後に前記n型キャリア蓄積層を形成することを特徴とする請求項6〜11の何れか1項に記載の半導体装置の製造方法。
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DE102017129955B4 (de) * | 2017-12-14 | 2021-10-07 | Infineon Technologies Austria Ag | Halbleitervorrichtung mit einem barrierengebiet sowie elektrische vorrichtung |
JP6946219B2 (ja) * | 2018-03-23 | 2021-10-06 | 株式会社東芝 | 半導体装置 |
CN113519062A (zh) * | 2019-09-13 | 2021-10-19 | 富士电机株式会社 | 半导体装置 |
CN111863607B (zh) * | 2020-07-28 | 2023-05-05 | 哈尔滨工业大学 | 一种抗辐射功率晶体管及其制备方法 |
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Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09260639A (ja) * | 1996-03-27 | 1997-10-03 | Hitachi Ltd | シリコン半導体装置の製造方法 |
JP2007311627A (ja) * | 2006-05-19 | 2007-11-29 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
JP2008091853A (ja) * | 2006-09-07 | 2008-04-17 | Fuji Electric Device Technology Co Ltd | 半導体装置およびその製造方法 |
JP2014007254A (ja) * | 2012-06-22 | 2014-01-16 | Sanken Electric Co Ltd | 半導体装置及びその製造方法 |
JP2014165306A (ja) * | 2013-02-25 | 2014-09-08 | Fuji Electric Co Ltd | 超接合半導体装置の製造方法 |
WO2014199465A1 (ja) * | 2013-06-12 | 2014-12-18 | 三菱電機株式会社 | 半導体装置 |
JP2017135339A (ja) * | 2016-01-29 | 2017-08-03 | 株式会社デンソー | 半導体装置 |
WO2017187670A1 (ja) * | 2016-04-27 | 2017-11-02 | 三菱電機株式会社 | 半導体装置および電力変換装置 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3435635B2 (ja) | 1999-10-27 | 2003-08-11 | 株式会社豊田中央研究所 | 絶縁ゲート型半導体装置、およびその製造方法ならびにインバータ回路 |
JP2004022941A (ja) | 2002-06-19 | 2004-01-22 | Toshiba Corp | 半導体装置 |
JP5089191B2 (ja) * | 2007-02-16 | 2012-12-05 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JP5443670B2 (ja) * | 2007-02-20 | 2014-03-19 | 株式会社豊田中央研究所 | 半導体装置とその製造方法 |
CN103999225B (zh) * | 2012-01-19 | 2017-02-22 | 富士电机株式会社 | 半导体装置及其制造方法 |
US10411111B2 (en) * | 2012-05-30 | 2019-09-10 | Kyushu Institute Of Technology | Method for fabricating high-voltage insulated gate type bipolar semiconductor device |
US9941269B2 (en) * | 2014-01-29 | 2018-04-10 | Mitsubishi Electric Corporation | Power semiconductor device including well extension region and field-limiting rings |
CN103956379B (zh) * | 2014-05-09 | 2017-01-04 | 常州中明半导体技术有限公司 | 具有优化嵌入原胞结构的cstbt器件 |
US9520798B2 (en) * | 2014-08-26 | 2016-12-13 | General Electric Company | Multi-level DC-DC converter with galvanic isolation and adaptive conversion ratio |
CN106463528B (zh) * | 2014-11-17 | 2019-10-11 | 富士电机株式会社 | 碳化硅半导体装置的制造方法 |
DE112015006006T5 (de) * | 2015-01-14 | 2017-10-26 | Mitsubishi Electric Corporation | Halbleitervorrichtung und verfahren zum herstellen dieser |
JP6720569B2 (ja) * | 2015-02-25 | 2020-07-08 | 株式会社デンソー | 半導体装置 |
JP6299816B2 (ja) | 2016-07-26 | 2018-03-28 | サミー株式会社 | 遊技機 |
-
2018
- 2018-01-31 JP JP2018015163A patent/JP7143085B2/ja active Active
- 2018-08-22 US US16/108,114 patent/US10916631B2/en active Active
- 2018-10-16 DE DE102018217675.2A patent/DE102018217675A1/de active Pending
-
2019
- 2019-01-25 CN CN201910072862.8A patent/CN110098253B/zh active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09260639A (ja) * | 1996-03-27 | 1997-10-03 | Hitachi Ltd | シリコン半導体装置の製造方法 |
JP2007311627A (ja) * | 2006-05-19 | 2007-11-29 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
JP2008091853A (ja) * | 2006-09-07 | 2008-04-17 | Fuji Electric Device Technology Co Ltd | 半導体装置およびその製造方法 |
JP2014007254A (ja) * | 2012-06-22 | 2014-01-16 | Sanken Electric Co Ltd | 半導体装置及びその製造方法 |
JP2014165306A (ja) * | 2013-02-25 | 2014-09-08 | Fuji Electric Co Ltd | 超接合半導体装置の製造方法 |
WO2014199465A1 (ja) * | 2013-06-12 | 2014-12-18 | 三菱電機株式会社 | 半導体装置 |
JP2017135339A (ja) * | 2016-01-29 | 2017-08-03 | 株式会社デンソー | 半導体装置 |
WO2017187670A1 (ja) * | 2016-04-27 | 2017-11-02 | 三菱電機株式会社 | 半導体装置および電力変換装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7462587B2 (ja) | 2021-03-25 | 2024-04-05 | 三菱電機株式会社 | 半導体装置の製造方法 |
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