CN110246887B - 半导体装置及电力变换装置 - Google Patents

半导体装置及电力变换装置 Download PDF

Info

Publication number
CN110246887B
CN110246887B CN201910155859.2A CN201910155859A CN110246887B CN 110246887 B CN110246887 B CN 110246887B CN 201910155859 A CN201910155859 A CN 201910155859A CN 110246887 B CN110246887 B CN 110246887B
Authority
CN
China
Prior art keywords
layer
semiconductor layer
impurity concentration
type impurity
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910155859.2A
Other languages
English (en)
Other versions
CN110246887A (zh
Inventor
藤井秀纪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to CN202210555566.5A priority Critical patent/CN114864700A/zh
Publication of CN110246887A publication Critical patent/CN110246887A/zh
Application granted granted Critical
Publication of CN110246887B publication Critical patent/CN110246887B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/145—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
    • H02M7/155—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
    • H02M7/1555—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only with control circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41716—Cathode or anode electrodes for thyristors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Inverter Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thyristors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

本发明目在于提供能够在确保耐压的同时，抑制恢复时的峰值电流的技术。半导体装置具备：p‑型阳极层(1)，其p型杂质浓度是恒定的；n‑型层(2)，其n型杂质浓度具有分布；以及n+型层(3)，其是与p‑型阳极层(1)之间夹着n‑型层(2)而配置的，n型杂质浓度比n‑型层(2)高且是恒定的，n‑型层(2)中的p‑型阳极层(1)侧的部分的n型杂质浓度比p‑型阳极层(1)的p型杂质浓度低。

Description

半导体装置及电力变换装置
技术领域
本发明涉及具有阳极层的半导体装置。
背景技术
近年来，为了改善功率半导体装置的性能，在将晶片衬底研磨得薄后，通过从背面进行的杂质扩散而设置了背面扩散层的构造成为主流。例如，在专利文献1的技术中，在n型杂质浓度恒定的n型衬底进行p型杂质的注入及热扩散而形成p型阳极层后，将晶片衬底研磨至所期望的厚度，从背面侧进行质子注入，从而形成n型缓冲层。另外，例如，在专利文献2的技术中，在晶片衬底的最背面形成n型杂质浓度较高的n+层。
专利文献1：国际公开第2016/203545号
专利文献2：日本专利第5309360号公报
但是，在上述技术中，为了确保耐压，需要提高p型阳极层的浓度，使耗尽层从p型阳极层延伸至n-型衬底侧。但是，在这样构成的情况下，存在恢复时的峰值电流较大的问题。
发明内容
因此，本发明就是鉴于上述问题而提出的，其目的在于，提供能够在确保耐压的同时，抑制恢复时的峰值电流的技术。
本发明涉及的半导体装置具备：阳极层，其p型杂质浓度是恒定的；第1半导体层，其n型杂质浓度具有分布；以及第2半导体层，其是与所述阳极层之间夹着所述第1半导体层而配置的，n型杂质浓度比所述第1半导体层高且是恒定的，所述第1半导体层中的所述阳极层侧的部分的n型杂质浓度比所述阳极层的p型杂质浓度低。
发明的效果
根据本发明，具备：阳极层，其p型杂质浓度是恒定的；以及第1半导体层，其n型杂质浓度具有分布。根据这样的结构，能够将由阳极层和第1半导体层构成的pn结设置于从半导体衬底的表面和背面侧算起的深的位置。因此，能够在确保耐压的同时，抑制恢复时的峰值电流。
附图说明
图1是表示关联半导体装置的结构的剖面图。
图2是表示实施方式1涉及的半导体装置的结构的剖面图。
图3是表示实施方式2涉及的半导体装置的结构的剖面图。
图4是表示实施方式3涉及的半导体装置的结构的剖面图。
图5是表示实施方式4涉及的半导体装置的结构的剖面图。
图6是用于说明实施方式4涉及的半导体装置的特性的图。
图7是表示实施方式5涉及的半导体装置的结构的剖面图。
图8是表示实施方式6涉及的半导体装置的结构的剖面图。
图9是表示实施方式7涉及的半导体装置的结构的剖面图。
图10是表示电力变换系统的结构的框图，在该电力变换系统中应用了实施方式8涉及的电力变换装置。
标号的说明
1 p-型阳极层，2 n-型层，3 n+型层，4、5 p-型层，6 p型层，8末端层，201主变换电路，203控制电路。
具体实施方式
<关联半导体装置>
在对本发明的实施方式涉及的半导体装置进行说明前，对与其关联的半导体装置(记为“关联半导体装置”)进行说明。
图1是表示关联半导体装置的剖面结构，以及与其对应的净掺杂浓度、掺杂分布、及电场强度的图。此外，净掺杂浓度是与实际的n型杂质浓度和实际的p型杂质浓度的差相当的有效浓度。
图1的关联半导体装置具备p型阳极层21、n-型层22、n型层23、n+型层24。通过一边对n型杂质浓度恒定的n-型衬底进行适当研磨，一边使用杂质扩散而选择性地形成p型阳极层21、n型层23、以及n+型层24，将n-型衬底的剩余部分作为n-型层22，从而形成关联半导体装置。在这样的结构中，需要以使耗尽层从p型阳极层21延伸至n-型层22侧的方式，提高p型阳极层21的浓度。但是，在这样构成的情况下，存在恢复时的峰值电流较大的问题。相对于此，在下面说明的本发明的实施方式涉及的半导体装置中，能够解决该问题。
<实施方式1>
图2是表示本发明的实施方式1涉及的半导体装置的剖面结构，以及与其对应的净掺杂浓度、掺杂分布、及电场强度的图。此外，图2的半导体装置能够应用于例如RFC二极管(Relaxed Field of Cathode Diode)、RC-IGBT(Reverse Conducting Insulated GateBipolar Transistor)等。
图2的半导体装置具备作为阳极层的p-型阳极层1、作为第1半导体层的n-型层2、作为第2半导体层的n+型层3。此外，在本实施方式1中，p-型阳极层1位于半导体衬底的表面侧，n+型层3位于半导体衬底的背面侧。半导体衬底的材质可以是例如硅(Si)，也可以是碳化硅(SiC)、氮化镓(GaN)、金刚石等宽带隙半导体。另外，各层也能够称为区域。
下面，关于n型杂质浓度及p型杂质浓度，除非明示为实际的杂质浓度，否则是作为净掺杂浓度而进行说明的。
在p-型阳极层1，p型杂质浓度是恒定的。在n-型层2，n型杂质浓度具有分布。具体而言，n-型层2中的p-型阳极层1侧的部分的n型杂质浓度比p-型阳极层1的p型杂质浓度低。在本实施方式1中，n-型层2的所有部分的n型杂质浓度都比p-型阳极层1的p型杂质浓度低。
n+型层3是与p-型阳极层1之间夹着n-型层2而配置的。在n+型层3，n型杂质浓度比n-型层2高且是恒定的。
接着，对本实施方式1涉及的半导体装置的制造方法的一个例子进行说明。
首先，准备p型实际的杂质浓度恒定的半导体衬底，对该半导体衬底进行研磨以使其变为所期望的厚度。之后，将质子、电子束以最大10MeV左右的能量照射或注入至半导体衬底，然后在温度350～500℃、时间30～300分钟的条件下对半导体衬底进行热处理工序。由此，被施主化后的层形成于半导体衬底的较深的部分。这里，对被施主化后的层的n型实际杂质浓度进行设定，以将半导体衬底的p型实际杂质浓度抵消。其结果，形成n型净掺杂浓度比半导体衬底的p型净掺杂浓度低的n-型层2，半导体衬底的与n-型层2相比位于表面侧的没有被施主化的部分变为p-型阳极层1。之后，通过以1E14～1E17[1/cm2]将磷向半导体衬底的背面整面进行离子注入，对半导体衬底进行热处理，从而形成恒定浓度的n+型层3。此时的p-型阳极层1的净掺杂浓度例如是1×1012～1×1014[1/cm3]，n+型层3的净掺杂浓度例如是1×1018～1×1020[1/cm3]。
根据这样构成的本实施方式1涉及的半导体装置，具备：p-型阳极层1，其p型杂质浓度是恒定的；以及n-型层2，其浓度梯度较平缓。根据这样的结构，能够将由p-型阳极层1和n-型层2构成的pn结设置于从半导体衬底的表面和背面侧算起的深的位置(例如图2的半导体装置的深度方向的正中央程度的位置)。因此，能够在确保耐压的同时，减少从p-型阳极层1向n-型层2的空穴注入，进而减小恢复时的峰值电流Irr。另外，由于具备调整了浓度梯度的n-型层2，因此能够进行恢复特性的调整。另外，通过具备n型杂质浓度高且恒定的n+型层3，能够得到抑制恢复时的耗尽层的不必要的延伸、以及降低欧姆接触电阻这两个效果。
<实施方式2>
图3是表示本发明的实施方式2涉及的半导体装置的剖面结构，以及与其对应的净掺杂浓度、及掺杂分布的图。以下，对本实施方式2涉及的结构要素中的与上述结构要素相同或类似的结构要素标注相同的参照标号，主要对不同的结构要素进行说明。
在本实施方式2中，n-型层2中的n+型层3侧的部分的n型杂质浓度比p-型阳极层1的p型杂质浓度高。而且，对浓度赋予梯度，以使得n-型层2的n型杂质浓度随着从p-型阳极层1朝向n+型层3而大致变高。
根据这样构成的本实施方式2涉及的半导体装置，能够得到与实施方式1相同的效果。另外，在本实施方式2中，由于对n-型层2的n型杂质浓度赋予了梯度，因此能够抑制恢复时的耗尽层的不必要的延伸。由此，能够抑制恢复时的通断速度变得过快而产生振荡，能够提高振荡耐量。
<实施方式3>
图4是表示本发明的实施方式3涉及的半导体装置的剖面结构，以及与其对应的净掺杂浓度、及掺杂分布的图。以下，对本实施方式3涉及的结构要素中的与上述结构要素相同或类似的结构要素标注相同的参照标号，主要对不同的结构要素进行说明。
在本实施方式3中，将作为第3半导体层的p-型层4追加于实施方式1的结构。在p-型层4，与p-型阳极层1相同地，p型杂质浓度是恒定的。而且，p-型层4以将n-型层2区分为p-型阳极层1侧的部分和n+型层3侧的部分的方式配置于n-型层2内，成为电位浮动状态。此外，p-型层4的数量可以是1个，也可以如图4那样为多个。
根据这样构成的本实施方式3涉及的半导体装置，能够得到与实施方式1相同的效果。另外，在本实施方式3中，通过处于电位浮动状态的p-型层4，能够调整恢复时的耗尽化所花费的时间及速度。
<实施方式4>
图5是表示本发明的实施方式4涉及的半导体装置的剖面结构，以及与其对应的净掺杂浓度、及掺杂分布的图。以下，对本实施方式4涉及的结构要素中的与上述结构要素相同或类似的结构要素标注相同的参照标号，主要对不同的结构要素进行说明。此外，图5的净掺杂浓度以及掺杂分布是A-A线处的净掺杂浓度以及掺杂分布。B-B线处的净掺杂浓度以及掺杂分布与实施方式1等的净掺杂浓度以及掺杂分布相同。
在本实施方式4中，将作为第3半导体层的p-型层5追加于实施方式1的结构。p-型层5相对于n-型层2配置于与n+型层3相同侧，与n+型层3相邻地配置。而且，在p-型层5，与p-型阳极层1相同地，p型杂质浓度是恒定的。
根据这样构成的本实施方式4涉及的半导体装置，能够得到与实施方式1相同的效果。另外，在本实施方式4中，由于在恢复动作时，在耗尽层到达了背面侧的时刻从背面侧注入空穴，因此能够提高振荡耐量。另外，如图6所示，通过对n+型层3的面积相对于总面积(n+型层3及p-型层5的面积)的比率进行调整，能够实现取得了恢复时的功率损耗和正向电压VF的大小之间的平衡的半导体装置。
<实施方式5>
图7是表示本发明的实施方式5涉及的半导体装置的剖面结构，以及与其对应的净掺杂浓度、及掺杂分布的图。以下，对本实施方式5涉及的结构要素中的与上述结构要素相同或类似的结构要素标注相同的参照标号，主要对不同的结构要素进行说明。
在本实施方式5中，将作为第4半导体层的p型层6追加于实施方式1的结构。p型层6相对于p-型阳极层1配置于与n-型层2相反侧。而且，在p型层6，p型杂质浓度比p-型阳极层1高且具有分布。具体而言，p型层6具有随着向p-型阳极层1而p型杂质浓度接近p-型阳极层1的p型杂质浓度的浓度梯度。此外，p型层6的净掺杂浓度的最大值例如是1×1015～1×1018[1/cm3]，n+型层3的净掺杂浓度例如是1×1018～1×1020[1/cm3]。p型层6的深度例如小于或等于3μm，n+型层3的深度例如小于或等于1μm。
根据这样构成的本实施方式5涉及的半导体装置，能够得到与实施方式1相同的效果。另外，在本实施方式5中，能够降低半导体衬底的表面侧的欧姆接触电阻。
<实施方式6>
图8是表示本发明的实施方式6涉及的半导体装置的剖面结构的图。以下，对本实施方式6涉及的结构要素中的与上述结构要素相同或类似的结构要素标注相同的参照标号，主要对不同的结构要素进行说明。
在本实施方式6中，n-型层2不仅配置于p-型阳极层1的n+型层3侧，还配置于p-型阳极层1的末端侧。n型层7配置于n-型层2和n+型层3之间。末端层8是与p-型阳极层1之间夹着p-型阳极层1的末端侧的n-型层2而配置的。而且，在末端层8，与p-型阳极层1相同地，p型杂质浓度是恒定的。
此外，本实施方式6涉及的半导体装置是由与实施方式1中说明过的制造方法相同的制造方法形成的。例如，以局部抵消p-型阳极层1的方式形成n-型层2，以局部抵消该n-型层2的方式形成末端层8。
根据这样构成的本实施方式6涉及的半导体装置，能够得到与实施方式1相同的效果。另外，在本实施方式6中，通过末端层8能够对末端区域的空穴注入进行限制。因此，能够提高恢复时的安全工作区域(SOA)的耐量。此外，以上使阳极层及末端层为p-型半导体层进行了说明，但并不限于此，也可以是p型半导体层。
<实施方式7>
图9是表示本发明的实施方式7涉及的半导体装置的剖面结构的图。以下，对本实施方式7涉及的结构要素中的与上述结构要素相同或类似的结构要素标注相同的参照标号，主要对不同的结构要素进行说明。
在本实施方式7中，将实施方式4中说明过的p-型层5(图5)追加于实施方式6的结构。根据这样构成的本实施方式7涉及的半导体装置，得到实施方式4中说明过的效果和实施方式6中说明过的效果。
<实施方式8>
本发明的实施方式8涉及的电力变换装置是具备主变换电路的电力变换装置，该主变换电路具有实施方式1～7的任意者涉及的半导体装置。以上说明过的半导体装置不限定于特定的电力变换装置的半导体装置，但下面，作为本实施方式8，对将实施方式1～7的任意者涉及的半导体装置应用于三相逆变器的情况进行说明。
图10是表示电力变换系统的结构的框图，在该电力变换系统中应用了本实施方式8涉及的电力变换装置。
图10所示的电力变换系统由电源100、电力变换装置200、以及负载300构成。电源100为直流电源，将直流电力供给至电力变换装置200。电源100可以由各种电源构成，例如，可以由直流系统、太阳能电池、蓄电池构成，也可以由与交流系统连接的整流电路、AC/DC变换器构成。另外，电源100也可以由将从直流系统输出的直流电力变换为规定的电力的DC/DC变换器构成。
电力变换装置200为在电源100和负载300之间连接的三相逆变器，将从电源100供给的直流电力变换为交流电力，将交流电力供给至负载300。如图10所示，电力变换装置200具备：主变换电路201，其将直流电力变换为交流电力而输出；以及控制电路203，其将对主变换电路201进行控制的控制信号输出至主变换电路201。
负载300为由从电力变换装置200供给的交流电力驱动的三相电动机。此外，负载300并不限于确定的用途，为搭载于各种电气设备的电动机，例如，用作面向混合动力汽车、电动汽车、铁路车辆、电梯、或者空调设备的电动机。
以下，对电力变换装置200的详情进行说明。主变换电路201具备开关元件和续流二极管(未图示)，通过开关元件进行通断，从而将从电源100供给的直流电力变换为交流电力，供给至负载300。主变换电路201的具体的电路结构存在各种结构，但本实施方式8涉及的主变换电路201为2电平的三相全桥电路，能够由6个开关元件和与各个开关元件反并联的6个续流二极管构成。主变换电路201的各开关元件及各续流二极管的至少任意1个由应用了上述实施方式1～7的任意者涉及的半导体装置的半导体模块202构成。6个开关元件两个两个地串联连接而构成上下桥臂，各上下桥臂构成全桥电路的各相(U相、V相、W相)。而且，各上下桥臂的输出端子，即主变换电路201的3个输出端子与负载300连接。
另外，主变换电路201具备对各开关元件进行驱动的驱动电路(未图示)，但也可以将驱动电路内置于半导体模块202，还可以为具备与半导体模块202分开的驱动电路的结构。驱动电路生成对主变换电路201的开关元件进行驱动的驱动信号，供给至主变换电路201的开关元件的控制电极。具体而言，驱动电路按照来自后述的控制电路203的控制信号，将使开关元件成为导通状态的驱动信号和使开关元件成为断开状态的驱动信号输出至各开关元件的控制电极。在将开关元件维持为接通状态的情况下，驱动信号为大于或等于开关元件的阈值电压的电压信号(接通信号)，在将开关元件维持为断开状态的情况下，驱动信号为小于或等于开关元件的阈值电压的电压信号(断开信号)。
控制电路203对主变换电路201的开关元件进行控制以将所期望的电力供给至负载300。具体而言，控制电路203基于应该供给至负载300的电力计算出主变换电路201的各开关元件应该成为导通状态的时间(导通时间)。例如，控制电路203能够通过与应该输出的电压对应地对开关元件的导通时间进行调制的PWM(Pulse Width Modulation)控制，而对主变换电路201进行控制。而且，控制电路203将控制指令(控制信号)输出至主变换电路201所具备的驱动电路，以使得在各时刻将接通信号输出至应该成为接通状态的开关元件，将断开信号输出至应该成为断开状态的开关元件。驱动电路按照该控制信号，将接通信号或断开信号作为驱动信号输出至各开关元件的控制电极。
在以上这样的本实施方式8涉及的电力变换装置中，由于作为主变换电路201的开关元件及续流二极管的至少任意1个，应用实施方式1～7的任意者涉及的半导体装置，因此能够在确保耐压的同时，抑制恢复时的峰值电流。
在以上说明过的本实施方式8中，说明了将实施方式1～7的任意者涉及的半导体装置应用于2电平的三相逆变器的例子，但本实施方式8并不限于此，能够应用于各种电力变换装置。在本实施方式8中，将实施方式1～7的任意者涉及的半导体装置设为2电平的电力变换装置，但也可以是3电平、多电平的电力变换装置，在将电力供给至单相负载的情况下也可以将上述半导体装置应用于单相逆变器。另外，在将电力供给至直流负载等的情况下，也可以将上述半导体装置应用于DC/DC变换器、AC/DC变换器。
另外，本实施方式8涉及的电力变换装置并不限于上述负载为电动机的情况，例如，也能够用作放电加工机、激光加工机、或感应加热烹调器、非接触供电系统的电源装置，并且也能够用作太阳能发电系统、蓄电系统等的功率调节器。
此外，本发明可以在其发明的范围内将各实施方式自由地组合，对各实施方式适当进行变形、省略。

Claims (6)

1.一种半导体装置，其具备：
阳极层，其p型杂质浓度是恒定的；
第1半导体层，其n型杂质浓度具有分布；以及
第2半导体层，其是与所述阳极层之间夹着所述第1半导体层而配置的，n型杂质浓度比所述第1半导体层高且是恒定的，
所述第1半导体层中的所述阳极层侧的部分的n型杂质浓度比所述阳极层的p型杂质浓度低，
所述第1半导体层中的所述第2半导体层侧的部分的n型杂质浓度比所述阳极层的p型杂质浓度高。
2.根据权利要求1所述的半导体装置，其中，
还具有第3半导体层，该第3半导体层与所述第1半导体层中的与所述第2半导体层所接触的面相同的面接触，该第3半导体层是与所述第2半导体层相邻配置的，该第3半导体层的p型杂质浓度是恒定的。
3.一种半导体装置，其具备：
阳极层，其p型杂质浓度是恒定的；
第1半导体层，其n型杂质浓度具有分布；以及
第2半导体层，其是与所述阳极层之间夹着所述第1半导体层而配置的，n型杂质浓度比所述第1半导体层高且是恒定的，
所述第1半导体层中的所述阳极层侧的部分的n型杂质浓度比所述阳极层的p型杂质浓度低，
所述半导体装置还具备第3半导体层，该第3半导体层配置于所述第1半导体层内，将该第1半导体层区分为所述阳极层侧的部分和所述第2半导体层侧的部分，该第3半导体层的p型杂质浓度是恒定的。
4.根据权利要求1或3所述的半导体装置，其中，
还具有第4半导体层，该第4半导体层相对于所述阳极层配置于与所述第1半导体层相反侧，该第4半导体层的p型杂质浓度比所述阳极层高且具有分布。
5.根据权利要求1至3中任一项所述的半导体装置，其中，
所述第1半导体层与所述阳极层的末端侧相邻地配置，
该半导体装置还具备末端层，该末端层是与所述阳极层之间夹着所述阳极层的末端侧的所述第1半导体层而配置的，该末端层的p型杂质浓度是恒定的。
6.一种电力变换装置，其具备：
主变换电路，其具有权利要求1至5中任一项所述的半导体装置，该主变换电路对被输入来的电力进行变换而输出；
控制电路，其将对所述主变换电路进行控制的控制信号输出至所述主变换电路。
CN201910155859.2A 2018-03-08 2019-03-01 半导体装置及电力变换装置 Active CN110246887B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210555566.5A CN114864700A (zh) 2018-03-08 2019-03-01 半导体装置的制造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018-041442 2018-03-08
JP2018041442A JP7126361B2 (ja) 2018-03-08 2018-03-08 半導体装置、電力変換装置、及び、半導体装置の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN202210555566.5A Division CN114864700A (zh) 2018-03-08 2019-03-01 半导体装置的制造方法

Publications (2)

Publication Number Publication Date
CN110246887A CN110246887A (zh) 2019-09-17
CN110246887B true CN110246887B (zh) 2022-12-13

Family

ID=67701416

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201910155859.2A Active CN110246887B (zh) 2018-03-08 2019-03-01 半导体装置及电力变换装置
CN202210555566.5A Pending CN114864700A (zh) 2018-03-08 2019-03-01 半导体装置的制造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN202210555566.5A Pending CN114864700A (zh) 2018-03-08 2019-03-01 半导体装置的制造方法

Country Status (4)

Country Link
US (1) US10763760B2 (zh)
JP (1) JP7126361B2 (zh)
CN (2) CN110246887B (zh)
DE (1) DE102019201814A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102019008929A1 (de) * 2019-12-20 2021-06-24 Azur Space Solar Power Gmbh Gasphasenepitaxieverfahren
DE102019008931B4 (de) * 2019-12-20 2024-04-11 Azur Space Solar Power Gmbh Gasphasenepitaxieverfahren
DE102019008927B4 (de) * 2019-12-20 2024-04-11 Azur Space Solar Power Gmbh Gasphasenepitaxieverfahren
DE102020123847A1 (de) * 2020-09-14 2022-03-17 Infineon Technologies Ag Feldstoppgebiet enthaltende leistungs-halbleiterdiode

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5977611A (en) * 1997-04-04 1999-11-02 Siemens Aktiengesellschaft Power diode and hybrid diode, voltage limiter and freewheeling diode having the power diode
CN1691349A (zh) * 2004-04-28 2005-11-02 三菱电机株式会社 反向导通型半导体元件及其制造方法
CN101640222A (zh) * 2008-07-31 2010-02-03 三菱电机株式会社 半导体装置及其制造方法
CN102163626A (zh) * 2009-12-22 2011-08-24 Abb技术有限公司 具有新的保护环终端设计的功率半导体器件及其生产方法
CN104465792A (zh) * 2013-09-12 2015-03-25 株式会社东芝 半导体装置
CN108431962A (zh) * 2015-12-28 2018-08-21 三菱电机株式会社 半导体装置、半导体装置的制造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS539360A (en) 1976-07-12 1978-01-27 Fuji System Drink flavor enhancing composition
JP3321185B2 (ja) * 1990-09-28 2002-09-03 株式会社東芝 高耐圧半導体装置
US7842590B2 (en) * 2008-04-28 2010-11-30 Infineon Technologies Austria Ag Method for manufacturing a semiconductor substrate including laser annealing
JP5888214B2 (ja) * 2012-11-30 2016-03-16 富士電機株式会社 窒化物系化合物半導体装置およびその製造方法
JP2015002277A (ja) * 2013-06-17 2015-01-05 三菱電機株式会社 炭化珪素半導体装置
JP6234337B2 (ja) * 2014-07-03 2017-11-22 三菱電機株式会社 炭化珪素半導体装置
DE102015208097B4 (de) * 2015-04-30 2022-03-31 Infineon Technologies Ag Herstellen einer Halbleitervorrichtung durch Epitaxie
CN107710417B (zh) 2015-06-16 2021-06-11 三菱电机株式会社 半导体装置的制造方法
JP6683044B2 (ja) * 2016-07-12 2020-04-15 富士電機株式会社 半導体装置の製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5977611A (en) * 1997-04-04 1999-11-02 Siemens Aktiengesellschaft Power diode and hybrid diode, voltage limiter and freewheeling diode having the power diode
CN1691349A (zh) * 2004-04-28 2005-11-02 三菱电机株式会社 反向导通型半导体元件及其制造方法
CN101640222A (zh) * 2008-07-31 2010-02-03 三菱电机株式会社 半导体装置及其制造方法
CN102163626A (zh) * 2009-12-22 2011-08-24 Abb技术有限公司 具有新的保护环终端设计的功率半导体器件及其生产方法
CN104465792A (zh) * 2013-09-12 2015-03-25 株式会社东芝 半导体装置
CN108431962A (zh) * 2015-12-28 2018-08-21 三菱电机株式会社 半导体装置、半导体装置的制造方法

Also Published As

Publication number Publication date
CN110246887A (zh) 2019-09-17
JP2019160853A (ja) 2019-09-19
CN114864700A (zh) 2022-08-05
DE102019201814A1 (de) 2019-09-12
JP7126361B2 (ja) 2022-08-26
US10763760B2 (en) 2020-09-01
US20190280613A1 (en) 2019-09-12

Similar Documents

Publication Publication Date Title
CN110246887B (zh) 半导体装置及电力变换装置
CN110098253B (zh) 半导体装置、电力变换装置以及半导体装置的制造方法
US20200194554A1 (en) Silicon carbide semiconductor device, power converter, method of manufacturing silicon carbide semiconductor device, and method of manufacturing power converter
WO2021014570A1 (ja) 炭化珪素半導体装置、電力変換装置および炭化珪素半導体装置の製造方法
CN111819696B (zh) 碳化硅半导体装置、电力变换装置和碳化硅半导体装置的制造方法
CN108574015B (zh) 半导体装置及电力变换装置
CN107871777B (zh) 半导体装置和其制造方法以及电力变换系统
JP7138770B2 (ja) 炭化珪素半導体装置、電力変換装置および炭化珪素半導体装置の製造方法
JP7094439B2 (ja) 炭化珪素半導体装置および電力変換装置
WO2021038787A1 (ja) 炭化珪素半導体装置、電力変換装置および炭化珪素半導体装置の製造方法
JP2019110226A (ja) ＳｉＣ半導体装置、電力変換装置およびＳｉＣ半導体装置の製造方法
JP7207512B2 (ja) 半導体装置、電力変換装置及び半導体装置の製造方法
CN110828315B (zh) 半导体装置的制造方法及电力转换装置
US12027590B2 (en) Silicon carbide semiconductor device, power conversion device, and manufacturing method of silicon carbide semiconductor device
US20230215921A1 (en) Silicon carbide semiconductor device and power converter
US20220406897A1 (en) Silicon carbide semiconductor device, power conversion apparatus, and method for manufacturing silicon carbide semiconductor
CN117461143A (zh) 碳化硅半导体装置以及使用碳化硅半导体装置的电力变换装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant